KR20000059888A - Data-Line layout Structure of memory Device - Google Patents

Abstract

PURPOSE: An improved data line layout structure of a semiconductor memory device is provided to realize the speedup of read operation. CONSTITUTION: An SRAM memory device includes a plurality of memory cell arrays formed in a block structure, block column pass sections, and block sense amplifiers. When data read from a cell array(100a) of a first block is outputted to the block sense amplifier(150a) through the block column pass section(130a), the block sense amplifier(150a) senses and amplifies a signal through a section data line. In particular, when the signal amplified in the block sense amplifier(150a) is transmitted to a main sense amplifier(200), transmission buses, i.e., main data lines(MDL), pass over a cell array(100n) of a second block. The main data lines(MDL) are formed with a metal layer different from that of a bit line or word line. Furthermore, the main data lines(MDL) have the same direction as the bit line has.

Description

Data-line layout structure of memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a data line layout structure of a semiconductor memory device in which a main data line of a high density integrated high-speed SRAM passes over an upper portion of a cell array.

As the integration and performance of semiconductor memory is accelerated, the competition among manufacturers is getting fiercer. In particular, as the cycle time of the system is shortened, the speed of the embedded memory must be realized at high speed.

In order to develop a high integration and high speed chip, there is a problem of deterioration in applying a cell array configuration and a data line arrangement in a memory in a conventional manner, thereby presenting a cell array configuration and a data line arrangement of the present invention.

FIG. 1 is a layout diagram illustrating a structure of a conventional memory cell block and a data line, and illustrates a plurality of cell blocks 1 and a main data line 5 (MDL).

Each of the plurality of cell blocks 1 includes a plurality of cells capable of recording data, and a column path part 2 for opening and closing data by selecting a bit line pair of a specific cell according to a column selection signal output from a column decoder. ), A block sense amplifier 3 for sensing and amplifying the data output from the column path part 2 and outputting the amplified data to the main data line 5, and the column path part 2 and the section data line are connected to each other. And a write driver 4 (WD) for amplifying and transferring the data transferred from the main data line 5 to the column pass section 2.

In addition, the main data line 5 is formed between the main sense amplifier and the input / output buffer unit 6 and the block sense amplifier 3 and the write driver 4 so that the external pin data pad and the plurality of cells 1 are read / read. Allow light data to pass through each other.

As shown in the figure, it can be seen that the layout of the main data line 5 is installed without passing through the upper part of the cell block 1.

This method has been used in a memory device having a relatively low integration density and having a relatively small number of rows of one cell array 1.

However, as the degree of integration increases, the number of rows in one cell array 1 must also increase, and as the number of rows increases, the capacitance of the bit line increases, which acts as an obstacle to speeding up the data read operation.

An object of the present invention is to improve the performance of the chip design and the optimization of the cell array configuration, which has emerged with the development of high integration products in the layout implementation, which was not a problem in the low integration chip, the main data line of the high-speed SRAM, especially the high density integrated To provide a data line layout structure of a semiconductor memory device designed to pass over the top of the cell array.

In order to achieve the above object, an apparatus of the present invention is an SRAM memory device having a plurality of memory cell arrays integrated in a block structure and a column pass portion and a sense amplifier of each block, wherein the apparatus comprises: When the read data is output to the block sense amplifier through the column pass section, the block sense amplifier senses and amplifies the signal through the section data line, and when the signal amplified by the block sense amplifier is transferred to the main sense amplifier. And form the main data line such that the mobile bus passes over the cell array of the second block.

1 is a layout diagram illustrating a structure of a conventional memory cell block and a data line;

2 is a diagram illustrating a configuration of a cell array for explaining a memory cell block and a data line structure according to an embodiment of the present invention;

3 is a view showing in more detail the structure of part A of FIG.

4 is a block diagram showing the structure of part B of FIG. 3 in more detail;

5 is a view showing in detail the layout of the portion B of Figure 3 according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100a, 100n: cell block 130a, 130n: column path part (Y-PATH)

150a, 150b: Block Sense Amplifier (BSA) 170a, 170n: Light Driver (WD)

200: main sense amplifier and input / output buffer 300: data pad (external pin)

SDL: Section Dataline MDL: Main Dataline

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 2 is a diagram showing the configuration of a memory cell block according to the present invention, in which 1 mat (MAT) is composed of 32 mats having 1M bits, and 2304 columns (32 cells × 9IO × 8 blocks) for each mat. , 512 rows.

Although not shown in the drawing, the number of cells (word lines) driven by one row decoder is 288 cells.

In this highly integrated (16M byte, 32M byte, 64M byte) product, the number of rows per mat can be 2 ⁿ rows. However, when the number of rows increases, the parasitic capacitor of the bit line increases, so the read / write operation is performed. The time required to read / write data in a cell increases, which impedes the speed of memory products.

In the cell array of the same figure, the data of x9 is outputted and the total is 36x.

In this case, data of the upper two mats and the lower two mats are output through the same main data line MDL.

3 is a diagram illustrating the structure of part A of FIG. 2 in more detail, and includes column decoders 110a and 110n for receiving and decoding column addresses from each of the mats 100a and 100n and outputted from the column decoder. The column pass units 130a and 130n for selecting the bit lines according to the signal and transferring the data outputted from the write driver to the bit lines, and providing the data output from the column path units 130a and 130n through the section data lines. Block sense amplifiers 150a and 150n (BSA) which receive and amplify the signal, a write driver WD which receives write data from a main data line (not shown; MDL) and transfers the write data to the column path unit, and the block sense amplifiers 150a and 150a, 150n) and between the write drivers 170a and 170n and an external pin-in data pad to amplify an output signal of the block sense amplifiers 150a and 150n or to the write drivers 170a and 170n. The installation structure of the main sense amplifier and the input / output buffer 200 for transmitting the input signal is shown.

FIG. 4 is a block diagram illustrating the structure of part B of FIG. 3 in more detail, and shows a general S / R read / write block.

Through the plurality of memory cell arrays 100a, the column path unit 130a receiving data of the cell array through the bit line pairs BL and BLb according to the column address CSL, and the section data line SDLR. Block sense amplifier 150a for sensing and amplifying data output from the column path unit 130a, and main sense for receiving and amplifying data output through block sense amplifier 150a through a main data line MDL. The amplifier 210 and a data output buffer 230 buffering data output through the main sense amplifier 210 and outputting the data to a data pad perform a read operation.

In addition, a data pad 300 for inputting / outputting external data as a chip external pin, a data input buffer 250 for receiving and buffering data output from the data pad 300, and the data input buffer 250. After receiving and amplifying the data output from the main data line (MDL), and provides a light driver 170a for driving the data light, and the data output from the light driver 170a through the section data line (SDLW) In response to the column selection signal CSL, specific bit line pairs BL and BLb are designated, and then the column pass unit 130a writes to the specific memory cell 100a through the bit line pair.

FIG. 5 is a diagram illustrating a layout of part B of FIG. 3 according to an embodiment of the present invention, and illustrates a layout state of a main data line MDL.

As shown in the figure, one MAT consists of eight blocks, one block consists of nine IOs (input and output lines), and one IO consists of 32 columns × 512 rows of cells. At this time, there is one block sense amplifier 150a and one write driver 170a per IO.

That is, multiple cells of 1IO are commonly sensed and amplified by one block sense amplifier 150a.

The point of the present invention is that the main data line (MDL) to the output data of the block sense amplifier 150a to the main sense amplifier 200 passes through the top of the cell array (100n).

In this case, the output signal (main data line) of the block sense amplifier 150a passing through the upper part of the cell array 100n must be a metal different from the metals of the bit lines BL and BLb and the word line WL. It can be seen that the process is 3 or more metals.

The bit line BL direction of the cell array 100a is vertical, the word line WL direction is horizontal, and the upper portion of the cell array 100n is formed of a metal layer different from the bit lines BL and the word line WL. This main data line MDL is in the same vertical direction as the bit line BL.

Here, when the main data line MDL, which is an output signal bus of the block sense amplifier 150a, passes through the cell array 100n, the cell array 100n includes not only a cell but also a power line and a section word line decoder. .

Although only two block cells 100a and 100n are shown in the figure, the upper / lower mat and the repeated cell block are similarly designed as described above in the figure.

In this way, in the memory device using two stages of the sense amplifier, the output signal of the first sense amplifier block sense amplifier 150a goes to the main sense amplifier 200, which is the second sense amplifier, to be combined, and the main data line ( The MDL is designed to pass through the other cell array 100n in the same direction as the bit line BL and with a metal layer different from the bit line BL and the word line WL.

Therefore, in the present invention, by designing a data bus from the block sense amplifier to the main sense amplifier to pass through the upper part of the cell array, a high density integrated memory layout structure can be more simply and easily implemented to achieve high integration and high speed simultaneously. It can be effective.

Claims (3)

An SRAM memory device having a plurality of memory cell arrays integrated in a block structure, a column pass portion of each block, and a sense amplifier, When data read from the cell array of the first block is output to the block sense amplifier through the column pass section, the block sense amplifier senses and amplifies the signal through a section data line, and the signal amplified by the block sense amplifier is And a main data line when the mobile bus passes over the cell array of the second block when moved to the main sense amplifier. The method of claim 1, wherein the main data line, And a metal layer passing over the cell array of the second block, the metal layer being different from the bit line and the word line. The method of claim 1, wherein the main data line, A data line layout structure of a semiconductor memory device, characterized in that it is provided in the same direction as the bit line and perpendicular to the word line.