KR20000051680A - Ethod for forming bit line of semiconductor memory device - Google Patents

Abstract

PURPOSE: A method is provided to prevent a short between a bit line and gate electrode by avoiding an over-etching of a bit line contact pad. CONSTITUTION: A method comprises steps: a) depositing a bit line contact pad(108a), a material layer(109), and an inter dielectric layer(110) in sequence on a substrate(100); b) forming a bit line opening(112a, 112b) on each of cell array and core/peripheral region by etching a part of an inter dielectric layer selectively; c) forming a bit line spacer(114a,114b) on both walls of bit line openings, in which a bit line contact pad(108a) is exposed by etching a material layer; d) forming a bit line contact hole(116) by etching an inter dielectric layer; e) depositing a conductive layer(120) on overall substrate; and f) forming a bit line(120a) connected to a bit line contact pad on a cell array region as well as a b it line(120c) connected to a substrate on a core/peripheral region by etching a conductive layer.

Description

TECHNICAL FIELD The bit line forming method of a semiconductor memory device {ETHOD FOR FORMING BIT LINE OF SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a bit line of a semiconductor memory device.

As dynamic random access memory devices (DRAMs) are highly integrated, design rules are decreasing, and thus, overcoming the limitations of photolithography processes and securing misalign margins are more important problems. It is emerging.

FIG. 1 is a plan view of a cell array region in which a bit line of a conventional semiconductor memory device is formed, and FIG. 2 is a cell array region and a core / peripheral circuit region (not shown in FIG. 1) cut along the line A1-A1 'of FIG. 1. ) Is a cross-sectional view.

Referring to FIGS. 1 and 2, a method of forming a bit line of a conventional DRAM is first active on a semiconductor substrate 10 having a cell array region and a core / periphery region. A device isolation layer 12 is formed to define an active region 11 and an inactive region.

A word line 13 including a gate electrode 13a and a gate spacer 13b is formed to pass through the active region 11. Next, an interlayer insulating layer 16 is deposited on the entire surface of the semiconductor substrate 10 including the word line 13. The film formed on the semiconductor substrate 10 under the interlayer insulating film 16 in the core / peripheral circuit region is a silicon nitride film 14, and an etch stopping layer during an etching process for forming a subsequent bit line contact 22b. Will act as).

The bit line contact pads 18 and the storage electrode contact pads 19 are formed to penetrate the interlayer insulating layer 16 and to be electrically connected to the active regions 11 between the word lines 13. The bit line contact pads 18 and the storage electrode contact pads 19 are simultaneously formed by, for example, a self-aligned contact forming process well known in the art.

The interlayer insulating layer 20 is deposited on the entire surface of the semiconductor substrate 10 including the contact pads 18 and 19. A bit line contact 22a electrically connected to the bit line contact pad 18 of the cell array region through the interlayer insulating layer 20 and electrically connected to an active region 11 of the core / peripheral circuit region. Bit line contacts 22b are formed respectively.

Subsequently, a conductive film is deposited and patterned on the interlayer insulating film 20 to form bit lines 24a to 24c electrically connected to the bit line contacts 22a and 22b.

However, when the bit line contacts 22a and 22b are simultaneously formed in the cell array region and the core / peripheral circuit region, the depths of the bit line contact holes in the cell array region and the core / peripheral circuit region may vary. A problem arises in that the bit line contact pad 18 is excessively etched, as indicated by reference numeral 26. Excessive etching of the bit line contact pads 18 causes a short between the bit lines 24a and 24b and the gate electrode 13a.

In addition, the limitation of the bit line pattern that can be implemented by current photolithography exposure equipment is a big obstacle in reducing the size of the cell. As a result, since the width of the bit lines cannot be reduced, the misalignment margin of subsequent storage node contacts and the bit lines 24a to 24c becomes very small.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problems, while simultaneously forming bit line contacts in the cell array region and the core / peripheral circuit region, while preventing excessive etching of the bit line contact pads, thus preventing bit lines and It is an object of the present invention to provide a bit line forming method of a semiconductor memory device capable of preventing a short circuit of a gate electrode.

Another object of the present invention is to provide a method of forming a bit line of a semiconductor memory device which can overcome the limitation of the bit line defined by the photolithography process and increase the misalignment margin of the bit line and the storage node contact.

1 is a plan view of a cell array region in which a bit line of a conventional semiconductor memory device is formed;

FIG. 2 is a cross-sectional view of a cell array region and a core / periphery region (not shown in FIG. 1) cut along the A1-A1 'line of FIG.

3 is a plan view of a cell array region in which bit lines are formed in a semiconductor memory device according to an embodiment of the present invention;

4A through 4D are cross-sectional views of a cell array region and a core / peripheral circuit region (not shown in FIG. 3) cut along the A2-A2 'line of FIG. 3, sequentially showing the processes of the bit line forming method.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 11, 101: active region

12, 102: device isolation film 14, 104, 109: silicon nitride film

16, 20, 106, 110: interlayer insulating film 18, 108a: bit line contact pad

22a, 22b, 118a, 118b: bit line contacts

24a-24c, 120a-120c: bit line

112a, 112b: bit line opening 114a, 114b: bit line spacer

116: bit line contact hole 120: bit line conductive film

According to the present invention for achieving the above object, a method of forming a bit line of a semiconductor memory device includes a semiconductor substrate having a cell array region and a core / peripheral circuit region, and a cell array region through an interlayer insulating film formed on the semiconductor substrate. In a bit line forming method of a semiconductor memory device including a bit line contact pad formed to be electrically connected to a semiconductor substrate of the semiconductor device, a material film and an interlayer insulating film are sequentially deposited on the entire surface of the semiconductor substrate including the bit line contact pad. In this case, the material film is formed of a film having an etching selectivity with the interlayer insulating film. The interlayer insulating layer is partially etched to expose a portion of the material layer to form respective bit line openings in the cell array region and the core / peripheral circuit region. Bit line spacers are formed on both sidewalls of the bit line opening. In this case, when the bit line spacer is formed, the material layer under the bit line opening is etched to expose the bit line contact pad. The interlayer insulating layer is etched to expose a portion of the semiconductor substrate under the bit line opening of the core / peripheral circuit region to form a bit line contact hole. A conductive film is deposited on the entire surface of the semiconductor substrate including the bit line opening and the bit line contact hole. Planar etching of the conductive layer to expose an upper portion of the interlayer insulating layer to form a bit line electrically connected to the bit line contact pad in the cell array region, and at the same time to electrically connect the semiconductor substrate to the core / peripheral circuit region. Form a bit line. This prevents a short circuit between the bit line and the gate electrode, and increases the misalignment margin of the bit line and the storage electrode contact.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a plan view of a cell array region in which a bit line is formed in a semiconductor memory device according to an exemplary embodiment of the present invention, and FIGS. 4A to 4D illustrate a cell array region and a core / peripheral cut along a line A2-A2 'of FIG. 3. A cross-sectional view of a circuit region (not shown in FIG. 3), which is a flowchart showing the processes of the bit line forming method sequentially.

Referring to FIGS. 3 and 4E, in the method of forming a bit line of a novel semiconductor memory device according to an embodiment of the present invention, after a bit line contact pad is formed, a silicon nitride film having an interlayer insulating film and an etching selectivity is deposited thinly. . This silicon nitride film is used as an etch stop layer in forming the bit line openings, thereby preventing excessive etching of the bit line contact pads in the cell array region. By forming bit line spacers with silicon nitride films on both sidewalls of the bit line openings, it is possible to overcome the limitations of the bit lines defined by the photolithography process and increase the misalignment margin of the bit lines and the storage electrode contacts.

In Figs. 4A to 4E, the same reference numerals are given to components that have the same functions as the components of the semiconductor memory device shown in Fig. 3.

Referring to FIG. 4A, a method of forming a bit line in a semiconductor memory device according to an embodiment of the present invention may first include an active region 101 and an inactive region on a semiconductor substrate 100 having a cell array region and a core / peripheral circuit region. In order to define the device isolation layer 102 is formed. As shown in FIG. 3, the active region 101 may be formed in a straight shape or may be formed in a 'T' shape. In addition, the device isolation layer 102 is formed by, for example, a shallow trench isolation method.

An ion implantation process is performed to form a well on the active region 101 and to adjust a threshold voltage of a transistor.

As shown in FIG. 3, a word line 103 including a gate electrode 103a and a gate spacer 103b is formed to pass through the active region 101. An interlayer insulating layer 106 is formed on the entire surface of the semiconductor substrate 100 including the word line 103.

The bit line contact pads 108a and the storage electrode contact pads 108b are formed to penetrate the interlayer insulating layer 106 and to be electrically connected to the active regions 101 of the cell array region.

The contact pads 108a, 108b are formed simultaneously, for example, by a self-aligned contact forming process well known in the art.

In this case, the bit line contact pads 108a are formed to extend from the active region 101 to overlap a portion of the device isolation layer 102.

After the thin material film is deposited on the interlayer insulating film 106 including the contact pads 108a and 108b, the interlayer insulating film 110 is subsequently deposited. The material film 109 is a film material having an etching selectivity with the subsequent interlayer insulating film 110. For example, the material film 109 is a silicon nitride film 109 and is deposited within a thickness range of 300 kPa to 500 kPa.

The interlayer insulating film 110 is deposited to a thickness of about 2000 mW.

The interlayer insulating layer 110 of the cell array region and the core / peripheral circuit region is partially etched using a photolithography process for forming a bit line, thereby forming bit line openings 112a and 112b, respectively. In this case, the silicon nitride film 109 is used as an etch stop layer.

The bit line opening 112a of the cell array region is for simultaneously forming a bit line contact and a bit line, the width of which is less than or equal to the width of a conventional bit line.

A thin material layer, for example, a silicon nitride layer is deposited on the interlayer insulating layer 110 including the bit line openings 112a and 112b. The silicon nitride layer is etched through an etch back process to form bit line spacers 114a and 114b on both sidewalls of the bit line openings 112a and 112b.

The bit line spacers 114a and 114b are used to increase the misalignment margin of the bit line and the storage electrode contacts, and the silicon nitride film for forming the bit line spacers 114a and 114b is deposited within a thickness range of 300 kV to 500 kV. .

In this case, the bit line spacers 114a and 114b are performed by applying an etching time such that the silicon nitride layer 109 under the bit line openings 112a and 112b is removed. That is, while the bit line spacers 114a and 114b are formed, a portion of the bit line contact pad 108a is exposed.

As such, the bit line contact pads 108a under the bit line opening 112a of the cell array region are exposed, thereby skipping further photolithography processes for forming bit line contacts in the cell array region. do.

In FIG. 4C, a photolithography process and an interlayer insulating film 106 etching process for forming a bit line contact in the core / peripheral circuit region are performed to form a bit line contact hole 116 under the bit line opening 112b. ) Is formed.

In this case, the bit line contact hole 116 is preferably a material layer formed on the semiconductor substrate 100 in the core / peripheral circuit region before deposition of the interlayer dielectric layer 106, for example, the silicon nitride layer 104 is etched stop layer. It is formed using.

A conductive film 120 for forming a bit line is deposited on the entire surface of the semiconductor substrate 100 including the bit line openings 112a and 112b and the bit line contact holes 116 to have a thickness of about 3000 μs. The conductive film 120 is formed of, for example, a polysilicon layer or a tungsten layer. A barrier layer (not shown), such as a Ti / TiN film, may be further formed before the conductive film 120 is formed. In this case, a titanium silicide layer may be further formed under the bit line contact hole 116 through a silicidation process.

Finally, the conductive layer 120 is flattened and etched until the upper surface of the interlayer dielectric layer 110 is exposed through a chemical mechanical polishing (CMP) process, and as shown in FIG. 4E, the bit is formed in the cell array region. The bit line contact 118a and the bit line 120a electrically connected to the line contact pad 108a are simultaneously formed, and the bit line 120b passing over the interlayer insulating film 106 is formed at the same time. In addition, a bit line contact 118b and a bit line 120c electrically connected to the active region 101 of the core / peripheral circuit region are simultaneously formed.

As described above, the bit line contact and the bit line of the DRAM according to the present invention are simultaneously formed through a dual damascene process. In other words, the insulating layer is etched to form a mold layer having a bit line contact and an opening for forming the bit line, and then the opening is filled with a conductive film and planarized etched.

In the present invention, the bit line contacts and the bit lines are simultaneously formed in a dual damascene process as described above. As a result, misalignment of bit lines and bit line contacts can be minimized.

By further forming an etch stop layer on the bit line contact pad with a silicon nitride film, it is possible to simultaneously form the bit line contact in the cell array region and the core / peripheral circuit region while preventing excessive etching of the bit line contact pad. Therefore, the short circuit between the bit line and the gate electrode can be prevented.

In addition, by forming the silicon nitride film spacers on both sidewalls of the bit line opening, it is possible to overcome the limitation of the bit line defined by the photolithography process and to increase the misalignment margin of the bit line and the storage electrode contact. .

Claims (3)

The semiconductor of the cell array region is formed through a semiconductor substrate 100 having a cell array region and a core / periphery region, and an interlayer insulating layer 106 formed on the semiconductor substrate 100. In the method of forming a bit line of a semiconductor memory device including a bit line contact pad (108a) formed to be electrically connected to the substrate 100, A material layer 109 and an inter layer dielectric 110 are sequentially deposited on the entire surface of the semiconductor substrate 100 including the bit line contact pads 108a. Forming a film having an etch selectivity with the interlayer insulating film 110; Forming the bit line openings 112a and 112b in the cell array region and the core / peripheral circuit region by partially etching the interlayer insulating layer 110 to expose a portion of the material layer 109. step; Bit line spacers 114a and 114b are formed on both sidewalls of the bit line openings 112a and 112b, and the material layer under the bit line openings 112a and 112b when the bit line spacers 114a and 114b are formed. 109 etching to expose the bit line contact pads 108a; Etching the interlayer insulating layer (106) to expose a portion of the semiconductor substrate (100) below the bit line opening (112b) of the core / peripheral circuit region to form a bit line contact hole (116); Depositing a conductive film (120) over the semiconductor substrate (100) including the bit line openings (112a, 112b) and bit line contact holes (116); And The conductive layer 120 is planarized and etched to expose the upper portion of the interlayer insulating layer 110, thereby forming a bit line 120a electrically connected to the bit line contact pad 108a in the cell array region. And forming a bit line (120c) electrically connected to the semiconductor substrate (100) in the core / peripheral circuit region. The method of claim 1, And the bit line spacers (114a, 114b) are formed of the same film quality as the material film (109). The method of claim 1, And the material film (109) is a silicon nitride film.