KR20000051266A - Apparatus for VSB filter by correcting clock delay error in VSB demodulator - Google Patents

Abstract

PURPOSE: A digital filter device compensating for a clock delay error of a vestigial sideband demodulator is provided to compensate for a clock delay error due to a design for a digital filter using multi clocks, whereby the digital filter is able to perform its operation without sharp increase in gate number regardless of relatively larger clock skew. CONSTITUTION: A digital filter device compensating for a clock delay error of a vestigial sideband demodulator comprises: first and second skew delayers(71,72) delaying output data from a plurality of adders by a half cycle of a system clock; a first multiplexer(73) multiplexing outputs of two adders among the plurality of adders delayed in the first and second skew retarders(71,72) and outputting the multiplexed data according to a selected signal; a second multiplexer(74) multiplexing a vestigial sideband filter coefficient and outputting it according to a selected signal; first and second retarders(75,76) delaying outputs of the first and second multiplexers(73,74) by a cycle of each system clock; a multiplexer(77) multiplexing outputs of the first and second delayers(75,76); third retarder(78) delaying an output of the multiplexer(77) by a cycle of 2 system clock; fourth delayer(79) delaying an output of the third delayer(78) for a cycle of the 2 system clock; an adder(80) adding outputs of the third and fourth delayers(78,79); fifth delayer(81) delaying an output of the adder(80) by a cycle of the 2 system clock; third skew delayer(82) delaying data of the fifth delayer(81) by a half cycle of the system clock; and sixth delayer latching an output of the third skew delayer(82) in the system clock operation and outputting the data.

Description

Digital filter device that compensates for clock delay error of residual sideband demodulator {Apparatus for VSB filter by correcting clock delay error in VSB demodulator}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VSB (Vestigial SideBand) demodulator used in HDTV (High Definition TeleVision, High Definition Television), and the like. The present invention relates to a digital filter device that compensates for a clock delay error of a residual sideband demodulator that operates regardless of a relatively large clock skew without a large increase of.

In general, HDTV, such as the GA (Grand Alliance) standard, uses a phase tracking loop. The HDTV is a TV that realizes higher definition and larger screen size by doubling the number of scanning players and increasing the aspect ratio to 16: 9 (4: 3 for general television) compared to the general television.

1 is a block diagram of a VSB demodulator of a general HDTV receiver.

As shown therein, the RF / IF front-end unit 1 extracts the intermediate frequency IF from the high frequency RF received through the antenna, and the RF / IF front-end unit 1 outputs the RF / IF front-end unit 1. An analog / digital converter 2 for sampling, quantizing, and converting an intermediate frequency into a digital signal; and a delay unit for delaying the output of the analog / digital converter 2 to output an in-phase I-channel signal. (3); A VSB filter (4) for VSB filtering the output of the analog / digital converter (2); A complex multiplier (5) for complex multiplying the I and Q signals output from the delay section (3) and the VSB filter (4); An error discriminating unit 6 which receives the complex multiplied I and Q channel signals from the complex multiplier 5 and determines an error to output a phase error; A phase accumulator (8) for accumulating the phase error output from the error discriminator (6); It consists of a numerically controlled oscillator 9 which receives the accumulated phase from the phase accumulator 8, compensates for and stores the sine and cosine of the phase, and outputs it to the complex multiplier 5.

The channel equalizer configured as described above extracts the intermediate frequency from the high frequency received from the RF-IF front-end unit 1, and the analog / digital converter 2 operates at a sampling rate of 21.52 MHz, and converts the analog / digital converter. The output of the section 2 is input to the delay section 3 and the VSB filter 4. The output of the VSB filter 4 is input to the complex multiplier 5 together with the VCO output, and the output of the complex multiplier 5 is input to the phase tracker.

In other words, the input I channel signal is first gain-adjusted and then passed through the VSB filter 4 to produce an estimate of the Q channel signal. This is possible because the I and Q components of the VSB (Vestigial SideBand) modulated signal are in a linear transformation similar to the Hilbert transform. The complex signal consisting of the I channel signal input to the phase tracking loop and the Q channel signal which is the output of the VSB filter 4 is compensated for by the complex multiplier 5.

2 is a block diagram of a conventional VSB filter.

The VSB filter can be implemented as a finite impulse response (FIR) filter having m taps, and has the following characteristics.

First, the coefficient of (m-1) / 2 taps including the center tap is 0 among the plurality of delay parts 11 to 25 which are m taps. Therefore, these (m-1) / 2 taps only act as delay buffers and are not used to calculate the output of the filter. That is, the current output of the filter is determined by the values in the remaining (m + 1) / 2 taps.

Second, the left and right tabs are opposite signs with respect to the center tap, and the absolute values are the same. When m = 31, the coefficient of the VSB filter may be represented as shown in the table shown in FIG. Therefore, the above properties can be used to reduce the number of multipliers used in the filter.

Fig. 2 is an example of the case of m = 31, which is designed using only 30 shift registers 11 to 25, 8 multipliers 34 to 41, and 15 two-input adders 26 to 33 (42 to 48). Shown is the general structure of a tap VSB filter. Where h0, h2, h4,... … , h14 means the coefficient of the VSB filter. Passing this VSB filter outputs an in-phase I signal and a Q signal in quadrature.

3 is a block diagram of a conventional digital filter.

As shown therein, a plurality of delay units 11 to 25 for receiving and delaying data and outputting in-phase signals; A plurality of adders 26 to 33 which receive the input data and data of the plurality of delay units 11 to 25 and add them respectively; First to fourth multiplexed / multiplied / added cells (51 to 54) for receiving the outputs of the two adders among the plurality of adders (26 to 33), respectively, and multiplying VSB filter coefficients to output the added values; A first cell adder (55) for adding output values of the first and second multiplexed / multiplied / added cells (51, 52); A second cell adder (56) for adding output values of the third and fourth multiplexed / multiplied / added cells (53) (54); A third cell adder (57) for adding output values of the first and second cell adders (55); A quadrature phase delay unit 58 outputs a quadrature phase signal by delaying the output of the third cell adding unit 57.

FIG. 4 is a detailed block diagram of the multiplex / multiply / add cells 51 to 54 in FIG.

As shown therein, a delay buffer 61 for delaying and storing the input system clock; A first multiplexer 62 for receiving and multiplexing the outputs of two adders of the plurality of adders 26 to 33; A second multiplexer 63 configured to receive and multiplex VSB filter coefficients; First and second delay units (64) (65) for delaying outputs of the first and second multiplexers (62, 63) for a predetermined period, respectively; A multiplier (66) for multiplying the outputs of the first and second delay units (64) (65); A third delay unit 67 for delaying the output of the multiplication unit 66; A fourth delay unit 68 for delaying the output of the third delay unit 67 for a predetermined time; An adder (69) for adding the outputs of the third and fourth delay units (67, 68); And a fifth delay unit 70 for delaying and outputting the output of the adder 69 for a predetermined time.

FIG. 5 is a timing diagram illustrating a clock delay error in FIG. 4.

Here, the operations of the plurality of delay units 11 to 25 and the plurality of adders 26 to 33 are the same as those described above. The first to fourth multiplexed / multiplied / added cells 51 to 54 include (26) and (27), (28) and (29), (30) and (31), (32) and (33). The outputs of the adders are input respectively. Since the structures and operations of the first to fourth multiplexed / multiplied / added cells 51 to 54 are the same, only the case of the first multiplexed / multiplied / added cells 51 will be described.

The delay buffer 61 delays and stores the input system clock. The system clock sys_clk is an input data rate clock, and 2sys_clk is a clock twice the input data rate. The slt output from the delay buffer 61 is a selection signal of the multiplexer obtained by delaying sys_clk.

Thus, the first multiplexer receives and multiplexes the data output from the adders 26 and 27, and the second multiplexer 63 multiplexes the VSB filter coefficients. The first and second delay units DFFA0 (DFFB0) 64 and 65 respectively delay the outputs of the first and second multiplexers 62 and 63 during the period of two system clocks. In 66, the outputs of the first and second delay units 64 and 65 are multiplied. That is, the multiplexers 62 and 63 alternately select ina and inb, ha and hb to perform two multiplications within a sys_clk period.

The third delay unit (DFF1) 67 delays the output of the multiplier 66 for a period of two system clocks, and the fourth delay unit (DFF2) 68 controls the third delay unit (DFF1) 67. Delays the output of A for two system clock cycles. The adder 69 adds data delayed for the period of two system clocks, respectively, and the fifth delay unit DFF3 70 delays the output of the adder 69 for one system clock and outputs the delayed data.

The output data has the same result as the operation using two multipliers. Then, the first and second cell adders 55 and 56 add the output values of the first to fourth multiplexed / multiplied / added cells 51 to 54, respectively, and the third and second cell adders 57 and 57 respectively. The output value of the cell adder 55 is added, and the quadrature phase delay unit 58 delays the output of the third cell adder 57 to output the quadrature phase signal.

One efficient way to reduce the number of gates in designing an Applicable Specific Integrated Circuit (ASIC) such as a digital filter that requires many computations is resource sharing using multiple clocks. When using multiple clocks in an ASIC design, the effect of clock skew must be considered.

Between different clock-trees, a mismatch in time delay can occur, as in FIG. This time delay is called clock skew, and there is a risk that the circuit will behave completely differently from the designer's intent if the clock is not properly compensated. To compensate for this clock skew, a method of delaying data by inserting a buffer between the latches and the latches has been attempted.

However, in order to achieve the desired time delay in ASICs with very short signal delay times, a very large number of buffers must be overlapped and inserted, which leads to an insignificant increase in the number of gates.

It was also cumbersome to manually find the critical path where clock skew occurs and manually insert a buffer.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, and an object of the present invention is to compensate for a clock delay error occurring in the design of a digital filter using multiple clocks, so that a relatively large number of gates is not increased. The present invention provides a digital filter device that compensates for a clock delay error of a residual sideband demodulator that can operate regardless of a clock skew.

In order to achieve the above object, the digital filter device that compensates for the clock delay error of the residual sideband demodulator according to the present invention,

First and second skew delay units respectively delaying data output from the plurality of adders by a half cycle of the system clock; A first multiplexer for receiving multiplexed outputs of the plurality of adders delayed by the first and second skew delay units and outputting multiplexed data according to a selection signal; A second multiplexer which receives the VSB filter coefficients and multiplexes them and outputs them according to a selection signal; First and second delay units for delaying outputs of the first and second multiplexers for a period of two system clocks, respectively; A multiplier for multiplying outputs of the first and second delay parts; A third delay unit for delaying the output of the multiplier for a period of two system clocks; A fourth delay unit for delaying the output of the third delay unit for a period of two system clocks; An adder for adding outputs of the third and fourth delay units; A fifth delay unit delaying the output of the adder for a period of two system clocks and outputting the delayed unit; A third skew delay unit configured to delay data of the fifth delay unit by a half cycle of a system clock; Technical features of the present invention include a sixth delay unit configured to receive the output of the third skew delay unit, operate as a system clock, latch, and output data.

1 is a block diagram of a typical VSB demodulator,

2 is a block diagram of a conventional digital filter,

3 is a block diagram of a conventional digital filter,

4 is a detailed block diagram of a multiplex / multiply / add cell in FIG.

5 is a timing diagram showing a clock delay error in FIG. 4;

6 is a block diagram of a digital filter device that compensates for a clock delay error of a residual sideband demodulator.

7 is a timing diagram of FIG. 6.

<Explanation of symbols for the main parts of the drawings>

71, 72, 82,: first to third skew delay unit

75, 76, 78, 79, 81, 83: first to sixth delay unit

73, 74: first and second multiplexer

77: multiplication unit

80: addition unit

Hereinafter, an embodiment according to the technical idea of the digital filter device for compensating for the clock delay error of the residual sideband demodulator according to the present invention will be described in detail with reference to the accompanying drawings.

First, in order to solve the problem of clock skew caused by using multiple clocks in order to reduce the number of gates in the ASIC design of the digital filter, a suitable time delay occurs in a data path that may be affected by clock skew. It is possible to design digital filters that operate independently of relatively large clock skews without a significant increase in number.

6 is a block diagram of a digital filter device that compensates for a clock delay error of a residual sideband demodulator.

As shown therein, the first and second skew delay units 71 and 72 respectively delay the data output from the plurality of adders 26 to 33 by a half cycle of the system clock; A first multiplexing output of two adders of the plurality of adders 26 to 33 delayed by the first and second skew delayers 71 and 72 to output multiplexed data according to a selection signal; Section 73; A second multiplexer 74 which receives the VSB filter coefficients and multiplexes them and outputs them according to a selection signal; First and second delay units (75) (76) for delaying the outputs of the first and second multiplexers (73) (74) for a period of two system clocks, respectively; A multiplier 77 for multiplying the outputs of the first and second delay units 75 and 76; A third delay unit (78) for delaying the output of the multiplier unit (77) for a period of two system clocks; A fourth delay unit (79) for delaying the output of the third delay unit (78) for a period of two system clocks; An adder (80) for adding the outputs of the third and fourth delay units (78, 79); A fifth delay unit (81) for delaying and outputting the output of the addition unit (80) for a period of two system clocks; A third skew delay unit (82) for delaying data of the fifth delay unit (81) by a half cycle of a system clock; The sixth delay unit 83 receives the output of the third skew delay unit 82, operates as a system clock, latches it, and outputs data.

7 is a timing diagram of FIG. 6.

Thus, the present invention inserts a latch that operates as a slt signal in a signal path affected by clock skew in the structure as shown in FIG. Here, ina and inb are outputs of the plurality of adders 26 to 33, as shown in FIGS. 2 and 3, and ha and hb mean the coefficients of the VSB filters to be multiplied by their respective inputs.

sys_clk is the input data rate clock and 2sys_clk is twice the clock of the input data rate. The slt input to the multiplexers 73 and 74 is a selection signal of the multiplexers 73 and 74 and is a signal obtained by delaying sys_clk by a half cycle of 2sys_clk.

The multiplexers 73 and 74 alternately select ina and inb, ha and hb to perform two multiplications in the multiplier 77 within one period of sys_clk, and latch them into the third delay unit (DFF1) 78, The adder 80 adds the output of the third delay unit DFF1 78 and the output of the fourth delay unit DFF2 79 that delayed this signal once to 2sys_clk, and then adds the fifth delay unit DFF3. At 81, latch to 2sys_clk.

When the sys_clk is latched by the third skew delay unit (DFF4) 82 operating in slt, which is a signal delayed by a half cycle of 2sys_clk, and then latched by the sixth delay unit (DFF5) 83 operating in sys_clk, two latches are performed. You will get the same result as if you used a multiplier. This data flow is shown in FIG.

As such, the present invention compensates the clock delay error that occurs in the design of a digital filter using multiple clocks, so that the clock operates without relatively increasing the number of gates.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. That is, the present invention can be used for effective design of a VSB filter or the like used in a VSB demodulator and can be applied to the design of a general digital filter. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the digital filter device that compensates for the clock delay error of the residual sideband demodulator according to the present invention is designed to compensate for the clock delay error generated by using multiple clocks to reduce the number of gates in the ASIC design of the digital filter. By allowing a proper time delay to occur in a data path that can be affected by clock skew, there is an effect that it can operate regardless of a relatively large clock skew without a large increase in the number of gates.

Claims (1)

In the digital filter device of the residual sideband demodulator, First and second skew delay units 71 and 72 for delaying the data output from the plurality of adders 26 to 33 by a half cycle of the system clock, respectively; A first multiplexing output of two adders of the plurality of adders 26 to 33 delayed by the first and second skew delayers 71 and 72 to output multiplexed data according to a selection signal; Section 73; A second multiplexer 74 which receives a VSB filter coefficient and outputs the multiplexed coefficients according to a selection signal; First and second delay units (75) (76) for delaying the outputs of the first and second multiplexers (73) (74) for a period of two system clocks, respectively; A multiplier 77 for multiplying the outputs of the first and second delay units 75 and 76; A third delay unit (78) for delaying the output of the multiplier unit (77) for a period of two system clocks; A fourth delay unit (79) for delaying the output of the third delay unit (78) for a period of two system clocks; An adder (80) for adding the outputs of the third and fourth delay units (78, 79); A fifth delay unit (81) for delaying and outputting the output of the addition unit (80) for a period of two system clocks; A third skew delay unit (82) for delaying data of the fifth delay unit (81) by a half cycle of a system clock; Compensating the clock delay error of the residual side band demodulator comprising a sixth delay unit 83 receives the output of the third skew delay unit 82 to operate as a system clock and latch and then output data. Digital filter device.