KR20000050507A - Apparatus for VSB filtering in VSB demodulator - Google Patents

Abstract

PURPOSE: A vestigial sideband filtering apparatus is provided to reduce the hardware volume by decreasing the number of multipliers in the VSB filter having plural taps used for the VSB demodulator. CONSTITUTION: A plurality of delay units(11-25) input and delay data to output an in-phase signal. Plural adders(26-33) input and add the inputted data and the data of the plural delay units(11-25). First to fourth multiplexing/multiplying/adding cells(51-54) input the outputs of two adders from the plural adders(26-33), multiplies the inputted outputs by a VSB filter coefficient, and adds the multiplied and inputted outputs for output values. A first cell adder(55) adds the output values of the first and second multiplexing/multiplying/adding cells(51-54). A second cell adder(56) adds the output values of the third and fourth multiplexing/multiplying/adding cells(51-54).

Description

Residual sideband filter device for residual sideband demodulator {Apparatus for VSB filtering in VSB demodulator}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a VSB (Vestigial SideBand) demodulator used in HDTV (High Definition TeleVision, High Definition Television), and the like. A sideband filter device.

In general, HDTV, such as the GA (Grand Alliance) standard, uses a phase tracking loop. The HDTV is a TV that realizes higher definition and larger screen size by doubling the number of scanning players and increasing the aspect ratio to 16: 9 (4: 3 for general television) compared to the general television.

1 is a block diagram of a VSB demodulator of a general HDTV receiver.

As shown therein, the RF / IF front-end unit 1 extracts the intermediate frequency IF from the high frequency RF received through the antenna, and the RF / IF front-end unit 1 outputs the RF / IF front-end unit 1. An analog / digital converter 2 for sampling, quantizing, and converting an intermediate frequency into a digital signal; and a delay unit for delaying the output of the analog / digital converter 2 to output an in-phase I-channel signal. (3); A VSB filter (4) for VSB filtering the output of the analog / digital converter (2); A complex multiplier (5) for complex multiplying the I and Q signals output from the delay section (3) and the VSB filter (4); An error discriminating unit 6 which receives the complex multiplied I and Q channel signals from the complex multiplier 5 and determines an error to output a phase error; A phase accumulator (8) for accumulating the phase error output from the error discriminator (6); It consists of a numerically controlled oscillator 9 which receives the accumulated phase from the phase accumulator 8, compensates for and stores the sine and cosine of the phase, and outputs it to the complex multiplier 5.

The channel equalizer configured as described above extracts the intermediate frequency from the high frequency received from the RF-IF front-end unit 1, and the analog / digital converter 2 operates at a sampling rate of 21.52 MHz, and converts the analog / digital converter. The output of the section 2 is input to the delay section 3 and the VSB filter 4. The output of the VSB filter 4 is input to the complex multiplier 5 together with the VCO output, and the output of the complex multiplier 5 is input to the phase tracker.

In other words, the input I channel signal is first gain-adjusted and then passed through the VSB filter 4 to produce an estimate of the Q channel signal. This is possible because the I and Q components of the VSB (Vestigial SideBand) modulated signal are in a linear transformation similar to the Hilbert transform. The complex signal consisting of the I channel signal input to the phase tracking loop and the Q channel signal which is the output of the VSB filter 4 is compensated for by the complex multiplier 5.

2 is a block diagram of a conventional VSB filter, and FIG. 3 is a table showing tap coefficients of a general VSB filter.

The VSB filter can be implemented as a finite impulse response (FIR) filter having m taps, and has the following characteristics.

First, the coefficient of (m-1) / 2 taps including the center tap is 0 among the plurality of delay parts 11 to 25 which are m taps. Therefore, these (m-1) / 2 taps only act as delay buffers and are not used to calculate the output of the filter. That is, the current output of the filter is determined by the values in the remaining (m + 1) / 2 taps.

Second, the left and right tabs are opposite signs with respect to the center tap, and the absolute values are the same. When m = 31, the coefficient of the VSB filter may be represented as shown in the table shown in FIG. Therefore, the above properties can be used to reduce the number of multipliers used in the filter.

Fig. 2 is an example of the case of m = 31, which is designed using only 30 shift registers 11 to 25, 8 multipliers 34 to 41, and 15 two-input adders 26 to 33 (42 to 48). Shown is the general structure of a tap VSB filter. Where h0, h2, h4,... … , h14 means the coefficient of the VSB filter. Passing this VSB filter outputs an in-phase I signal and a Q signal in quadrature.

However, such a conventional VSB filter has a problem in that the number of multipliers occupying the largest volume in hardware design is (m + 1) / 4, which greatly increases the volume of hardware.

Accordingly, the present invention has been proposed to solve the above conventional problems, and an object of the present invention is to reduce the number of multipliers to (m + 1) / 8 in a VSB filter having m taps used in a VSB demodulator. The present invention provides a residual sideband filter device for a residual sideband demodulator capable of greatly reducing hardware volume.

In order to achieve the above object, a residual sideband filter device for a residual sideband demodulator according to the present invention,

A plurality of delay units for receiving data and delaying the data to output an in-phase signal; A plurality of adders which receive the input data and data of the plurality of delay units and add them respectively; First to fourth multiplexed / multiplied / added cells which respectively receive outputs of two adders from the plurality of adders and multiply VSB filter coefficients to output the added values; A first cell adder for adding output values of the first and second multiplexed / multiplied / added cells; A second cell adder for adding output values of the third and fourth multiplexed / multiplied / added cells; A third cell adder for adding output values of the first and second cell adders; It is characterized in that the technical configuration consists of a quadrature phase delay unit for outputting a quadrature phase signal by delaying the output of the third cell adding unit.

1 is a block diagram of a typical VSB demodulator,

2 is a block diagram of a conventional VSB filter;

3 is a table showing tap coefficients of a typical VSB filter.

4 is a block diagram of a VSB filter according to the present invention;

FIG. 5 is a detailed block diagram of a multiplex / multiply / add cell in FIG. 4;

6 is a timing diagram of FIG.

<Description of the code | symbol about the principal part of drawing>

11 to 25: delay unit 26 to 33: addition unit

51 to 54: multiplex / multiply / add cell 55 to 57: cell adder

58: quadrature phase delay unit

Hereinafter, with reference to the accompanying drawings an embodiment according to the technical idea of the residual sideband filter device for the present invention residual sideband demodulator as described above in detail.

First, the VSB filter is composed of a delay register, a shift register, a multiplier, an adder, etc. In the present invention, by reducing the number of multipliers in half, the volume can be greatly reduced in hardware implementation by the multiplex / multiply / add cells.

4 is a block diagram of a VSB filter according to the present invention.

As shown therein, a plurality of delay units 11 to 25 for receiving and delaying data and outputting in-phase signals; A plurality of adders 26 to 33 which receive the input data and data of the plurality of delay units 11 to 25 and add them respectively; First to fourth multiplexed / multiplied / added cells (51 to 54) for receiving the outputs of the two adders among the plurality of adders (26 to 33), respectively, and multiplying VSB filter coefficients to output the added values; A first cell adder (55) for adding output values of the first and second multiplexed / multiplied / added cells (51, 52); A second cell adder (56) for adding output values of the third and fourth multiplexed / multiplied / added cells (53) (54); A third cell adder (57) for adding output values of the first and second cell adders (55); A quadrature phase delay unit 58 outputs a quadrature phase signal by delaying the output of the third cell adding unit 57.

FIG. 5 is a detailed block diagram of the multiplex / multiply / add cells 51 to 54 in FIG.

As shown therein, a delay buffer 61 for delaying and storing the input system clock; A first multiplexer 62 for receiving and multiplexing the outputs of two adders of the plurality of adders 26 to 33; A second multiplexer 63 configured to receive and multiplex VSB filter coefficients; First and second delay units (64) (65) for delaying outputs of the first and second multiplexers (62, 63) for a predetermined period, respectively; A multiplier (66) for multiplying the outputs of the first and second delay units (64) (65); A third delay unit 67 for delaying the output of the multiplication unit 66; A fourth delay unit 68 for delaying the output of the third delay unit 67 for a predetermined time; An adder (69) for adding the outputs of the third and fourth delay units (67, 68); And a fifth delay unit 70 for delaying and outputting the output of the adder 69 for a predetermined time.

Referring to the operation of the present invention configured as described above is as follows.

First, FIG. 6 is a timing diagram of FIG. Here, the operations of the plurality of delay units 11 to 25 and the plurality of adders 26 to 33 are the same as in the conventional apparatus.

The first to fourth multiplexed / multiplied / added cells 51 to 54 include (26) and (27), (28) and (29), (30) and (31), (32) and (33). The outputs of the adders are input respectively. Since the structures and operations of the first to fourth multiplexed / multiplied / added cells 51 to 54 are the same, only the case of the first multiplexed / multiplied / added cells 51 will be described.

The delay buffer 61 delays and stores the input system clock. The system clock sys_clk is an input data rate clock, and 2sys_clk is a clock twice the input data rate. The slt output from the delay buffer 61 is a selection signal of the multiplexer obtained by delaying sys_clk.

Thus, the first multiplexer receives and multiplexes the data output from the adders 26 and 27, and the second multiplexer 63 multiplexes the VSB filter coefficients. The first and second delay units DFFA0 (DFFB0) 64 and 65 respectively delay the outputs of the first and second multiplexers 62 and 63 during the period of two system clocks. In 66, the outputs of the first and second delay units 64 and 65 are multiplied. That is, the multiplexers 62 and 63 alternately select ina and inb, ha and hb to perform two multiplications within a sys_clk period.

The third delay unit (DFF1) 67 delays the output of the multiplier 66 for a period of two system clocks, and the fourth delay unit (DFF2) 68 controls the third delay unit (DFF1) 67. Delays the output of A for two system clock cycles. The adder 69 adds data delayed for the period of two system clocks, respectively, and the fifth delay unit DFF3 70 delays the output of the adder 69 for one system clock and outputs the delayed data.

The output data has the same result as the operation using two multipliers.

Then, the first and second cell adders 55 and 56 add the output values of the first to fourth multiplexed / multiplied / added cells 51 to 54, respectively, and the third and second cell adders 57 and 57 respectively. The output value of the cell adder 55 is added, and the quadrature phase delay unit 58 delays the output of the third cell adder 57 to output the quadrature phase signal.

As such, the present invention significantly reduces hardware volume by reducing the number of multipliers to (m + 1) / 8 in a VSB filter having m taps used in a VSB demodulator.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the residual sideband filter device for the residual sideband demodulator according to the present invention reduces the number of multipliers in the VSB filter having m taps used in the VSB demodulator to (m + 1) / 8 to reduce the hardware volume. The effect can be greatly reduced.

Claims (2)

A residual sideband filter device for a residual sideband demodulator, A plurality of delay units for receiving data and delaying the data to output an in-phase signal; A plurality of adders which receive the input data and data of the plurality of delay units and add them respectively; First to fourth multiplexed / multiplied / added cells which respectively receive outputs of two adders from the plurality of adders and multiply a VSB (Vestigial SideBand) residual coefficient to output an added value; A first cell adder for adding output values of the first and second multiplexed / multiplied / added cells; A second cell adder for adding output values of the third and fourth multiplexed / multiplied / added cells; A third cell adder for adding output values of the first and second cell adders; And a quadrature phase delay unit configured to delay an output of the third cell adder and output a quadrature phase signal. The method of claim 1, wherein the first to fourth multiplexed / multiplied / added cells, A delay buffer for delaying and storing an input system clock; A first multiplexing unit configured to receive and multiplex outputs of two adding units among the plurality of adding units; A second multiplexer configured to receive and multiplex VSB filter coefficients; First and second delay units for delaying outputs of the first and second multiplexers for a predetermined period, respectively; A multiplier for multiplying outputs of the first and second delay parts; A third delay unit for delaying the output of the multiplier unit; A fourth delay unit delaying an output of the third delay unit for a predetermined time; An adder for adding outputs of the third and fourth delay units; And a fifth delay unit configured to delay and output an output of the adder for a predetermined time.