KR20000050380A - Tray for semiconductor chip package - Google Patents
Tray for semiconductor chip package Download PDFInfo
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- KR20000050380A KR20000050380A KR1019990000222A KR19990000222A KR20000050380A KR 20000050380 A KR20000050380 A KR 20000050380A KR 1019990000222 A KR1019990000222 A KR 1019990000222A KR 19990000222 A KR19990000222 A KR 19990000222A KR 20000050380 A KR20000050380 A KR 20000050380A
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- tray
- semiconductor chip
- chip package
- frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/67333—Trays for chips
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting substrates others than wafers, e.g. chips
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Packaging Frangible Articles (AREA)
Abstract
Description
본 발명은 반도체 칩 패키지용 트레이에 관한 것으로, 더욱 상세하게는 반도체 칩 패키지의 변형에 대응하여 선택된 영역만을 사출금형하여 제작할 수 있도록 한 반도체 칩 패키지용 트레이에 관한 것이다.The present invention relates to a tray for a semiconductor chip package, and more particularly, to a tray for a semiconductor chip package that can be manufactured by injection molding only a selected region corresponding to a deformation of the semiconductor chip package.
일반적으로 조립공정에 투입되는 반도체 칩 패키지들은 정전기방지용 재질로 이루어진 튜브 또는 트레이에 일정 수량이 담겨져 각 공정 사이로 운반된다.In general, semiconductor chip packages put into an assembly process are contained in a predetermined quantity in a tube or a tray made of an antistatic material and transported between processes.
이와 같이 반도체 칩 패키지들을 튜브 또는 트레이에 담아 운반하는 이유는 외부로 노출된 반도체 칩 패키지들이 정전기에 의해 손상되는 것을 방지함과 아울러 반도체 칩 패키지들의 보관 또는 이송의 편리성을 추구하기 위함이다.The reason for transporting the semiconductor chip packages in a tube or a tray is to prevent the externally exposed semiconductor chip packages from being damaged by static electricity and to pursue convenience of storing or transporting the semiconductor chip packages.
한편, 상기에서 언급한 트레이는 반도체 칩 패키지의 크기 및 구조 등을 동시에 고려하여 기 제작된 사출성형용 금형을 통해 정전기 방지용 재질의 합성수지(resin)가 사출성형되어 제조된다.On the other hand, the above-mentioned tray is manufactured by injection molding a synthetic resin (resin) of the antistatic material through the injection molding die made in consideration of the size and structure of the semiconductor chip package at the same time.
이때, 제조 완료된 트레이는 통상 일체형의 구조물로 이루어진다.At this time, the completed tray is usually made of an integral structure.
그러나, 이렇게 일체형으로 트레이를 제작함으로써 여러 가지 문제점이 야기되었다.However, various problems have been caused by the integrated production of the tray.
일례로, 트레이가 일체형으로 제작됨으로써, 반도체 칩 패키지의 크기 및 구조의 변경에 대응하여 다른 트레이를 제작할 경우, 트레이 전체에 대응되는 금형을 제작하기 때문에 사출성형용 금형의 제작 기간이 길어지는 문제점이 있다.For example, since the tray is manufactured integrally, when a different tray is manufactured in response to a change in the size and structure of the semiconductor chip package, a mold corresponding to the entire tray is manufactured, thus increasing the manufacturing period of the injection molding mold. have.
다른 예로, 트레이 전체에 대응하여 금형이 제작되기 때문에 금형 제작에 많은 비용이 소요되는 문제점이 있다.As another example, since the mold is manufactured corresponding to the entire tray, there is a problem in that a large cost is required to manufacture the mold.
또 다른 예로 외부충격으로부터 취약한 베어 칩(bare chip) 또는 칩 스케일 패키지에 대응하여 트레이를 변형 적용하는데 어려운 문제점이 있다.As another example, it is difficult to deform the tray in response to a bare chip or chip scale package that is vulnerable to external shock.
따라서, 본 발명의 목적은 트레이의 제작 기간을 단축하는데 있다.Therefore, an object of the present invention is to shorten the production period of the tray.
본 발명의 다른 목적은 금형 제작에 소요되는 기간을 단축하는데 있다.Another object of the present invention is to shorten the time required to manufacture a mold.
본 발명의 또 다른 목적은 외부충격에 취약한 베어 칩 및 칩 스케일 패키지 등에 대응하여 트레이를 적절히 변형 적용하는데 있다.Still another object of the present invention is to appropriately modify and apply a tray in response to a bare chip and a chip scale package vulnerable to external shock.
본 발명의 또 다른 목적은 다음의 상세한 설명 및 첨부된 도면으로부터 명확해질 것이다.Further objects of the present invention will become apparent from the following detailed description and the accompanying drawings.
도 1은 본 발명의 기술에 따른 실시예에 의한 반도체 칩 패키지용 트레이를 나타낸 분해 사시도.1 is an exploded perspective view showing a tray for a semiconductor chip package according to an embodiment of the present invention.
도 2는 본 발명의 기술에 따른 다른 실시예에 의한 반도체 칩 패키지용 트레이를 나타낸 분해 사시도.Figure 2 is an exploded perspective view showing a tray for a semiconductor chip package according to another embodiment according to the technology of the present invention.
도 3은 도 2의 트레이를 결합한 상태에서 포켓에 반도체 칩 패키지를 수납한 다음 도 2의 Ⅲ-Ⅲ을 나타낸 결합 단면도3 is a cross-sectional view illustrating III-III of FIG. 2 after storing a semiconductor chip package in a pocket in a state in which the tray of FIG. 2 is coupled;
이와 같은 목적을 달성하기 위하여 본 발명은 트레이를 포켓들이 형성되는 포켓프레임과 포켓프레임을 수납하는 지지프레임으로 구분하여 따로 제작하여 상호 착탈결합할 수 있도록 한다.In order to achieve the above object, the present invention allows the tray to be separated into a pocket frame in which pockets are formed and a support frame for accommodating the pocket frame, so that the trays can be detached from each other.
이때, 포켓프레임과 지지프레임간의 착탈 결합을 용이하게 할 수 있도록 포켓프레임의 측면에 적어도 하나 이상의 결합돌기가 형성되고, 상기 결합돌기와 대응되는 지지프레임의 내측면에 결합돌기를 수납하는 돌기수납홈이 형성될 수 있다.In this case, at least one coupling protrusion is formed on the side of the pocket frame to facilitate detachable coupling between the pocket frame and the support frame, and a protrusion storing groove accommodating the coupling protrusion on the inner side of the support frame corresponding to the coupling protrusion is provided. Can be formed.
또한, 포켓프레임의 이면과 지지프레임의 저면 사이에 충격흡수부재가 개재될 수 있다.In addition, an impact absorbing member may be interposed between the rear surface of the pocket frame and the bottom surface of the support frame.
이하 첨부된 도면을 참조하여 본 발명의 기술에 따른 실시예에 의한 반도체 칩 패키지용 트레이를 보다 상세하게 살펴보면 다음과 같다.Hereinafter, a semiconductor chip package tray according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
반도체 칩 패키지용 트레이(10)는 정전기 방지용 재질로 이루어진 직육면체로 이루어진다The semiconductor chip package tray 10 is made of a rectangular parallelepiped made of an antistatic material.
본 발명에 따르면, 트레이(10)는 크게 포켓프레임(12)과 지지프레임(14)으로 이루어진다.According to the present invention, the tray 10 is largely composed of a pocket frame 12 and a support frame 14.
포켓프레임(12)은 직사각형상으로 반도체 칩 패키지(도시되지 않음)를 수납하는 포켓들(16)이 행렬 구조로 두께 방향으로 관통 형성되어 이루어진다.The pocket frame 12 is formed by penetrating through the thickness direction in the form of a matrix of pockets 16 that accommodate a semiconductor chip package (not shown) in a rectangular shape.
포켓프레임(12)의 네 측면에는 각각 포켓프레임(12)의 외부로 향할수록 폭이 넓어지는 테이퍼 형상의 결합돌기(18)가 상호 이격되어 한쌍으로 형성된다.On each of four sides of the pocket frame 12, tapered coupling protrusions 18 having a wider width toward the outside of the pocket frame 12 are formed in a pair spaced apart from each other.
지지프레임(14)은 포켓프레임(12)의 표면을 제외한 그 이외의 부분, 예컨대, 측면과 이면을 감싸는 구조물로, 포켓프레임(12)의 결합돌기(18)와 대응되는 지지프레임(14)의 내측면에 결합돌기(18)와 대응 결합하는 역 테이퍼 형상의 돌기수납홈(20)이 형성되어 이루어진다.The support frame 14 is a structure that surrounds portions other than the surface of the pocket frame 12, for example, the side and the back, and includes a support frame 14 corresponding to the engaging protrusion 18 of the pocket frame 12. On the inner side is formed a projection receiving groove 20 of the reverse tapered shape corresponding to the coupling projection 18 is formed.
이러한 포켓프레임(12)과 지지프레임(14)은 포켓프레임(12)의 결합돌기(18)가 지지프레임(14)의 돌기수납홈(20)에 수납되어 착탈 결합된다.The pocket frame 12 and the support frame 14 are detachably coupled to the coupling protrusion 18 of the pocket frame 12 by being received in the protrusion receiving groove 20 of the support frame 14.
종래에는 트레이 자체가 하나의 사출금형에서 일체로 제작됨으로써, 반도체 칩 패키지의 모델이 변형될 경우, 트레이 전체에 대응하여 사출금형을 다시 제작함으로써 사출금형의 제작 기간이 길어졌지만, 본 발명에서는 반도체 칩 패키지의 변형에 따라 변형되는 포켓들(16)이 형성되는 영역, 예컨대, 포켓프레임(12)과 그 이외의 영역, 예컨대, 반도체 칩 패키지의 변형에 따라 변경되지 않는 지지프레임(14)을 따로 제작함으로써, 반도체 칩 패키지의 모델이 변형될 경우, 변형된 반도체 칩 패키지에 대한 트레이 전체에 대한 사출금형을 제작하지 않고, 포켓프레임(12)에 대한 사출금형만을 제작함으로써, 지지프레임(14)에 대한 사출금형의 제작 기간 만큼 사출금형의 제작 기간을 줄임으로써, 그만큼 트레이의 제작 기간을 단축할 수 있다.Conventionally, since the tray itself is integrally manufactured in one injection mold, when the model of the semiconductor chip package is deformed, the production period of the injection mold is increased by remanufacturing the injection mold corresponding to the entire tray. The support frame 14 which is not changed by the deformation of the semiconductor chip package is separately manufactured in an area in which the pockets 16 deformed according to the deformation of the package are formed, for example, the pocket frame 12 and other areas. As a result, when the model of the semiconductor chip package is deformed, instead of manufacturing the injection mold for the entire tray for the deformed semiconductor chip package, only the injection mold for the pocket frame 12 is produced, thereby supporting the support frame 14. By reducing the production period of the injection mold by the production period of the injection mold, the production period of the tray can be shortened by that amount.
이는 트레이(10)가 이미 규격화되어 있기 때문에 지지프레임(14)과 포켓프레임(12)의 분할 제작이 가능하게 된다. 즉, 트레이(10)의 규격화로 인해 지지프레임(14)은 항상 일정한 형태의 크기를 유지할 수 있으며, 포켓들(16)이 형성되는 포켓프레임(12)만을 변형된 반도체 칩 패키지에 대응하여 사출금형을 제작함으로써, 지지프레임(14)에 대한 사출금형을 반복적으로 제작하지 않아도 되기 때문에 그만큼 트레이의 제작기간이 단축된다.Since the tray 10 is already standardized, it is possible to make a split production of the support frame 14 and the pocket frame 12. That is, due to the standardization of the tray 10, the support frame 14 can always maintain a certain size, and only the pocket frame 12 in which the pockets 16 are formed corresponds to the modified semiconductor chip package. By manufacturing the mold, since the injection mold for the support frame 14 does not have to be produced repeatedly, the production period of the tray is shortened by that amount.
물론, 지지프레임(14)에 대한 사출금형을 반복적으로 제작하지 않기 때문에 사출금형에 대해 제작 기간이 단축되며, 지지프레임(14)에 대한 사출금형이 제작되지 않는 만큼 사출금형을 제작하는 소요되는 경비가 줄어든다.Of course, since the injection mold for the support frame 14 is not repeatedly produced, the production period is shortened for the injection mold, and the cost required to manufacture the injection mold as much as the injection mold for the support frame 14 is not manufactured. Decreases.
한편, 베어 칩 또는 칩 스케일 패키지와 같은 외부 충격에 취약한 반도체 칩 패키지에 대해 보안책으로, 상기 실시예에서 언급한 트레이를 변형하여 적용할 수 있다. 이를 하기에서 설명하는 다른 실시예에서 상세히 설명하기로 한다.On the other hand, as a security measure for a semiconductor chip package that is vulnerable to external shocks, such as a bare chip or a chip scale package, the tray mentioned in the above embodiment may be modified and applied. This will be described in detail in another embodiment described below.
상기 실시예에서 언급한 부분과 동일한 부분에 대한 상세한 설명은 생략하고, 동일한 부분에 대한 부호는 동일하게 부여한다.Detailed descriptions of the same parts as those mentioned in the above embodiment will be omitted, and the same reference numerals will be given to the same parts.
도 3에 도시된 바와 같이, 충격을 흡수할 수 있는 충격흡수부재, 예를 들어 충격흡수용 시트(22)가 포켓프레임(12)을 수납하는 지지프레임(14)의 수납공간내에 수납되어 포켓프레임(12)과 지지프레임(14) 사이에 개재된다.As shown in FIG. 3, a shock absorbing member capable of absorbing a shock, for example, a shock absorbing sheet 22 is accommodated in a storage space of a support frame 14 accommodating the pocket frame 12. It is interposed between 12 and the support frame 14.
이렇게 포켓프레임(12)과 지지프레임(14) 사이에 충격흡수용 시트가 설치되어 외부로부터의 충격 및 이 충격으로 인한 볼 그리드 어레이 패키지(24)와의 접촉면에 대한 충격 등을 흡수함으로써, 충격에 의한 볼 그리드 어레이 패키지(24)의 손상을 최소화할 수 있다.Thus, a shock absorbing sheet is installed between the pocket frame 12 and the support frame 14 to absorb the impact from the outside and the impact on the contact surface with the ball grid array package 24 due to the impact. Damage to the ball grid array package 24 can be minimized.
종래에는 볼 그리드 어레이 패키지들이 포켓들에 각각 수납된 상태에서 외부로부터 충격이 트레이에 가해질 경우, 딱딱한 재질로 이루어질 트레이로 인해, 외부 충격이 트레이 내부로 쉽게 전달되어 볼 그리드 어레이 패키지들에 가해짐으로써, 제품이 손상될 위험성이 높았지만, 본 발명에서는 트레이(10) 내부로 전달되는 충격을 충격흡수용 시트(22)에서 흡수함으로써, 외부 충격으로 인해 볼 그리드 어레이 패키지(24)가 손상되는 것을 방지할 수 있으며, 또한, 볼 그리드 어레이 패키지(24)의 솔더볼이 접촉하는 접촉면이 충격흡수용 시트(22)이기 때문에 접촉면에 대한 충격 흡수가 가능하여 제품이 손상될 위험성이 저하된다.Conventionally, when the impact is applied to the tray from the outside while the ball grid array packages are respectively accommodated in the pockets, due to the tray made of a hard material, the external impact is easily transmitted into the tray and applied to the ball grid array packages. Although the risk of product damage was high, in the present invention, the shock transmitted to the tray 10 is absorbed by the shock absorbing sheet 22 to prevent the ball grid array package 24 from being damaged due to external shock. In addition, since the contact surface contacting the solder ball of the ball grid array package 24 is a shock absorbing sheet 22, shock absorption on the contact surface is possible, thereby reducing the risk of product damage.
이상에서 살펴본 바와 같이, 본 발명은 반도체 칩 패키지들을 수납하는 트레이를 포켓들이 형성되는 포켓프레임과 포켓프레임을 수납하는 지지프레임으로 구분하여 상호 착탈결합할 수 있도록 따로 제작함으로써, 반도체 칩 패키지의 모델이 변경될 경우, 포켓프레임을 변경된 반도체 칩 패키지에 맞게 제작한 다음 기 제작된 지지프레임에 결합시킴으로써, 지지프레임의 제작에 소요되는 기간만큼 트레이의 제작기간을 줄일 수 있는 효과가 있다.As described above, the present invention provides a tray for accommodating the semiconductor chip packages into a pocket frame in which pockets are formed and a support frame for accommodating the pocket frame, so that the trays for storing the semiconductor chip packages are separately manufactured to be detachably coupled to each other. If changed, by manufacturing the pocket frame according to the modified semiconductor chip package and then coupled to the pre-fabricated support frame, there is an effect that can reduce the production period of the tray by the time required to manufacture the support frame.
또한, 반도체 칩 패키지의 모델이 변경될 경우, 지지프레임의 제작에 소요되던 사출금형에 대한 경비 소요가 줄어들기 때문에 그만큼 금형 제작에 소요되는 비용을 절감할 수 있는 효과가 있다.In addition, when the model of the semiconductor chip package is changed, the cost required for the injection mold used to manufacture the support frame is reduced, thereby reducing the cost of manufacturing the mold.
또한, 포켓프레임과 지지프레임 사이에 충격방지부재를 개재하여 외부로부터 가해지는 충격을 충격방지부재에서 흡수함으로써, 외부 충격으로 인해 트레이의 포켓에 수납되는 반도체 칩 패키지가 손상되는 것을 방지할 수 있는 효과가 있다.In addition, by absorbing the impact applied from the outside through the impact preventing member between the pocket frame and the support frame in the impact preventing member, it is possible to prevent damage to the semiconductor chip package accommodated in the pocket of the tray due to external impact. There is.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990000222A KR20000050380A (en) | 1999-01-08 | 1999-01-08 | Tray for semiconductor chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990000222A KR20000050380A (en) | 1999-01-08 | 1999-01-08 | Tray for semiconductor chip package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000050380A true KR20000050380A (en) | 2000-08-05 |
Family
ID=19570804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990000222A KR20000050380A (en) | 1999-01-08 | 1999-01-08 | Tray for semiconductor chip package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000050380A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100807317B1 (en) * | 2007-02-07 | 2008-02-28 | 주식회사 오킨스전자 | Test tray for semiconductor chip package and method for moving semiconductor chip package |
-
1999
- 1999-01-08 KR KR1019990000222A patent/KR20000050380A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100807317B1 (en) * | 2007-02-07 | 2008-02-28 | 주식회사 오킨스전자 | Test tray for semiconductor chip package and method for moving semiconductor chip package |
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