KR20000045876A - Method for creating cobalt salicide membrane of semiconductor device - Google Patents
Method for creating cobalt salicide membrane of semiconductor device Download PDFInfo
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- KR20000045876A KR20000045876A KR1019980062479A KR19980062479A KR20000045876A KR 20000045876 A KR20000045876 A KR 20000045876A KR 1019980062479 A KR1019980062479 A KR 1019980062479A KR 19980062479 A KR19980062479 A KR 19980062479A KR 20000045876 A KR20000045876 A KR 20000045876A
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- Prior art keywords
- gate electrode
- film
- cobalt
- semiconductor device
- forming
- Prior art date
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- 239000010941 cobalt Substances 0.000 title claims abstract description 38
- 229910017052 cobalt Inorganic materials 0.000 title claims abstract description 38
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000012528 membrane Substances 0.000 title abstract 6
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 239000000203 mixture Substances 0.000 claims abstract description 11
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 239000011810 insulating material Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 5
- 229910017855 NH 4 F Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 18
- 229910021332 silicide Inorganic materials 0.000 abstract description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052710 silicon Inorganic materials 0.000 abstract description 17
- 239000010703 silicon Substances 0.000 abstract description 17
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000001312 dry etching Methods 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 239000011800 void material Substances 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 31
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 11
- 229910052719 titanium Inorganic materials 0.000 description 11
- 238000002955 isolation Methods 0.000 description 6
- 229910019001 CoSi Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 241000252506 Characiformes Species 0.000 description 1
- 229910019044 CoSix Inorganic materials 0.000 description 1
- 229910004339 Ti-Si Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910010978 Ti—Si Inorganic materials 0.000 description 1
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
Abstract
Description
본 발명은 반도체장치의 형성방법에 관한 것으로서, 특히 비정항이 낮은 코발트 살리사이드막을 갖는 반도체장치의 게이트 전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a gate electrode of a semiconductor device having a low cobalt salicide film.
일반적으로, 소자의 집적도가 증가함에 따라 불순물 주입영역인 정션(Junction)의 깊이가 줄어들고 게이트 전극의 선폭이 감소하게 되고 그로 인하여 소자에서 요구되는 면저항을 구현하는데 문제점이 있었다. 이와 같은 면저항을 개선하기 위하여 정션과 게이트 전극 부위에 텅스텐실리사이드(WSi)보다 비저항이 낮은 코발트실리사이드(CoSi2)를 동시에 형성하는 살리사이드(Salicide:Self-Aligned Silicide) 공정을 실시하여 면저항을 감소하고 있다.In general, as the degree of integration of the device increases, the depth of the junction, which is an impurity injection region, decreases and the line width of the gate electrode decreases, thereby causing a problem in implementing sheet resistance required by the device. In order to improve the sheet resistance, a salicide (Self-Aligned Silicide) process, which simultaneously forms cobalt silicide (CoSi 2 ) having a lower resistivity than tungsten silicide (WSi) at the junction and the gate electrode, reduces the sheet resistance. have.
이러한 코발트 살리사이드 공정시 게이트 전극 부분에서는 도프트 폴리실리콘과 코발트(Co)가 반응하여 코발트 실리사이드막이 형성되는데 반하여 게이트 전극 에지부분의 기판내의 정션에서는 단결정인 실리콘기판과 반응하는 코발트 실리사이드막이 형성됨에 따라 정션 부분의 실리사이드막이 균일한 계면을 얻기가 어려웠다. 이를 극복하고자 코발트 실리사이막의 에피성장을 도울수 있도록 티타늄(Ti)과 코발트(Co) 또는 코발트와 티타늄의 이중 금속막을 순서적으로 증착하는 제조 방법이 제안되고 있다.In the cobalt salicide process, dopant polysilicon and cobalt (Co) react in the gate electrode portion to form a cobalt silicide layer, whereas in the junction of the gate electrode edge portion, a cobalt silicide layer that reacts with a single crystal silicon substrate is formed. It was difficult to obtain a uniform interface of the silicide film of the junction portion. In order to overcome this problem, a manufacturing method of sequentially depositing a double metal film of titanium (Ti) and cobalt (Co) or cobalt and titanium has been proposed to help epitaxial growth of the cobalt silicide film.
도 1은 종래 기술에 의한 반도체장치의 코발트 살리사이드 공정을 설명하기 위한 수직 단면도이다.1 is a vertical cross-sectional view for explaining a cobalt salicide process of a semiconductor device according to the prior art.
이를 참조하면, 반도체기판으로서 실리콘 기판(10)에 소자간 분리를 위한 소자분리막(12)을 형성하고 소자분리막에 의해 구분되는 기판의 활성 영역 위에 게이트 산화막(14)을 형성하고, 그 위에 게이트 도전층으로서 도프트 폴리실리콘(16)을 증착하고 게이트 마스크를 이용한 사진 및 식각 공정을 실시하여 상기 폴리실리콘막(16)을 패터닝하여 게이트 전극을 형성한다. 그 다음, 절연물질을 증착하고 건식식각 공정으로 상기 절연물질을 식각하여 게이트 전극의 측벽에 사이드 스페이서막(18)을 형성하고, 불순물 이온 주입 공정을 실시하여 게이트 전극 에지 근방의 기판내에 불순물이 주입된 소스/드레인 정션(20)을 형성한다.Referring to this, a device isolation film 12 is formed on the silicon substrate 10 as a semiconductor substrate, and a gate oxide film 14 is formed on the active region of the substrate separated by the device isolation film, and the gate conduction is formed thereon. The polysilicon layer 16 is patterned to form a gate electrode by depositing the doped polysilicon 16 as a layer and performing a photolithography and an etching process using a gate mask. Next, an insulating material is deposited and the insulating material is etched by a dry etching process to form a side spacer film 18 on the sidewall of the gate electrode, and an impurity ion implantation process is performed to implant impurities into the substrate near the edge of the gate electrode. The formed source / drain junction 20.
그리고, 실리사이드 공정을 진행하여 상기 결과물 위에 티타늄(Ti)과 코발트(Co) 또는 코발트와 티타늄의 이중 금속막(22,24)을 순차적으로 증착한 후에 열공정을 실시하여 상기 소스/드레인 정션(20)과 게이트 전극 위에 코발트 실리사이드막을 형성한다.In addition, a silicide process is performed to sequentially deposit titanium (Ti) and cobalt (Co) or cobalt and titanium double metal layers 22 and 24 on the resultant, and then thermally perform the source / drain junction 20. And a cobalt silicide film on the gate electrode.
그러나, 상기 실리사이드 공정시 티타늄(Ti)/코발트(Co)/실리콘(Si)이 순차 적층되어 있을 경우에는 실리콘의 자연 산화막 제거능력이 떨어져 실리콘 표면의 깨끗한 세정 공정이 반드시 요구되는 반면에, 코발트(Co)/티타늄(Ti)/실리콘(Si)이 순차 적층되어 있을 경우에는 티타늄이 실리콘에 직접 접촉되어 자연산화막의 제거 및 에피성장을 할 수 있는 점이 있지만 사이드 스페이서막(18) 하부의 기판 내에서 주확산원소인 실리콘이 이동하게 되어 결국 이 부분에서 공동(void)이 발생하는 현상(F)이 일어나게 된다.However, when titanium (Ti) / cobalt (Co) / silicon (Si) are sequentially stacked in the silicide process, the ability to remove the natural oxide film of silicon is poor and a clean cleaning process of the silicon surface is required, whereas cobalt ( When Co) / titanium (Ti) / silicon (Si) are sequentially stacked, there is a point that titanium can be directly contacted with silicon to remove the natural oxide film and to grow epitaxially, but within the substrate under the side spacer film 18 Silicon, which is the main diffusion element, moves and eventually causes a phenomenon (F) in which a void occurs.
또한, 티타늄(Ti)/코발트(Co)/실리콘(Si) 내지 코발트(Co)/티타늄(Ti)/실리콘(Si) 구조의 경우에는 일반적으로 열처리 및 선택적 식각 공정의 2단계 공정을 진행하기 때문에 제조 공정의 단계 및 제조 공정 시간이 늘어나게 된다.In addition, in the case of titanium (Ti) / cobalt (Co) / silicon (Si) to cobalt (Co) / titanium (Ti) / silicon (Si) structures, a two-step process of heat treatment and selective etching is generally performed. The steps of the manufacturing process and the manufacturing process time increase.
본 발명의 목적은 상기 종래기술의 문제점을 해결하기 위하여 게이트 전극 및 소스/드레인의 정션위에 코발트 살리사이드막을 형성하는데 있어 비정질의 Co-Ti-Si 혼합물을 이용함으로써 이 증착 막내에 보유된 적은 양의 티타늄에 의해서 계면이 균질한 실리사이드막의 확보하면서 사이드 스페이서막 하부 근방의 실리콘 이동으로 인한 공극화 발생을 억제하여 제조 공정의 신뢰성을 향상시킬 수 있는 코발트 살리사이드막을 갖는 반도체장치의 게이트 전극 형성방법을 제공하는데 있다.An object of the present invention is to reduce the amount of small amount retained in this deposited film by using an amorphous Co-Ti-Si mixture in forming a cobalt salicide film on the junction of the gate electrode and the source / drain to solve the problems of the prior art. Provided is a method of forming a gate electrode of a semiconductor device having a cobalt salicide film which can improve the reliability of the manufacturing process by securing the silicide film having a homogeneous interface by titanium and suppressing the occurrence of voids due to the movement of silicon near the bottom of the side spacer film. It is.
도 1은 종래 기술에 의한 반도체장치의 코발트 살리사이드 공정을 설명하기 위한 수직 단면도,1 is a vertical cross-sectional view for explaining a cobalt salicide process of a semiconductor device according to the prior art;
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 코발트 살리사이드막 형성 방법을 설명하기 위한 수직 단면도들,2A to 2C are vertical cross-sectional views illustrating a method of forming a cobalt salicide film of a semiconductor device according to the present invention;
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100 : 실리콘기판 102 : 소자분리막100: silicon substrate 102: device isolation film
104 : 게이트 산화막 106 : 도프트 폴리실리콘막104: gate oxide film 106: doped polysilicon film
108 : 사이드 스페이서막 110 : 소스/드레인 정션108: side spacer film 110: source / drain junction
112 : TixCoySiz혼합막 114, 116 : 코발트 살리사이드막112: Ti x Co y Si z mixed film 114, 116: cobalt salicide film
상기 목적을 달성하기 위하여 본 발명은 반도체기판 상부의 활성 영역위에 게이트 산화막을 형성하고 그 위에 게이트 전극을 형성하고 게이트 전극 에지 하부 근방의 활성 영역내에 도전형 불순물이 주입된 소스/드레인 정션으로 이루어진 반도체장치의 모스 트랜지스터를 형성함에 있어서, 게이트 산화막위에 도프트 폴리실리콘으로 이루어진 게이트 전극을 형성하는 단계와, 게이트 전극 측멱에 절연물질로 이루어진 사이드 스페이서막을 형성하는 단계와, 게이트 전극 에지 하부근방의 활성 영역내에 도전형 불순물을 주입하여 소스/드레인 정션을 형성하는 단계와, 결과물 위에 TixCoySiz의 혼합물을 증착하고 열처리 및 미반응 물질의 세정공정을 실시하여 게이트 전극 및 소스/드레인 정션 위에 코발트 살리사이드막을 동시에 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a semiconductor including a source / drain junction in which a gate oxide layer is formed on an active region on an upper surface of a semiconductor substrate, a gate electrode is formed thereon, and conductive impurities are implanted into an active region near the edge of the gate electrode. In forming a MOS transistor of the device, forming a gate electrode made of doped polysilicon over the gate oxide film, forming a side spacer film made of an insulating material on the side of the gate electrode, and an active region near the bottom of the gate electrode edge. Implanting conductive impurities into the source / drain junction, depositing a mixture of Ti x Co y Si z on the resultant, performing a heat treatment and cleaning of unreacted material, and performing cobalt on the gate electrode and the source / drain junction Simultaneously forming a salicide film Characterized in that made in box.
본 발명의 방법에 있어서, 상기 TixCoySiz의 혼합물 타겟은 x:y를 1:0.5∼3.0 비율로 하며 x+y:z를 1:0.3∼2.5 비율로 한다. 그리고, 세정 공정은 H2SO4+H2O2내지 NH4F+HF의 혼합용액 중의 어느 하나를 사용하며 이때 70∼150℃의 온도 조건과 30분이내에서 실시하는 것이 바람직하다.In the method of the present invention, the mixture target of Ti x Co y Si z has x: y in a ratio of 1: 0.5 to 3.0 and x + y: z in a ratio of 1: 0.3 to 2.5. In addition, the washing process uses any one of a mixed solution of H 2 SO 4 + H 2 O 2 to NH 4 F + HF, and at this time, it is preferably carried out within a temperature condition of 70 to 150 ° C and within 30 minutes.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대하여 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 코발트 살리사이드막 형성 방법을 설명하기 위한 수직 단면도들이다.2A to 2C are vertical cross-sectional views illustrating a method of forming a cobalt salicide film of a semiconductor device according to the present invention.
우선, 반도체기판으로서 실리콘기판(100) 상부에 소자간 분리를 위한 소자분리막(102)을 형성한 후에 소자분리막(102)에 의해 구분되는 기판의 활성 영역 위에 게이트 산화막(104)을 형성하고, 그 위에 순차적으로 게이트 도전층으로서 도프트 폴리실리콘막(106)을 형성한다. 이때, 도프트 폴리실리콘의 증착은 500∼650℃의 반응챔버내 온도 범위와 80Torr이하의 증착 압력하에서 이루어지며 SiH4와 PH3가스를 소오스 가스(source gas)로 이용한다. 그 다음, 게이트 마스크를 이용한 사진 및 식각 공정을 실시하여 상기 도프트 폴리실리콘막(106)을 패터닝하여 게이트 전극을 형성하고, 기판 전면에 절연물질을 증착하고 건식식각 공정으로 상기 절연물질을 식각하여 게이트 전극의 측벽에 사이드 스페이서막(108)을 형성한 후에, 불순물 이온 주입 공정을 실시하여 게이트 전극 에지 근방의 기판내에 불순물이 주입된 소스/드레인 정션(110)을 형성한다.First, after forming a device isolation film 102 for isolation between devices on the silicon substrate 100 as a semiconductor substrate, a gate oxide film 104 is formed over the active region of the substrate divided by the device isolation film 102. A doped polysilicon film 106 is formed sequentially as a gate conductive layer thereon. At this time, the deposition of the doped polysilicon is performed under a temperature range of 500 to 650 ° C. and a deposition pressure of 80 Torr or less, and SiH 4 and PH 3 gases are used as the source gas. Then, the doped polysilicon layer 106 is patterned by using a gate mask to form a gate electrode, an insulating material is deposited on the entire surface of the substrate, and the insulating material is etched by a dry etching process. After the side spacer film 108 is formed on the sidewall of the gate electrode, an impurity ion implantation process is performed to form a source / drain junction 110 in which impurities are implanted in the substrate near the gate electrode edge.
그리고나서, 기판 전면에 스퍼터링(sputtering) 공정을 이용하여 비정질의 TixCoySiz의 혼합물(112)을 증착하는데, 이때 혼합물 타겟의 x:y 비율은 1:0.5∼3.0로 정하며 x+y:z의 비율은 1:0.3∼2.5 비율로 한다.Then, a mixture 112 of amorphous Ti x Co y Si z is deposited on the entire surface of the substrate using a sputtering process, where the x: y ratio of the mixture target is set at 1: 0.5 to 3.0 and x + y. The ratio of: z is 1: 0.3 to 2.5.
이어서 도 2b에 도시된 바와 같이, 열처리 공정을 실시하여 비정질막을 결정화시키는데, 이때 공정은 500∼900℃의 온도 범위에서 급속 열처리 공정을 실시하거나 500∼850℃의 온도 범위에서 퍼니스 열처리 공정을 실시하도록 한다. 이에, 상기 게이트 전극의 도프트 폴리실리콘막(106)과 소스/드레인 정션(110) 위에 있는 TixCoySiz의 혼합물(112)의 코발트(Co)와 이에 접합 부분의 실리콘이 반응하여 코발트 실리사이드막(CoSix)(114,116)이 형성되며 반응하지 않는 코발트(Co)와 티타늄(Ti)은 잉여 실리콘과 반응하여 폴리의 CoTiSi상이 얻어진다.Subsequently, as shown in FIG. 2B, a heat treatment process is performed to crystallize the amorphous film, wherein the process may be performed by a rapid heat treatment process at a temperature range of 500 to 900 ° C. or a furnace heat treatment process at a temperature range of 500 to 850 ° C. do. Accordingly, cobalt (Co) of the mixture 112 of Ti x Co y Si z on the doped polysilicon layer 106 and the source / drain junction 110 of the gate electrode reacts with cobalt silicon. Silicide films (CoSix) 114 and 116 are formed and cobalt (Co) and titanium (Ti), which do not react, react with excess silicon to obtain a CoTiSi phase of poly.
좀 더 상세하게, 게이트 전극의 도프트 폴리실리콘막(106) 부분에서는 폴리의 코발트 실리사이드막(116)이 얻어지는 반면에, CoSi막이 실리콘과 격자불일치가 1.2%이내이기 때문에 소스/드레인 정션(110) 부분에서는 에피 성장으로 형성된 단결정의 코발트 살리사이드막(114)이 형성된다. 또한 사이드 스페이서막(108) 위에서는 Ti이 N과 반응하여 얇은 TiN이 형성된다.More specifically, the cobalt silicide film 116 of poly is obtained in the doped polysilicon film 106 portion of the gate electrode, while the source / drain junction 110 is formed because the CoSi film has a lattice mismatch of less than 1.2% with silicon. In the portion, a single crystal cobalt salicide film 114 formed by epitaxial growth is formed. Further, on the side spacer film 108, Ti reacts with N to form thin TiN.
그 다음 도 2c에 도시된 바와 같이 미반응 물질의 세정공정을 실시하여 상기 게이트 전극(106)과 소스/드레인 정션(110) 위에 형성된 코발트 살리사이드막(114,116)을 제외한 나머지 비반응 막을 제거하도록 한다. 이때, 세정 공정은 H2SO4+H2O2(piranha) 내지 NH4F+HF의 혼합용액(BOE) 중의 어느 하나를 사용하며 이때 70∼150℃의 온도 조건과 30분이내에서 실시하도록 한다.Next, as shown in FIG. 2C, an unreacted material is cleaned to remove the remaining unreacted film except for the cobalt salicide films 114 and 116 formed on the gate electrode 106 and the source / drain junction 110. . At this time, the cleaning process using any one of the mixed solution (BOE) of H 2 SO 4 + H 2 O 2 (piranha) to NH 4 F + HF and at this time it is to be carried out within a temperature condition of 70 ~ 150 ℃ and 30 minutes. .
상기와 같은 본 발명에 따른 제조 공정에 의하면, TixCoySiz의 혼합물(112)을 이용하여 상대적으로 적은 Ti량과 실리콘의 충분한 공급으로 인해 사이드 스페이서막(108) 하부의 기판 내에서 실리콘 원자의 확산으로 인해 공극화(void) 현상이 억제된다.According to the manufacturing process according to the present invention as described above, by using a mixture 112 of Ti x Co y Si z, the silicon in the substrate below the side spacer film 108 due to the relatively small amount of Ti and sufficient supply of silicon. Due to the diffusion of atoms, voids are suppressed.
따라서, 상기한 바와 같이 본 발명에 따른 반도체장치의 코발트 살리사이드 제조 공정을 이용하게 되면, 비정질의 TixCoySiz혼합물의 증착공정 및 열처리 공정시 이 혼합막 내의 상대적으로 적은 Ti량으로 인해 사이드 스페이서막 하부에서 실리콘 원자의 이동량이 감소하게 되어 기판내의 공극화 현상이 억제된다.Therefore, when using the cobalt salicide manufacturing process of the semiconductor device according to the present invention as described above, due to the relatively small amount of Ti in the mixed film during the deposition process and heat treatment process of the amorphous Ti x Co y Si z mixture The amount of movement of silicon atoms under the side spacer film is reduced, so that the phenomenon of voiding in the substrate is suppressed.
또한 비정질 상태로 증착된 TixCoySiz막은 고온 열처리 공정을 실시하여 결정화를 이루어 특히 소스/드레인 정션부분에서 계면이 균질한 에피성장의 코발트 실리사이드막을 획득할 수 있다.In addition, the Ti x Co y Si z film deposited in an amorphous state may be crystallized by performing a high temperature heat treatment to obtain a cobalt silicide film having an epitaxially grown interface, especially at the source / drain junction.
동시에 본 발명은 TixCoySiz막내에 강한 자연 산화막 제거능력 특성을 갖는 Ti을 함유하고 있어, 소스/드레인 정션 부위의 자연 산화막을 제거할 수 있는 장점이 있다.At the same time, the present invention includes Ti having a strong natural oxide film removing ability in the Ti x Co y Si z film, which has the advantage of removing the natural oxide film at the source / drain junction.
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