KR20000045626A - Pre-processing apparatus for adjusting decoding time of video decoder - Google Patents

Abstract

PURPOSE: A pre-processing apparatus for adjusting decoding time of video decoder is provided to prevent error from occurring while performing a decoding process by controlling the VBV(Video Buffer Verifier). CONSTITUTION: A pre-processing apparatus for adjusting decoding time of video decoder includes a shift register(110), a start code detector(120), a state machine(130), a counter(140), a data latch/control signal generator(150), a frame rate latch(160), a VBV buffer size latch(170) and a VBV delay latch(180). The shift register(110) shifts input video stream sequentially. The state machine(130) inputs enable signal from the detector(120) and controls writing of input video stream. The counter(140) is controlled by the signal from the detector(120). The data latch/control signal generator(150) generates signals for latching frame rate, VBV buffer size and VBV buffer delay. The frame rate latch(160), the VBV buffer size latch(170) and the VBV delay latch(180) are operated by the control signal from the data latch/control signal generator.

Description

Preprocessor for video decoding time adjustment

The present invention relates to a pre-processor for adjusting the decoding time of a video decoder in a high-definition television (HDTV). In particular, the present invention relates to extracting a parameter after a sequence-header is input, and to extracting a video buffer. Verifier) relates to a preprocessor for controlling the decoding time of a video decoder to prevent an error in decoding by controlling to store an input video stream in a buffer.

In general, high definition television (HDTV) adopts Moving Picture Experts Group-2 (MPEG-2) as a video standard.

In general, encoding a video signal changes the amount of information generated due to the complexity of the video and the speed of the motion. In order to transmit at a constant transmission rate corresponding to the change amount, code generation amount control (bit rate control) must be performed. In MPEG-2, a buffer (VBV-buffer) is provided at the time of transmission, and the amount of data generated by changing the quantization coefficient according to the occupancy of the buffer is adjusted so as not to exceed or fall within a certain range (VBV buffer size). Similarly, since the amount of data of the encoded video signal is variable at the receiving side, the buffer of the size used at the time of transmission is used to correspond to the amount of change.

In hardware implementation of a video decoder that decodes a video stream that conforms to the MPEG-2 standard, a VBV delay control function is required through the VBV-buffer to adjust the decoding time. This delay control can be implemented by pre-extracting parameters such as VBV delay before writing the video stream to the VBV-buffer. Delay control function can be processed by software in case of existing TV class MPEG-2 video decoder, while hardware processing is inevitable because HDTV class decoder has high input data rate and required processing speed. .

In order to implement the VBV delay control function that adjusts the decoding time in an HDTV-class MPEG-2 video decoder, a pre-processing process for controlling necessary parameters and data input to the VBV-buffer is required.

1 is a block diagram of a video decoder applied to a general HDTV system.

As shown, the preprocessor 11 detects the VBV delay information from the input video stream to control the time at which the video stream can be read, and detects the frame rate information to secure the decoding time of the video stream. A VBV buffer control unit 12 for controlling the overall operation of the decoding system according to various control information (frame rate information, VBV buffer size information, etc.) obtained by the preprocessor 11, and a video stream recording obtained by the preprocessor 11; The VBV buffer 13 and the VBV buffer controller 12 record the video stream data input according to the control signal to the RAM and output the video stream stored according to the read control signal obtained from the rear decoder 14. And a video decoding unit 14 for decoding the video stream obtained from the VBV buffer unit 13 under control. All.

In the above, the preprocessor 11 in the first to fourth D flip-flop (11a to 11d) and the first to fourth D flip-flop (11a to 11d) for sequentially latching and outputting the input video stream, respectively A comparison unit 51e for comparing the delayed value to determine the stream type, and a control signal for recording the VBV delay value, frame rate information, and VBV size information according to the type of the bitstream determined by the comparison unit 51e. And a control logic and counter 51f for generating a ready signal RDY and a recordable signal WE according to the bitstream type, and a write control signal output from the control logic and counter 51f. A VBV delay value latch section 11g for latching and outputting a buffer delay value from the data obtained by the first to fourth D flip-flops 11a to 11d, and a write control signal output from the control logic and counter 11f. According to the first to The first to fourth Ds according to the frame rate latch section 11h for latching and outputting the frame rates obtained from the 4D flip flops 11a to 11d and the write control signals output from the control logic and counter 11f. The VBV size latch section 11i latches and outputs the VBV buffer size obtained by the flip-flops 11a to 11d.

The video decoder configured as described above first latches the video stream data input from the first to fourth D flip-flops 11A to 11d in the preprocessor 11 in 8-bit units to output delayed video stream data. At this time, the comparing unit 11e compares the 8-bit video stream data latched and output from the first to fourth D flip-flops 11a to 11d, respectively, and determines the type of the stream. Initializes the control logic and counter 11f, and passes the stream type determination value. The video stream input above is shown in FIG. 3. As shown in Fig. 3, the video stream is in order of Sequence Header, Sequence Extension, Extension & User, Group of Picture Header, User data, Picture Header, Picture Coding Extension, Extension & User, Picture Data, Sequence End. The solid line that is fed back or skipped in the line indicates that the data may or may not be recorded in that portion.

On the other hand, the control logic and counter 11f are initialized by the reset signal and adjust the VBV buffer delay value, frame rate, and VBV buffer size according to the input stream type determination value, the address, and the data read signal RD. A write control signal (Write-Cnt) to write is generated, and a 3-bit RDY signal is generated to externally read the VBV buffer delay value, VBV buffer size, and frame rate. The recordable signal WE is generated according to the type of the stream, and the VBV buffer delay value, the VBV buffer size, and the frame rate are transferred to the read block.

In this case, the write enable signal WE is disabled in the case of data that does not need to be written to the VBV buffer (for example, garbage data generated when a channel is changed).

On the other hand, the VBV delay value latch section 11g is a 16-bit VBV delay from the data output from the first to fourth D flip-flops 11a to 11d in accordance with the write control signal output from the control logic and counter 11f. The value is latched and transferred to the VBV buffer unit 13 to determine the time point at which data is read from the VBV buffer during decoding.

In addition, the frame rate latch unit 11h latches the frame rate of 4 bits from the data output from the first to fourth D flip-flops 11a to 11d in accordance with the write control signal output from the control logic and counter 11f. The control unit transmits the control signal to the decoding unit 14 at a later stage. Similarly, the VBV buffer size latch section 11i also has 10-bit VBV buffer size data from the data output from the first to fourth D flip-flops 11a to 11d in accordance with the write control signal output from the control logic and counter 11f. The latch is transmitted to the CPU 60 and other video decoders as control signals.

Meanwhile, the VBV buffer unit 13 stores the delayed video stream data input to the RAM according to the VBV buffer delay value obtained by the preprocessor 11, and the decoding unit 14 stores the video stream data stored in the RAM. Decode and decode the original video data to output.

However, such a conventional preprocessor generates a control signal for controlling the VBV buffer according to the type of the input video stream and stores the input video stream appropriately in the VBV buffer. In this case, there is a problem that a decoding error occurs because the parameters for processing the input video stream cannot be accurately extracted.

Therefore, the present invention has been proposed to solve all the problems arising from the preprocessor for controlling the VBV buffer installed in the front of the conventional demodulator,

It is an object of the present invention to extract errors after a sequence-header is input and to control the storage of the input video stream in a Video Buffer Verifier (VBV) -buffer to prevent errors in decoding. The present invention provides a preprocessor for adjusting the decoding time of a video decoder.

The present invention (apparatus) for achieving the above object,

A preprocessor for controlling a VBV buffer for storing an encoded input video stream,

A shift register section for sequentially shifting the input video stream;

A start code detector for detecting a start code from data output from the shift register section;

A state machine for receiving a signal output from the start code detector as an enable signal and extracting a sequence header from data output from the shift register unit to generate a control signal for controlling recording of an input video stream;

A counter for counting according to the signal output from the start code detector and outputting a count value;

Control for latching and outputting a recordable signal and a count start signal output from the state machine and the counter, respectively, and latching the frame rate, the VBV buffer size, and the VBV buffer delay value according to the control signals output from the state machine and the counter. A data latch and control signal generator for generating a signal;

A frame rate latch unit for latching and outputting frame rate data obtained from the shift register according to a control signal output from the data latch and control signal generator;

A VBV buffer size latch unit for latching and outputting VBV buffer size data obtained from the shift register in accordance with a control signal output from the data latch and control signal generator;

And a VBV buffer delay value latch unit for latching and outputting a VBV buffer delay value obtained from the shift register according to a control signal output from the data latch and control signal generator.

In the above, the state machine transitions to an initialization state when the signal S1 obtained from the shift register unit is a clear signal, and transitions to a sequence header extraction state when the signal S1 is B3 in the initialization state, and the sequence header When the signal S1 is 00 in the extracted state, the signal transitions to the picture header extraction state, and when the input signal S1 is B7 in the picture header extraction state, the signal transitions to the initialization state.

The data latch and control signal generator may include a first flip-flop for latching a writable signal output from the state machine, and a counting value output from the counter to output a count start signal for a VBV delay. A second flip-flop, a third flip-flop for generating a control signal for the frame rate latch according to the control signals output from the state machine and the counter, and a VBV size latch according to the control signals output from the state machine and the counter, respectively And a fourth flip-flop for generating a control signal for the second flip-flop and a fifth flip-flop for generating a control signal for the VBV buffer delay according to the control signals output from the state machine and the counter, respectively.

1 is a block diagram of a video decoder applied to a general HDTV system;

2 is a detailed configuration diagram of a conventional preprocessor;

3 is a structural diagram of a video stream input to FIG. 1;

4 is a block diagram of a preprocessor for adjusting the decoding time of a video decoder according to the present invention;

5 is a state transition diagram of the state machine of FIG.

<Explanation of symbols for main parts of drawing>

110: shift register section

120: start signal detector

130: state machine

140: counter

150: data latch and control signal generator

160: frame rate latch unit

170: VBV buffer size latch portion

180: VBV buffer delay value latch unit

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention according to the technical spirit as described above in detail.

4 is a block diagram of a preprocessor for adjusting the decoding time of a video decoder according to the present invention.

As shown, a shift register unit 110 for sequentially shifting an input video stream; A start code detector 120 for detecting a start code from data output from the shift register unit 110; A state machine 130 that receives a signal output from the start code detector 120 as an enable signal Enna and extracts a sequence header from data output from the shift register 110 to control recording of an input video stream. )and; A counter 140 controlling a counting operation according to a signal output from the start code detector 120 and outputting a count value; Frame rate and VBV are latched and output according to control signals outputted from the state machine 130 and the counter 140, respectively, by latching and outputting the recordable signal and the count start signal outputted from the state machine 130 and the counter 140, respectively. A data latch and control signal generator 150 for generating a control signal for latching the buffer size and the VBV buffer delay value; A frame rate latch unit 160 for latching and outputting frame rate data obtained from the shift register unit 110 according to a control signal output from the data latch and control signal generation unit 150; A VBV buffer size latch unit 170 for latching and outputting VBV buffer size data obtained from the shift register unit 110 according to a control signal output from the data latch and control signal generator 150; The VBV buffer delay value latch unit 180 latches and outputs the VBV buffer delay value obtained by the shift register unit 110 according to the control signal output from the data latch and control signal generator 150.

The data latch and control signal generator 150 latches a first flip-flop 151 for latching a recordable signal output from the state machine 130 and a counting value output from the counter 140. Second flip-flop 152 outputting the count start signal for the VBV delay, and a control signal for the frame rate latch according to control signals output from the state machine 130 and the counter 140, respectively. A third flip-flop 153, a fourth flip-flop 154 for generating a control signal for the VBV size latch according to the control signals output from the state machine 130 and the counter 140, and the state machine ( 130 and a fifth flip-flop 155 for generating a control signal for the VBV buffer delay according to the control signals output from the counter 140 and the counter 140, respectively.

The operation of the preprocessor for adjusting the decoding time of the video decoder according to the present invention configured as described above will be described with reference to FIG. 5.

First, the shift register unit 110 shifts and outputs a video stream input to the first to fifth shift registers 111 to 115 five times in byte units.

Next, the start code detector 120 searches for the output signals of the first to fourth shift registers 111 to 114 in the shift register unit 110, and then the fourth, third and second shift registers 114 ( 113) When the output of 112 becomes 0x "1", the start code detection signal start_code is output. This signal is used as the enable signal Ena of the state machine 130 and at the same time as the clear signal of the counter 140.

The state machine 130 is driven when a signal detected by the start code is input from the start code detector 120, and the state machine 130 transitions according to the signal S1 output from the shift register unit 110. The register unit 110 generates a write enable signal WE and other control signals of the delayed video stream.

Here, as shown in FIG. 5, the state machine 130 includes an initialization state S1, a sequence-header extraction state S2, a picture header wait state S3, a picture header extraction state S4, and a body state S5. Transition operation is performed in five states of), and a control signal is generated accordingly.

In other words, when a clear signal that is a signal for initializing the preprocessor is input, the state machine 130 enters an initialization state S1. The change of state is possible only when the start code (start_code) occurs and when a clear signal is input. When the start code (start_code) occurs in the initialization state, the value of the fourth shift register 114 among the output signals of the shift register unit 110 is checked. If the value is 0x "B3" (the content of the video stream is a sequence header) When the state transitions to the sequence header extraction state S2 and the value of the fourth shift register 114 is not 0x "B3", the initialization state is maintained. If the output value of the fourth shift register 114 is 0x "0" in the sequence header extraction state S2, the transition to the picture header extraction state S4 is performed. If the output value is not 0x "0", the picture is in the current state. The header waiting state S3 is maintained. In the picture header extraction state S4, when a start code start_code is generated, the state transitions to the body state S5. In the body state S5, the current state is maintained until the clear signal is generated.

The start code values mentioned above are shown in Table 1-1 below.

Name Start code value Sequence_start_code B3 Group_of_Picture_start_code B8 Picture_start_code 00 Sequence_end_code B7

The counter 140 counts from 0 to 11, and the count value is 4 bits (cnt []). The cnt [] becomes a value of 0 when a start code signal is input. The cnt [] is incremented every clock to 11 to maintain the current value. The value of this counter 9140 indicates the number of bytes after each header in the stream contents.

In addition, when the state machine 130 is in the initialization state, the first sequence header of the content of the input video stream cannot be found, and the rest of the state is the content after the sequence header. Therefore, in the video stream output through the shift register unit 110, data should be stored in the VBV-buffer only when the state of the state machine 130 is a sequence header extraction state, a picture header waiting state, a picture header extraction state, and a body state. The state machine 130 outputs a recordable signal / WE only in a state where the sequence header is found.

The writable signal output as described above is latched by the first flip-flop 151 in the data latch and control signal generator 150 and then transferred to the VBV buffer unit (13 in FIG. 1).

On the other hand, including the sequence header for controlling the VBV buffer, the frame-rate present in the eighth byte, the VBV buffer size in the eleventh byte, and the VBV buffer delay value in the sixth, seventh, and eighth bytes of the picture part. The state of the state machine 130 and the value of the counter 140 are used to extract the parameters.

That is, when the state of the state machine 130 is a sequence header extraction state and the value of the counter 140 is 3, the third flip-flop 153 in the data latch and control signal generator 150 generates frame rate data. An enable signal for extraction is generated, and the enable rate signal drives the frame rate latch unit 160 to latch the frame rate.

In addition, when the state of the state machine 130 is a sequence header extraction state and the value of the counter 140 is 7, the fourth flip-flop 154 in the data latch and control signal generator 150 has a VBV buffer size. An enable signal for extraction is generated, and by the enable signal, the VBV buffer size latch unit 170 drives to latch the VBV buffer size.

In addition, when the state of the state machine 130 is a picture header state and the value of the counter 140 is 3, the fifth flip-flop 155 in the data latch and control signal generation unit 150 has a VBV buffer delay value. An enable signal for extraction is generated, and the enable signal causes the VBV buffer delay value latch unit 180 to drive to latch the VBV buffer delay value.

As described above, the present invention extracts a sequence header of an input video stream and extracts a parameter for controlling the input video stream in the state where the sequence header is extracted, thereby providing accuracy in parameter extraction and thus decoding error. There is an advantage that can be prevented.

Claims (3)

A preprocessor for controlling a VBV buffer for storing an encoded input video stream, A shift register section for sequentially shifting the input video stream; A start code detector for detecting a start code from data output from the shift register section; A state machine which receives a signal output from the start code detector as an enable signal and extracts a sequence header from data output from the shift register section to control recording of an input video stream; A counter for controlling a counting operation according to a signal output from the start code detector and outputting a count value; Latches and outputs a recordable signal and a count start signal output from the state machine and the counter, respectively, and latches a frame rate, a VBV buffer size, and a VBV buffer delay value according to the state signal and the count value output from the state machine and the counter. A data latch and control signal generator for generating a control signal for performing the control; A frame rate latch unit for latching and outputting frame rate data obtained from the shift register according to a control signal output from the data latch and control signal generator; A VBV buffer size latch unit for latching and outputting VBV buffer size data obtained from the shift register in accordance with a control signal output from the data latch and control signal generator; And a VBV buffer delay value latch unit for latching and outputting a VBV buffer delay value obtained from the shift register according to a control signal output from the data latch and control signal generator. Pretreatment unit. The method according to claim 1, wherein the state machine transitions to an initialization state when the signal S1 obtained from the shift register unit is a clear signal, and transitions to a sequence header extraction state when the signal is "B3" in the initialization state, When the signal is "0" in the sequence header extraction state, the signal transitions to the picture header extraction state. When the picture is extracted in the picture header extraction state, the signal transitions to the body state. In the body state, the input signal S1 is "B7". And a preprocessing device for controlling the decoding time of the video decoder, wherein the transition to the initialization state is performed. The count start signal of claim 1, wherein the data latch and control signal generator comprises: a first flip-flop for latching a writable signal output from the state machine; and a counting value output from the counter; A second flip-flop to be output to the third flip-flop for generating a latch enable signal for frame rate extraction when the state of the state machine is a sequence header extraction state and the counter value is 3; Is a sequence header extraction state and the value of the counter is 7, the fourth flip-flop generating an enable signal for extracting the VBV buffer size, the state of the state machine is the picture header state, and the value of the counter is 3, the fifth flip-flop generates an enable signal for extracting the VBV buffer delay value. Pretreatment device.