KR20000045355A - Overlay mark of semiconductor device - Google Patents

Overlay mark of semiconductor device Download PDF

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Publication number
KR20000045355A
KR20000045355A KR1019980061913A KR19980061913A KR20000045355A KR 20000045355 A KR20000045355 A KR 20000045355A KR 1019980061913 A KR1019980061913 A KR 1019980061913A KR 19980061913 A KR19980061913 A KR 19980061913A KR 20000045355 A KR20000045355 A KR 20000045355A
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KR
South Korea
Prior art keywords
mark
semiconductor device
overlap
superimposed
pattern
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KR1019980061913A
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Korean (ko)
Inventor
백승원
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김영환
현대전자산업 주식회사
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Priority to KR1019980061913A priority Critical patent/KR20000045355A/en
Publication of KR20000045355A publication Critical patent/KR20000045355A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark

Abstract

PURPOSE: An overlay mark of a semiconductor device is provided to measure simultaneously a critical dimension and an overlay rate between processes by forming overlay marks. CONSTITUTION: An overlay mark of a semiconductor device comprises a first overlay mark(15) and a second overlay mark. The first overlay mark comprises an inner box and an outer box. The inner box and the outer box have a uniform thickness and the same size. An edge portion one side of the inner box is adjacent to an edge portion of one side of the outer box toward a diagonal line direction. The second overlay mark is formed by the same shape as the first overlay mark. The second overlay mark is overlaid with the second overlaid mark when the second overlay mark is rotated as much as 90°.

Description

반도체 소자의 중첩마크Overlap Mark of Semiconductor Device

본 발명은 반도체 소자의 중첩마크(Overlay Mark)에 관한 것으로, 특히 두 개의 인너(inner) 및 아웃박스(out box)를 같은 크기로 제작하고, 서로 교차되면서 인접한 중첩마크를 형성하고, 이를 이용하여 형성된 패턴의 임계치수(Critical Demension ; 이하 'CD' 라 함)와 공정간의 중첩도를 동시에 측정할 수 있는 반도체 소자의 중첩마크에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overlay mark of a semiconductor device. In particular, two inner and out boxes may be manufactured in the same size, and the adjacent overlap marks are formed while crossing each other. The present invention relates to an overlap mark of a semiconductor device capable of simultaneously measuring a critical dimension (hereinafter, referred to as 'CD') of an formed pattern and an overlap between processes.

일반적으로 반도체 소자의 제조공정 중, 현재 소정의 패턴을 형성하기 위한 공정을 진행하기 위해서는, 그 이전에 형성된 층(layer)과의 정렬(align)이 잘 이루어진 상태에서 진행되어야 한다.In general, in order to proceed with the process for forming a predetermined pattern in the manufacturing process of the semiconductor device, it must proceed in a state that the alignment with the layer (former) previously formed well.

즉, 이전 공정에 의해 형성된 층과 현재의 진행하고자 하는 층이 정확하게 정렬이 된 상태에서 공정이 진행되어야 하므로 중첩도 측정은 반도체 소자 제조공정에 있어서 필수적으로 선행되어야 하는 매우 중요한 요소이다.That is, since the process must proceed in a state where the layer formed by the previous process and the current layer to be processed are precisely aligned, the degree of overlap measurement is a very important factor that must be preceded in the semiconductor device manufacturing process.

이를 위하여 종래에는 다음과 같은 중첩마크를 주로 사용하여 왔다.To this end, conventionally, the following overlap marks have been mainly used.

크기가 다른 두 개의 정사각박스 형태의 패턴을 형성하고, 상기 두 개의 박스중 하나는 다른 하나의 박스 내측에 삽입되게 하여 상기 두 패턴간의 위치관계를 파악하여 두 개의 층간의 정렬도를 측정하였다.Two square box-shaped patterns having different sizes were formed, and one of the two boxes was inserted into the other box to determine the positional relationship between the two patterns to measure the degree of alignment between the two layers.

그러나 상기와 같은 종래의 정사각 박스형태의 중첩마크는 집적도가 상대적으로 낮은 소자부터 계속 적용되어 사용되어지고 있으나, 반도체 소자의 집적화가 더욱 이루어질 경우에는 형성되는 패턴의 크기에 비해 중첩마크의 패턴 크기가 너무커 실제적인 층간의 정렬도를 나타내는 데 어려움이 따른다.However, the conventional overlapping mark in the form of a square box as described above has been used since relatively low integration device, but when the integration of the semiconductor device is further made, the pattern size of the overlap mark is larger than the size of the formed pattern. Too large it is difficult to show the degree of alignment between the layers.

또한 종래에는 CD 나 중첩정도를 측정하기 위해서는 CD를 측정하기 위한 패턴과 중첩도를 측정을 하기 위한 패턴을 각각 따로 만들어서 각각의 전용 장비를 사용하여 측정을 해야하므로, 작업이 번거롭고, 측정에 따른 시간이 많이 소요되는 문제점이 있다.In addition, conventionally, in order to measure the degree of CD or overlapping, the pattern for measuring CD and the pattern for measuring the degree of overlap must be made separately and measured using each dedicated equipment, which is cumbersome, and the time required for measurement This is a problem that takes a lot.

아울러 상기한 종래의 방법은 중첩도를 측정함에 있어, 좌측과 우측의 중첩도만을 확인할 수 있고, 상,하 방향으로의 중첩정도를 알기 위해서는 웨이퍼를 90도 다시 회전시킨 후 측정해야 하는 불편이 따르는 등의 문제점이 있다.In addition, in the above-described conventional method, the degree of overlap between the left and the right sides can be confirmed in measuring the degree of overlap, and in order to know the degree of overlap in the up and down directions, it is inconvenient to measure the wafer after rotating the wafer 90 degrees again. There is such a problem.

따라서 본 발명은 상기의 종래의 문제점을 해결하기 위한 것으로, 본 발명은 두 개의 인너 및 아웃박스를 같은 크기로 제작하고, 서로 대각선 방향으로 인접하는 중첩마크를 형성 및 이용함에 의해 형성된 패턴의 CD 와 공정간의 중첩도를 동시에 측정할 수 있게 하여 반도체 소자의 제조공정 수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 중첩마크를 제공함에 그 목적이 있다.Therefore, the present invention is to solve the above-mentioned conventional problems, the present invention is to produce the two inner and the outer box of the same size, and by forming and using the overlapping marks adjacent to each other diagonally with the CD of the pattern formed It is an object of the present invention to provide an overlap mark of a semiconductor device capable of simultaneously measuring the degree of overlap between processes, thereby improving the yield and reliability of the manufacturing process of the semiconductor device.

도 1 은 본 발명에 의한 제1 중첩마크를 도시한 도면1 is a view showing a first overlap mark according to the present invention;

도 2 는 본 발명에 의한 제2 중첩마크를 도시한 도면2 is a view showing a second superimposed mark according to the present invention;

도 3 은 본 발명의 중첩마크를 도시한 도면3 is a diagram illustrating an overlap mark of the present invention;

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1,3 : 동일한 크기의 인너 및 아웃박스로 된 중첩마크 패턴1,3: Overlapping mark pattern with inner and outbox of same size

11 : 제1 중첩마크 13 : 제2 중첩마크11: first overlap mark 13: second overlap mark

15 : 본 발명의 중첩마크15: superposition mark of the present invention

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 중첩마크는,The overlap mark of the semiconductor device according to the present invention for achieving the above object,

인너박스와 아웃박스를 균일한 두께, 같은 크기로 형성하되, 상기 각 박스의 일측 모서리부를 대각선 방향으로 인접하도록 위치시켜 구성한 제1 중첩마크와,A first overlap mark formed of an inner box and an outer box with a uniform thickness and the same size, and having one corner portion of each box positioned adjacent to each other in a diagonal direction;

상기 제1 중첩마크와 동일한 형상으로 형성되되, 90도 회전할 경우 상기 제1 중첩마크와 중되는 제2 중첩마크를 구비하여, 패턴의 CD 및 공정 전후의 중첩도를 동시에 측정할 수 있는 것을 특징으로 한다.The first overlap mark is formed in the same shape as the first overlap mark, and when rotated 90 degrees, the first overlap mark and the second overlap mark are weighted, so that the CD of the pattern and the degree of overlap before and after the process can be simultaneously measured. It is done.

이하 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 중첩마크의 일실시예에 대한 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the overlap mark of the semiconductor device according to the present invention.

도 1 내지 도 3 은 본 발명에 따른 반도체 소자의 중첩마크를 도시한 도면이다.1 to 3 are views illustrating overlap marks of a semiconductor device according to the present invention.

도 1 은 본 발명에 의한 제1 중첩마크 패턴(11)으로, 두 개의 인너 및 아웃박스(1)를 같은 크기 및 균일한 두께로 제작한 후, 서로 결착되게 구성한 것이다. 즉 두 개의 인너 및 아웃박스(1,3)의 일측 모서리부가 접한상태에서 서로 대각선 방향으로 대향해 있는 형태로 형성한 중첩마크 패턴이다.1 is a first overlap mark pattern 11 according to the present invention, after the two inner and the outer box 1 is manufactured in the same size and uniform thickness, it is configured to bind to each other. That is, it is a superimposed mark pattern formed in a form in which the two inner and outer boxes 1 and 3 are in contact with each other in a diagonal direction while being in contact with each other.

상기 제1 중첩마크 패턴(11)은 본 공정의 앞 단계에서 형성된 중첩마크 패턴이다.The first overlap mark pattern 11 is an overlap mark pattern formed in the previous step of this process.

도 2 는 상기 도 1 에 도시된 제1 중첩마크 패턴(11)과 동일한 형태의 제2 중첩마크(13) 패턴으로 상기 제1 중첩마크 패턴(11)과는 90도 방향으로 회전한 상태의 패턴이다.FIG. 2 is a pattern of a second superimposed mark 13 having the same shape as the first superimposed mark pattern 11 shown in FIG. 1 and rotated in a 90 degree direction with the first superimposed mark pattern 11. to be.

도 3 은 본 발명에 따라 상기 제1 중첩마크 패턴(11)과 제2 중첩마크 패턴(13)이 현재의 공정에서 함께 형성된 상태의 도면이다.3 is a view showing a state in which the first overlap mark pattern 11 and the second overlap mark pattern 13 are formed together in the present process according to the present invention.

상기 도시된 본 발명의 중첩마크(15)에 있어서, 지역(A)와 지역(B)을 측정함에 의해 현 공정에서 형성된 패턴의 CD 값을 측정할 수 있으며, 또한 앞 공정에서 형성된 패턴들이 적합한 공정, 예컨데 식각공정이나 도포공정과 같은 공정에 따라 CD의 변화폭을 알 수 있으며, 상대적으로 그 오차를 예측할 수가 있다.In the superimposed mark 15 of the present invention shown above, by measuring the area (A) and the area (B), it is possible to measure the CD value of the pattern formed in the current process, and the pattern formed in the previous process is a suitable process For example, the variation of CD can be known according to the process such as etching process or coating process, and the error can be predicted relatively.

또한 상기 도시된 본 발명의 중첩마크(15)에 있어서, 제1 중첩마크(11)와 제2 중첩마크(13)가 서로 접하는 부분인 지역(C)를 측정하고, 지역(A)와 지역(B)에서의 측정값을 서로 합한 값에 상기 지역(C)에서의 측정값을 뺀 값이 바로 중첩값이 되므로 중첩정도를 바로 알 수가 있다.In addition, in the superimposed mark 15 of the present invention shown in the above, the first superimposed mark 11 and the second superimposed mark 13 measure an area C which is a part in contact with each other, and an area A and an area ( Since the value obtained by subtracting the measured value in B) from the measured value in the region C becomes the overlapping value, the degree of overlapping can be immediately known.

이때 만약 큰 오차를 갖는 중첩값을 가졌다면, 측정중 측정신호가 지역(C) 영역에서 바로 구분할 수 있을 정도로 나타나므로 그 값을 읽게 되면 허용오차를 얼마만큼 벗어났는 지를 확연히 알 수 있게 된다.At this time, if there is an overlapping value with a large error, the measurement signal appears to be distinguishable in the area (C) area during the measurement. Therefore, when reading the value, it is possible to clearly know how far the tolerance is.

또한 상기 본 발명의 중첩마크(15)에 있어서, 지역(D)와 지역(E)에서 측정하여 비교함으로써 정렬이 얼마만큼 회전되었는지도 확인할 수 있다.In addition, in the superimposed mark 15 of the present invention, it is also possible to check how much the alignment is rotated by measuring and comparing the area D and the area E. FIG.

이상 상술한 바와 같이, 본 발명에 따른 반도체 소자의 중첩마크는 크기가 같고 균일한 두께로 제작된 인너 및 아웃박스가 결합된 형태, 즉 상기 인너 및 아웃박스의 모서리부를 서로 접한 상태에서 대각선 방향으로 대향해 있는 형태로 구성한 제1 중첩마크와, 상기 제1 중첩마크와 동일한 형상으로 형성되고, 상기 제1 중첩마크와 중첩시 90도 회전되어 결착되는 제2 중첩마크를 구비하여, 중첩마크의 소정영역을 측정함에 의해 감광막 패턴의 CD 와, 공정후 변한 CD의 상대적 오차의 확인이 가능하며, 또한 상기 제1 중첩마크와 제2 중첩마크가 접하는 두 부분을 측정함에 의해 중첩값을 얻을 수 있으며, 아울러 두 개의 값을 비교하여 정렬이 얼마나 회전되었는 가를 알 수 있어 중첩오차의 폭을 최소화할 수 있고, 측정시간을 줄여 장비의 이용효율을 높일 수 있으며, 중복된 장비의 구매 및 사용으로 비용의 절감을 기할 수 있다.As described above, the overlap mark of the semiconductor device according to the present invention has a shape in which the inner and the outer box are made of the same size and have a uniform thickness, that is, the corners of the inner and the outer box are in contact with each other in a diagonal direction. A first overlap mark formed in an opposite shape, and a second overlap mark formed in the same shape as the first overlap mark, and rotated by 90 degrees when overlapped with the first overlap mark, so as to define the overlap mark. By measuring the area, it is possible to confirm the relative error between the CD of the photoresist pattern and the CD changed after the process, and the overlap value can be obtained by measuring two portions where the first overlap mark and the second overlap mark are in contact with each other. By comparing the two values, we can see how much the alignment has been rotated, so that the width of the overlapping error can be minimized. In addition, the cost can be reduced by purchasing and using redundant equipment.

Claims (5)

인너박스와 아웃박스를 균일한 두께, 같은 크기로 형성하되, 상기 각 박스의 일측 모서리부를 대각선 방향으로 인접하도록 위치시켜 구성한 제1 중첩마크와,A first overlap mark formed of an inner box and an outer box with a uniform thickness and the same size, and having one corner portion of each box positioned adjacent to each other in a diagonal direction; 상기 제1 중첩마크와 동일한 형상으로 형성되되, 90도 회전할 경우 상기 제1 중첩마크와 중되는 제2 중첩마크를 구비하여, 패턴의 CD 및 공정 전후의 중첩도를 동시에 측정할 수 있는 반도체 소자의 중첩마크The semiconductor device is formed in the same shape as the first superimposed mark, and has a second superimposed mark which is the first superimposed mark and the intermediate superimposed mark when rotated 90 degrees so that the CD of the pattern and the degree of superimposition before and after the process can be simultaneously measured. Overlap Mark 제 1 항에 있어서The method of claim 1 상기 중첩마크에 있어서, 상기 제1 중첩마크와 제2 중첩마크가 접하는 두 개의 지역(D, E)에서 측정한 중첩값을 서로 비교함에 의해 회전정렬의 오차정도를 구할 수 있도록 한 것을 특징으로 하는 반도체 소자의 중첩마크.In the superimposed mark, an error degree of rotational alignment can be obtained by comparing the superimposed values measured in two regions (D, E) where the first superimposed mark and the second superimposed mark are in contact with each other. Overlap mark of semiconductor device. 제 1 항에 있어서The method of claim 1 상기 중첩마크에 있어서, 앞 공정 패턴의 CD값과 현 공정 패턴의 CD 값의 상대적 오차를 구하여 CD 바이어스를 구하는 것을 특징으로 하는 반도체 소자의 중첩마크In the superimposed mark, the superimposed mark of the semiconductor device, wherein the CD bias is obtained by obtaining a relative error between the CD value of the previous process pattern and the CD value of the current process pattern. 제 1 항에 있어서The method of claim 1 상기 중첩마크에 있어서, 패턴의 라운드니스(Roundness)는 앞 공정에서 패터닝후의 각 박스의 에지 부분의 데미지를 현 공정의 CD와 비교함에 의해 측정하는 것을 특징으로 하는 반도체 소자의 중첩마크.In the superimposed mark, the roundness of the pattern is measured by comparing the damage of the edge portion of each box after patterning in the previous process with the CD of the current process. 제 1 항에 있어서The method of claim 1 상기 중첩마크에 있어서, 소정 공정(식각,도포 등)에서의 공정마진은 상기 제4항 또는 제4항에 의해 예측하는 것을 특징으로 하는 반도체 소자의 중첩마크.The superimposition mark of the semiconductor device according to claim 4, wherein the process margin in a predetermined process (etching, coating, etc.) is predicted according to claim 4 or 4.
KR1019980061913A 1998-12-30 1998-12-30 Overlay mark of semiconductor device KR20000045355A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100816192B1 (en) * 2006-08-24 2008-03-21 동부일렉트로닉스 주식회사 Semiconductor device having alignment mark
US11119414B2 (en) 2013-12-17 2021-09-14 Asml Netherlands B.V. Yield estimation and control

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100816192B1 (en) * 2006-08-24 2008-03-21 동부일렉트로닉스 주식회사 Semiconductor device having alignment mark
US11119414B2 (en) 2013-12-17 2021-09-14 Asml Netherlands B.V. Yield estimation and control

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