KR20000044787A - Video data interpolation device for switching direction of interpolated pixel data - Google Patents

Abstract

PURPOSE: A video data interpolation device for switching a direction of interpolated pixel data is provided to transform vertical processing pixel data to horizontal processing pixel data. CONSTITUTION: A video data interpolation device for switching a direction of interpolated pixel data comprises a memory group(100), an interpolation filter(200), a shift register(300), a control portion(500), and a filter memory group(400). The memory group is formed with data memories of n number for storing parallel video data of n number. The interpolation filter outputs directly interpolated video data from the input video data of n number. The shift register shifts and stores the interpolated data of each n clock period toward a first direction and shifts and outputs the stored interpolated data of n number toward a second direction. The control portion outputs an address control signal for reading sequentially the interpolated data toward a vertical direction and a control signal for shifting the interpolated data toward the first and the second directions. The filter memory group is formed with filter memories of n number for storing the interpolated data of n number shifted toward the second direction.

Description

Image data interpolation device for changing the interpolated pixel data direction

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image data interpolation apparatus of a digital television signal processing apparatus, and more particularly, to an interpolation apparatus having a modified shift register for converting vertically processed pixel data into horizontally processed pixel data.

Television, one of the representative media of modern society, has been developed with the introduction of digital technology with the advent of the digital era, and recently, it has been developed into a digital television such as high definition television (HDTV). Digital TVs such as HDTVs are attracting attention as new media that can maximize the realism by increasing the clarity, compact disc quality, and aspect ratio of the screen, compared to conventional analog TVs.

Since the quality of a television's screen is proportional to the signal received by the receiver, no matter how large the screen can be, if the amount of information received is the same, the screen will be blurred and the image quality will be lower. The technique of increasing the number of scan lines forming a frame is used. As is well known, the US NTSC standard has 525 scan players, while the European PAL and SECOM systems have 625 lines, whereas digital TVs, such as HDTV, now double the number of scan lines of traditional analog television. It can provide five times more information and dramatically improve image quality.

In order to display a video signal on a digital television, an image signal consisting of a series of image "frames" must be converted into a digital form and transmitted to the digital television. However, since the usable frequency range of a conventional transmission channel is limited, in order to transmit a large amount of digital data, the amount of data transmitted is compressed to reduce the amount. Among these compression techniques, the hybrid coding scheme combining probabilistic coding and temporal and spatial compression is known to be the most efficient. A video signal compressed using such an encoding method is transmitted to a receiver and decoded to be reproduced as a desired video signal.

On the other hand, although digital television has a resolution of 1920 x 1080, since decoded digital image data is applied at 640 x 480 or 704 x 480 resolution, an interpolation filter is used to match the resolution of 1920 x 1080 of digital television. The necessary image data should be generated by interpolation by up filtering. Interpolation of image data generates at least one or more new pixel data using one image data, that is, pixel data. In general, interpolation principle creates an interpolated pixel value by selecting an intermediate value between a series of pixel data. Giving is used.

A typical interpolation filter device is digital image data, i.e., pixel data D00, D10, D01, D11, D02, D12, D03, D13,. A plurality of digital image data D00, D01, D02, D03, sequentially read from each memory in the data memory group 10 and a memory group 10 consisting of respective data memories for receiving and storing. And interpolation filter 20 which interpolates the intermediate pixel data required to generate new pixel data F00, F01, F02, F03, .... At this time, the pixel data interpolated by the interpolation filter 20 is stored in the filter memory group 30 composed of respective filter memories for interpolation of new pixel data, and is also output to the display apparatus through a video processing circuit (not shown).

As clearly illustrated in FIG. 1, the pixel data in the vertical direction output from the data memory group 10 is interpolated and filtered in the interpolation filter 20 and then in the vertical direction as it is in each filter memory in the filter memory group 30. You can see that it is being saved. However, since the interpolation data stored in each filter memory in the filter memory group 30 is processed in the horizontal direction, a separate direction changing device is required at the front end of the video processing circuit to convert the interpolated data in the horizontal direction. have. For this reason, the configuration of the video processing circuit becomes complicated, which makes it difficult to control the entire system.

Accordingly, the present invention has been made to solve the above-described problem, and provides a digital image data interpolation apparatus capable of converting a data storage order by converting pixel data processed in a vertical direction in a horizontal direction in a digital image data interpolation apparatus in a horizontal direction. For that purpose.

According to an aspect of the present invention, there is provided a filter device including: a data memory group including n data memories for temporarily storing n parallel input image data; An interpolation filter for serially outputting one image data interpolated therefrom using n pieces of image data input every clock period; A modified shift register for shifting and storing the interpolated data output in series from the interpolation filter in a first direction every n clock periods, and for shifting the stored n interpolated data in parallel in a second direction; Outputs an address control signal AD for sequentially reading the data to be interpolated from each data memory in the data memory group in the vertical direction, and controls for shifting the modified shift register in the first and second directions Control means for generating a signal; And a filter memory group consisting of n filter memories each storing n interpolation data shifted in the second direction from the modified shift register.

1 is a block diagram of a data interpolation apparatus of a digital television of the prior art;

2 is a block diagram of a data interpolation apparatus of a digital television constructed in accordance with the present invention;

3 is a circuit diagram illustrating a detailed configuration of the modified shift register shown in FIG.

4 illustrates operation timing for driving the shift register of FIG.

<Description of the symbols for the main parts of the drawings>

100: data memory group 200: interpolation filter

300: modified shift register 311,. . . , 344: shift register cell

M: Multiplexer D: D-Type Flip-Flops

400: filter memory group

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Fig. 2 is a block diagram of an image data interpolation apparatus for digital television according to the present invention, wherein the image data interpolation apparatus of the present invention performs 1: 2 interpolation processing.

The data interpolation apparatus of the present invention includes a filter memory group 400 including a data memory group 100, an interpolation filter 200, a modified shift register 300, and a plurality of filter memories. .

The memory group 100 is composed of n, for example four data memories 110, 1120, 130, 140, each of which is in parallel from an unillustrated data rearrangement means. Each of n provided, i.e., four digital image data is stored. As can be seen with reference to the data sequence illustrated at the bottom of FIG. 2, the data D00, D10, D20, D30,... Are sequentially stored in the first data memory 110, and the second data memory ( The data D01, D11, D21, D31,... Are sequentially stored in the first to fourth data memories 110 to 140 in the vertical direction. In addition, the data stored in each of the data memories 110, 120, 130, and 140 in the memory group 100 are sequentially read and interpolated from each memory by the address signal AD provided from the controller 500. It is output to the filter 200 side.

The interpolation filter 200 outputs one image data interpolated therefrom using vertical image data provided from the data memory group 100. Interpolation data output from the interpolation filter 200 is provided to the filter memory group 400 via the modified shift register 300 according to the present invention.

Referring to Figure 3, a detailed configuration of a modified shift register 300 according to the present invention is shown. As shown, the shift register 300 of the present invention consists of n * m, e.g., shift register cells 311, ..., 344 in a 4 * 4 matrix, each shift register cell being a two-input. A 1-output multiplexer (M) and a D-type flip-flop (D). Where n corresponds to the number of data memories, and m represents the maximum number of data that can be stored in each memory. Shift register cells 311,..., 344 in each column shift the interpolation data provided from the interpolation filter 300 to the right in accordance with the timing shown in FIG. 4, and the lower end according to the timing shown in FIG. 4, respectively. And to receive interpolated data shifted from a shift register cell of a column. The modified shift register 300 converts the interpolation data input in the vertical direction from the interpolation filter 200 in the horizontal direction by the operation as described in detail below, and provides the converted shift register 300 to the next filter memory group 400. In addition, null is provided for the type force terminal that does not receive interpolation data or shifted interpolation data in each multiplexer M in the last fourth column 311, 312, 313, 134 of the modified shift register 300. Data, for example "0".

Again, in FIG. 2, the filter memory group 400 composed of n, that is, four filter memories 410, 420, 430, and 440 is provided with interpolation data provided by being redirected horizontally from the modified shift register 300. F00, F01, F02, F03; F10, F11, F12, F13; F20, F21, F22, F23; F30, F31, F32, F33) are stored sequentially.

The controller 500 sequentially reads data from each of the memories 110, 120, 130, and 140 in the memory group 100 at every cycle of the clock CLK illustrated in FIG. 4, and interpolates through the read data. A control signal such as an address signal AD or the like is generated to be provided to the filter 200. In addition, the control unit 500 converts the interpolation data in the vertical direction output from the interpolation filter 200 every n clock periods of the clock CLK, that is, every 4 clock periods, and then converts the horizontal interpolation data in the modified shift register 300 in the horizontal direction. The multiplexer selection control signal MS is generated and provided to the shift register 300. The multiplexer selection control signal MS is the same as dividing the frequency of the address signal AD by four.

The operation of the data interpolation apparatus of the present invention having the above-described configuration will be described in detail as follows with reference to the timing diagram of FIG.

First, the image data interpolation apparatus of the present invention uses data D00, D01 from each memory 110, 120, 130, 140 by an address signal AD provided from the controller 100 at the beginning of the system clock CLK. , D02 and D03 are provided to the interpolation filter 200. The interpolation filter 200 outputs interpolation data F0 processed using the previous four data to the modified shift register 300 and generates new interpolation data F1. Since the above-described process is repeatedly performed, the interpolation filter 200 sequentially outputs interpolation data F00, F01, F02, and F03 processed in the vertical direction, and interpolation data processed in the vertical direction from the interpolation filter 300. (F00, F01, F02, F03) are applied to the shift register cells 314, 324, 334, and 344 of the first row in the modified shift register 300.

Shift register cells 314, 324, 334, and 344 of each row in the shift register 300 modified during four periods of the clock CLK shown in Fig. 4, that is, during the high level period of the multiplexer selection control signal MS; The interpolation data is shifted to the right by the selection control signal MS provided to the control terminal of the multiplexer M in 313, 323, 333, 343; 312, 322, 332, 342; 311, 321, 331, and 341. do. At the same time, multiplexer M in each shift register cell 314, 324, 334, 344; 313, 323, 333, 343; 312, 322, 332, 342; 311, 321, 331, 341 The interpolation data shifted from the lower flip flop D is received through the input terminal.

In the next clock period, the shift register cells 314, 324, 334 of the first row in the shift register 300 in which the interpolation data F10, F11, F12, F13 processed in the vertical direction from the interpolation filter 300 are modified. 344, the interpolation data is shifted to the right by the selection control signal provided to the control terminal of each multiplexer M, and the shift register cells 314, 324, 334 and 344 of each row; Multiplexers M in 313, 323, 333, 343; 312, 322, 332, 342; 311, 321, 331, and 341 again receive data from the flip-flop D below. The above-described process is repeated for four periods of the clock shown in FIG. 4, so that the flip-flops D in the shift register cells 344, 343, 342, and 341 of the first column are interpolated from the interpolation filter 200, respectively. F20, F10, and F00) are stored.

Next, when the multiplexer M in the first column 344, 343, 342, 341 outputs data provided to its type force terminal in accordance with the low-level multiplexer selection control signal shown in FIG. The flip-flops D in the shift register cells 344, 343, 342, and 341 of the columns respectively correspond to stored interpolation data F30, F20, F10, and F00 respectively. , 420, 410 will be output. This process is repeatedly performed during the low level signal period of the multiplexer selection control signal shown in FIG. 4, so that the filter memories 440, 430, 420, and 410 in the filter memory group 400 are illustrated at the lower right of FIG. 2B. As described above, the interpolation data (F00, F01, F02, F03; F10, F11, F12, F13; F20, F21, F22, F23; F30, F31, F32, and F33) converted in the horizontal direction are stored sequentially.

As such, the interpolation data stored in the horizontal direction in each of the memories 410, 420, 430, and 440 in the filter memory group 400 is displayed on the monitor of the digital television through a video signal processor (not shown).

Therefore, since the interpolation data read and processed in the vertical direction in the 1: 2 image data interpolation device is changed in the horizontal direction without post-processing at the rear end of the filter memory, no control for data conversion is necessary. The advantage is that it can be configured more simply.

Claims (2)

A filter device for interpolation of digital image data in digital television, a data memory group consisting of n data memories for temporarily storing n parallel input image data; An interpolation filter for serially outputting one image data interpolated therefrom using n pieces of image data input every clock period; A modified shift register for shifting and storing the interpolated data output in series from the interpolation filter in a first direction every n clock periods, and for shifting the stored n interpolated data in parallel in a second direction; Outputs an address control signal AD for sequentially reading the data to be interpolated from each data memory in the data memory group in the vertical direction, and controls for shifting the modified shift register in the first and second directions Control means for generating a signal; And a filter memory group consisting of n filter memories respectively storing n interpolation data shifted in the second direction from the modified shift register. The method of claim 1, wherein the modified shift register is: A shift register cell of an n * m matrix for shifting n interpolation data serially output from said interpolation filter in said first and second directions; Each shift register cell is: Each input terminal receiving interpolation data shifted in the first direction and interpolation data shifted in the second direction, and selectively receiving the interpolated data in the first direction or the second direction in response to the selection signal; Output to multiplexer; A D-type flip that temporarily latches interpolation data selectively output from the multiplexer and outputs the latched interpolation data to shift register cells coupled to the first and second directions when new data is provided from the multiplexer Interpolation filter device for redirection of interpolated pixel data, characterized in that it has a flop.