JP2556746B2 - Image storage - Google Patents

Description

The present invention relates to an image storage device suitable for a video printer or the like.

<Prior Art> Generally, in the processing of an image signal in a video printer or the like, as shown in FIG. 7, the image signal is sampled at every period T and quantized to perform, for example, a 5-bit binary. It is converted into data and stored in the storage element. Further, at the time of reproduction, binary data is read from the storage element, returned to a sample value, and then smoothed by a low-pass filter to be returned to an image signal.

In this case, from the sampling theorem, the band B of the image signal
It is well known that B = f / 2, where f = 1 / T (sampling repetition frequency).

FIG. 8 is a schematic configuration diagram of an image storage device in a conventional video printer that performs the above-described signal processing.

The input image captured for printing is quantized into 1-bit data by the A / D conversion circuit 1 once by sampling, converted into parallel data by the 1-to-n parallel conversion circuit 2, and n times. Of the sampled data n × 1 bits are stored in the storage element 5.

At the time of reproducing an image, the data read out n × 1 bit at a time is converted into 1-bit serial data by the n: 1 serial conversion circuit 8 and converted into a sample value by the D / A conversion circuit 9, The low pulse filter 10 smoothes and outputs as an image signal. Incidentally, 11 ₀ is a control circuit that controls each unit.

<Problems to be Solved by the Invention> In such an image storage device in a video printer of the conventional example, in order to simplify the circuit configuration and reduce the cost, the sampling frequency is lowered to reduce the capacity of the storage element 5. If it is attempted to reduce the number, the band of the image signal becomes narrow, and there is a problem that the reproduced image deteriorates.

The present invention has been made in view of the above points,
An object of the present invention is to simplify the configuration of the image storage device to reduce the cost and to reduce the deterioration of the reproduced image as much as possible.

<Means for Solving the Problems> In the present invention, in order to achieve the above object, an A / D conversion circuit for converting an input image signal into digital data having a predetermined number of bits, and the A / D conversion circuit. A parallel conversion circuit that converts the output of the circuit into a plurality of sets of parallel data for each predetermined number of bits, and a selection that selects a required number of sets of parallel data from the plurality of sets of parallel data based on a selection signal. A circuit and a selection control circuit that outputs the selection signal that regularly switches each group so that the required number of combinations selected by the selection circuit are different for each field and one line of the image signal, Based on the memory into which the required number of sets of parallel data selected by the selection circuit are written and the required number of sets of parallel data read from the memory, the parallel data not selected by the selection circuit. And an arithmetic circuit for arithmetically outputting interpolation data corresponding to the data, and data reproduction for reproducing and outputting as a plurality of sets of parallel data by interpolating the required number of sets of parallel data read from the memory with the interpolation data. A circuit, a serial conversion circuit for converting a plurality of sets of parallel data from the data reproduction circuit into digital data having the predetermined number of bits, and a D / A conversion circuit for D / A converting the digital data from the serial conversion circuit. It has and.

<Operation> According to the above configuration, not all the sampled image data is stored in the memory, but only the data regularly selected by the selection circuit is stored, and the unstored data is stored by the arithmetic circuit. Since the interpolation is performed using the calculated interpolation data, the storage capacity of the memory can be reduced and the deterioration of the reproduced image can be suppressed.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic configuration diagram of an image storage device in a video printer according to an embodiment of the present invention, and portions corresponding to the conventional example in FIG. 8 are designated by the same reference numerals.

In the image storage device of this embodiment, the storage capacity is reduced,
Moreover, in order to suppress the deterioration of the reproduced image, all the sampled image data are not stored in the storage element, but only the regularly selected data are stored and the unstored data are selected. It is configured as follows so as to be interpolated by the interpolation data calculated based on the above data.

That is, this image storage device converts an input image signal into digital data of a predetermined number of bits (1 bit) and an output of the A / D conversion circuit 1 with a predetermined number of bits. A parallel conversion circuit 2 for converting a plurality of sets (n sets) of parallel data for each number, and a selection circuit for selecting a required number of sets (m sets) of parallel data from the plurality of sets of parallel data based on a selection signal. 3 and a selection control circuit 4 which outputs a selection signal for regularly switching each set so that the required number of combinations selected by the selection circuit 3 are different for each field and one line of the image signal. The selection circuit 3 selects the required number of sets of parallel data selected by the selection circuit 3 into which the parallel data is written, and the required number of sets of parallel data read from the storage device 5. Did not parallel Data to be reproduced and output as a plurality of sets of parallel data by interpolating a required number of sets of parallel data read from the storage element 5 with the calculation circuit 6 that outputs interpolation data corresponding to the data. A reproduction circuit 7, a serial conversion circuit 8 for converting parallel data from the data reproduction circuit 7 into digital data having a predetermined number of bits (1 bit), and digital data from the serial conversion circuit 8 is D / A converted. It is provided with a D / A conversion circuit 9, a low pulse filter 10 to which the output of the D / A conversion circuit 9 is given, and a control circuit 11 for controlling each unit.

The A / D conversion circuit 1 and the parallel conversion circuit 2 are processed in the same manner as in the conventional example. That is, in the A / D conversion circuit 1, the input image signal is quantized into 1-bit data by sampling every period T, and in the 1-to-n parallel conversion circuit 2, 1-bit data is obtained every nT time. It is converted into n sets of parallel data for each, that is, 1 × n bit parallel data.

The selection circuit 3 selects and outputs m sets of data out of the n sets of parallel data from the parallel conversion circuit 2 based on the n-bit selection signal from the selection control circuit 4.

In the memory element 5, 1 × m selected by the selection circuit 3
Bit data is sequentially stored. Therefore, the storage capacity of the storage element 5 can be reduced as compared with the conventional example in which all sampled data of 1 × m bits are sequentially stored.

The selection control circuit 4 outputs a selection signal for regularly switching each set so that the required number of combinations selected by the selection circuit 3 are different for each field and line of the image signal. In this embodiment, as will be described later, the set to be selected is regularly switched depending on whether it is an odd field or an even field, and whether it is an odd line or an even line. The n-bit selection signal is also given to the data reproducing circuit 7.

When reproducing an image, 1 × m-bit parallel data is read from the storage element 5 and given to the data reproducing circuit 7 and the arithmetic circuit 6.

The arithmetic circuit 6 arithmetically outputs, based on the m sets of parallel data read from the storage element 5, interpolation data corresponding to the nm sets of parallel data not selected by the selection circuit 3. For example, on the screen, the average value of the data located above and below or to the left and right of the unselected data is calculated as interpolation data.

The data reproducing circuit 7 which reproduces and outputs as n sets of parallel data by interpolating the m sets of parallel data read from the storage element 5 with the mn sets of interpolation data from the arithmetic circuit 6, performs selection control. Based on the output of this selection position storage circuit 12 and the selection position storage circuit 12 that stores the selection signal from the circuit 4 and controls the reading of the storage element 5 during reproduction, the original temporal correlation is obtained. Thus, the data reproducing section 13 for rearranging the data is provided.

Since the selection position storage circuit 12 stores an n-bit selection signal corresponding to which set of parallel data has been selected by the selection circuit 3, based on this, when reading data from the storage element 5, The control is performed such that the reading is stopped at the timing of reading the data of the unselected group.

The data reproducing section 13 is basically composed of a data selector, and based on the output of the selected position storage circuit 12, the original time of the data read from the storage element 5 and the interpolation data from the arithmetic circuit 6 Are rearranged so that there is a statistical correlation
Output as a set of parallel data.

The n sets of parallel data from the data reproducing unit 13 are converted into 1-bit serial data by the n-to-1 serial conversion circuit 8 as in the conventional case, and are further converted into sampled value sequences by the D / A conversion circuit 9. Further, it is smoothed by the low-pass filter 10 and output.

FIG. 2 is a diagram schematically showing the flow of the above signal processing.

The input image signal is A / D converted into 1-bit quantized data A, B ... Z, Y, and converted by the parallel conversion circuit 2 into n sets of parallel data for each bit. Of the n sets of parallel data, m sets of parallel data A, C ... W, X are selected by the selection circuit 3 and stored in the storage element 5. At the time of reproduction, the interpolation data B ′, Y ′, Z ′ corresponding to the parallel data read out from the storage element 5 from the m sets of parallel data A, C ... W, X and not selected by the selection circuit 3. Are interpolated into n sets of parallel data A, B'C ... X, Y ', Z', and serial conversion circuit 8 produces 1-bit serial data A, B '... Y', Z '. The output image is D / A converted and smoothed.

Next, the selection of data in the selection circuit 3 will be described in detail. For example, a case where n = 4 and m = 3 will be described. In this embodiment, as the selection method of the data in which the input image signal shown in FIG. 3 (A) is sampled, the first to fourth four shown in FIGS. 3 (B) to 3 (E) are used. It adopts the same selection method and switches them regularly. 3 (B) to 3 (E)
Indicates unselected data.

In this embodiment, the odd lines of the odd field are set to the first selection method, and the even lines of the odd field are set to the third selection method.
And the odd lines in the even field are
In the second selection method, the even lines of the even field are selected by the fourth selection method.

FIG. 4 is a diagram showing display dots of an image according to this embodiment, where ● indicates dots corresponding to the data selected by the selection circuit 3, and ○ indicates not selected by the selection circuit 3 and displayed above and below. Each dot corresponding to the interpolation data interpolated by the data is shown.

FIG. 5 shows display dots of a conventional example in which all sampled data are stored and reproduced. Compared with this conventional example, in this embodiment, the storage capacity of the storage element 5 is 3/4. It will be.

Further, as shown in FIG. 6, when the sampling period is 4/3 times that of the conventional case and all the data is stored, in this case, the storage capacity is the same as that of the present embodiment, but The horizontal resolution is superior in the present embodiment for interpolating.

Since the data of all the images sampled in this way is not stored in the storage element 5, the capacity of the storage element 5 can be reduced, and the unstored data is interpolated by the interpolation data and the position to be interpolated. Is changed regularly as shown in FIG. 4, so that the interpolation becomes less noticeable than in the case where the interpolation position is fixed,
It is also possible to suppress deterioration of the reproduced image. In addition, A / D
IC other than conversion circuit 1, D / A conversion circuit 9 and storage element 5
It can be miniaturized by
The cost can be reduced.

The data selection method and the interpolation data calculation method in the selection circuit 3 are not limited to those in the above embodiments.

<Effects of the Invention> As described above, according to the present invention, not all sampled image data is stored in the memory, but only the data regularly selected by the selection circuit is stored and not stored. The data is interpolated by the interpolated data calculated by the arithmetic circuit, and the interpolation position is regularly changed to make it inconspicuous. Therefore, the storage capacity of the memory can be reduced and the deterioration of the image can be suppressed. .

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a diagram for explaining signal processing of the embodiment shown in FIG. 3, FIG. 3 is a diagram for explaining a data selection method, FIG. 4 is a diagram showing display dots in the embodiment of FIG. 1, FIG. FIG. 6 is a diagram showing display dots in a conventional example, FIG. 7 is a diagram for explaining a signal processing method, and FIG. 8 is a block diagram of a conventional example. 1 ... A / D conversion circuit, 2 ... Parallel conversion circuit, 3 ... Selection circuit, 4 ... Selection control circuit, 5 ... Storage element, 6 ... Arithmetic circuit, 7 ... Data reproduction circuit, 8 ... … Serial conversion circuit,
9 ... D / A conversion circuit.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04N 5/907 B41J 3/00 Y

Claims (1)

(57) [Claims] 1. An A / D conversion circuit for converting an input image signal into digital data having a predetermined number of bits, and an output of the A / D conversion circuit is used as a plurality of sets of parallel data for each predetermined number of bits. A parallel conversion circuit for converting into a parallel selection circuit, a selection circuit for selecting a required number of sets of parallel data from the plurality of sets of parallel data based on a selection signal, and a combination of the required number of sets selected by the selection circuit, A selection control circuit that outputs the selection signal that regularly switches each set so as to be different for each field and one line of the image signal, and a memory in which a required number of sets of parallel data selected by the selection circuit are written. An arithmetic circuit for arithmetically outputting interpolation data corresponding to the parallel data not selected by the selection circuit, based on a required number of sets of parallel data read from the memory; The required sets of the parallel data read from the memory,
A data reproduction circuit that reproduces and outputs the plurality of sets of parallel data by interpolating with the interpolation data, and a serial conversion circuit that converts the plurality of sets of parallel data from the data reproduction circuit into the digital data of the predetermined number of bits. And D that converts digital data from this serial conversion circuit to D / A
An image storage device comprising an / A conversion circuit.