KR20000044166A - Automatic gain control circuit of digital television receiving system and method for the same - Google Patents

Abstract

PURPOSE: An automatic gain control circuit of a digital television receiving system and a method for the same are provided to perform accurately an automatic gain control by separating a coarse gain control and a fine gain control. CONSTITUTION: An automatic gain control circuit of a digital television receiving system and a method for the same comprise an analog/digital conversion portion(40), an absolute value generation portion(50), an error detection portion(60), an error estimation portion(70), and an output portion(80). The analog/digital conversion portion converts a received data symbol to a digital value. The absolute value generation portion obtains an absolute value of the converted digital value. The error detection portion detects a mean absolute value from the absolute values corresponding to field synchronization symbols and segment synchronization symbols. The error estimation portion generates coarse gain control data when the mean error value is more than a predetermined range and fine gain control data when the mean error value is less than the predetermined range. The output portion outputs gain control signals corresponding to the coarse and the fine gain control data.

Description

Automatic Gain Control Circuit and Method for Digital Television Receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit and method for a digital television receiver, and more particularly, to an automatic gain control circuit and method capable of fast and precise automatic gain control by dividing into coarse and fine gain control.

Recently, many systems have been researched and developed for transmitting and receiving television signals in digital form. USP 5,087,975 discloses a VSB (Vestigial side band) system for transmitting television signals on a 6 MHz television channel to consecutive M level symbols with a relatively small pilot at the low edge of the channel.

Even if the level M is changed, the symbol rate is properly fixed to 684H (10.76M symbols / second). H is the NTSC horizontal scan frequency. The number of symbol levels used in a particular arrangement is a function of signal to noise ratio. 16, 8, 4 and 2 are provided for cable systems, and 8 is appropriate for terrestrial or over-the-air broadcasts.

Preferred operation of the receiver in a television system requires that the received carrier signal be picked up relatively quickly and the gains of the RF and IF sections of the receiver adjusted appropriately. The use of pilots in a VSB system facilitates carrier acquisition, but carrier acquisition is never easy, because the pilot is relatively low level.

Accordingly, U.S. Patent 5,565,932 samples the level of the received data symbols, accumulates and divides the sampled signal to obtain an average value, subtracts the reference value from the obtained average value, detects an error, and generates a gain control signal in response to the detected error. do.

This patent does not guarantee that the symbol data will converge correctly to "0" even if averaged even if the symbol data has random properties. Therefore, even if a signal having a reference level is acquired, an error may occur if the average value does not converge to "0".

The object of the present invention is to detect the error by taking only the synchronous symbol data among the received symbol data, and to evaluate the detected error to perform the coarse gain control when the predetermined range is exceeded. The present invention provides an automatic gain control circuit and method for a digital television receiver capable of fast and precise gain control by performing fine gain control when entering within a predetermined range.

It is another object of the present invention to provide an automatic gain control circuit and method which can simplify the circuit configuration by providing a pulse width modulation of the obtained gain control value to an RF signal and an IF amplification unit.

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In order to achieve the above objects of the present invention, a circuit of the present invention includes an analog-to-digital converter for converting a received data symbol into a corresponding digital value, an absolute value generator for obtaining an absolute value of the converted digital value, and the absolute value. Error detection means for determining an average error value from absolute values corresponding to the field sync symbols and the segment sync symbols among the field sync symbols and the segment sync symbols, and generating corresponding coarse gain control data if the average error value is greater than or equal to a predetermined range, And an error evaluating means for generating fine gain control data controlled in a direction in which the average error value becomes zero, and an output means for outputting a gain control signal corresponding to the coarse or fine gain control data. It is done.

The error detecting means includes: an input selector for selecting the absolute value and the first reference value in response to the recovered field synchronization symbol clock and the segment synchronization symbol clock; and subtracting the first reference value from the absolute value input through the input selector. A subtractor, an accumulator for accumulating each symbol error value of the subtractor, a symbol counter for counting recovered field synchronization symbol segments and a segment synchronization symbol clock, and output data of the accumulator in response to the output of the symbol counter; A divider for outputting an average error value.

The input selector comprises: a first selector for selectively outputting the absolute value and a reference value of the sync symbol in response to a recovered field sync symbol clock and a segment sync symbol clock; and the first selector in response to an enable signal provided from a clock recoverer; An output of the first selector and a second selector for selectively outputting the absolute value.

The circuit includes a third selector for selectively providing a first reference value in the enabled state and a second reference value in the disabled state in response to the enable signal provided from a clock recovery device.

The method of the present invention comprises the steps of converting a received data symbol into a corresponding digital value, obtaining an absolute value of the converted digital value, and corresponding to field sync symbols and segment sync symbols among the absolute values. Determining an average error value from absolute values, and generating corresponding coarse gain control data if the average error value is greater than or equal to a predetermined range, and if the average error value is within a predetermined range, controlling the fine error in a direction in which the average error value becomes zero Generating gain control data and outputting a gain control signal corresponding to coarse or fine gain control data.

The error detection may include selecting the absolute value and the first reference value in response to the recovered field synchronization symbol clock and the segment synchronization symbol clock, subtracting the first reference value from the input absolute value, and subtracting the subtractor. Accumulating the respective symbol error values of C; and counting the recovered field synchronization symbol clock and segment synchronization symbol clock, and dividing the accumulated value in response to a counting value to output an average error value.

The selecting step includes selecting a reference value of the absolute value and the synchronization symbol in response to the recovered field synchronization symbol clock and the segment synchronization symbol clock, and the selected value and the response value in response to an enable signal provided from a clock recovery device. Selecting an absolute value.

The subtraction step selects the first reference value in the enabled state and the second reference value in the disabled state as the subtracted number in response to the enable signal provided from the clock recoverer.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention through an embodiment of the present invention.

1 shows the configuration of a VSB digital television receiver. In Fig. 1, a digital television receiver includes a tuner 10, an intermediate frequency filter and a synchronization detector 12, an NTSC cancellation filter 14, an equalizer 16, a phase tracker 18, a trellis decoder. 20, a data deinterleaver 22, a Reed-Solomon decoder 24, a data derandomizer 26, and a synchronization and timing circuit 28.

The tuner 10 receives a 6 MHz signal (UHF or VHF) from the antenna. It is a high side injection double conversion type with a primary frequency of 920MHz. Image frequency above 1 GHz, fixed front end filter facilitates removal. The first intermediate frequency selection is high enough to prevent the input band pass filter from leaking from the local oscillator (978-1723 MHz) to the tuner front end and interfering with other UHF channels (460-806 MHz). It is low enough for the second harmonics of the UHF channels to fall above. The tuner has a band pass filter that limits the 50-180 MHz frequency range, removing all non-TV signals that fall within the tuner's image frequency range (920 MHz). The first mixer is driven by a synthesized low phase noise local oscillator of at least the first IF. The first local oscillator and the input band pass filter are controlled by a microprocessor. The tuner is capable of tuning all UHF, VHF broadcast bands, standard, IRC and HRC cable bands. At the front of the IF amplifier at 920 MHz, the delay AGC of the primary IF signal is performed. The second mixer is driven by a second local oscillator which is a 876 MHz voltage controlled SAW oscillator. The second local oscillator is controlled by the FPLL sync detector. The 44 MHz second IF signal is applied to the IF amplifier.

The 44 MHz second intermediate frequency signal thus processed is output from the tuner and applied to the intermediate frequency filter and the synchronization detector 12.

Carrier recovery is performed with small pilot carriers by the FPLL circuit. The third local oscillator is a fixed reference oscillator. Frequency drafts or variations are compensated for in the second local oscillator. The control of the second local oscillator is made by the FPLL sync detector. The frequency loop provides a frequency pull-in region of ± 100 kHz, and the phase locking loop has a narrow band of less than 2 kHz. During frequency acquisition, the frequency loop uses in-phase (I) and quadrature phase (Q) pilot signals. The AFC low pass filter works on the bead signal generated by the frequency difference between the VCD and the input pilot. Most high frequency signals are removed from the AFC filter. Only the pilot bit signal remains. The beetle signal is limited to a square wave while passing through the limiter, and multiplied by the quadrature signal to generate an error signal. The polarity of the error signal is determined depending on whether the frequency of the VCO signal is above or below the frequency of the intermediate frequency signal. The error signal is filtered through the APC low pass filter, integrated and output as a DC signal. The DC signal controls the tuner's second local oscillator to reduce the frequency difference. When the frequency difference approaches zero, the APC loop phase locks the input intermediate frequency to the third local oscillation frequency.

Repetitive data segment synchronization is detected between random data synchronously detected by the narrowband filter. From the data segment synchronization, a 10.76 MHz symbol clock is generated with the coherence AGC signal. The 10.76 MHz I-channel composite baseband data signal (synchronization and data) from the synchronous detector is converted into a digital signal through an A / D converter. Data segment sync detectors, including four symbol sync correlators, detect two-level syncs that occur at specific repetition rates.

When data segment sync is detected, a coherent AGC is generated using the measured segment sync amplitude. The amplitude of the sync is determined from the transmitter. Each time synchronization is detected at the receiver, it is compared with a reference value and the difference is integrated. The integrated output controls the tuner's high and medium frequency amplifiers.

2 shows a circuit configuration of an AGC according to a preferred embodiment of the present invention. In FIG. 2, the AGC circuit includes an absolute value generator 50, an error detection unit 60, an error evaluation unit 70, and an output unit 80. 40 is an analog-to-digital converter (hereinafter referred to as ADC) and 40 is a clock recoverer.

The ADC inputs the 10.76 MHz I-channel composite baseband data signal (synchronization and data) shown in Fig. 3 to generate a digital composite I signal.

The 10.76 MHz I-channel composite baseband data signal (synchronization and data) of Fig. 3 represents a frame sync segment. VSB mode consists of 104 unused sequences. The data segment consists of segment synchronization of 4 symbols, data of 828 symbols, and an error correction code.

The clock recoverer 40 detects segment sync and frame sync to generate a segment sync symbol clock SS and a frame sync symbol clock FS, and generates an enable signal EN upon timing recovery.

The absolute value detector 50 takes the absolute value and outputs it because the digital signal output from the ADC has a value between -7 and +7.

The error detector 60 may generate an average error value from absolute values corresponding to frame sync symbols and segment sync symbols among the absolute values in response to the frame sync symbol clock and the segment sync symbol clock provided from the clock recoverer 40. Determine.

The error detector 60 includes a first selector 61, a second selector 62, a third selector 63, a subtractor 64, an adder 65, a delayer 66, a divider 67, and a symbol. And a counter 68.

The first and second selectors 61, 62 constitute an input selector. The first selector 61 selects an absolute value when the segment sync symbol clock and the frame sync symbol clock are applied, and otherwise selects the first reference value (level 5). The second selector 62 selects an absolute value before the clock recovery in response to the enable signal EN of the clock recoverer 40 and selects an output of the first selector 61 after the clock recovery. The third selector 63 selects the second reference value (level 4) before the clock recovery in response to the enable signal EN provided from the clock recoverer 40, and selects the first reference value (level 5) after the clock recovery. Select.

That is, the noncoherent AGC is performed before the clock recovery, and the coherent AGC is selected after the clock recovery.

The subtractor 64 subtracts the absolute value received from the reference value selected by the third selector 63 to generate a difference between the two values. Therefore, if the absolute value (the absolute value of the frame sync symbol and the segment symbol) is 5 when the AGC is performed after the clock recovery, the difference value of the subtractor 64 becomes zero since the first reference value is level 5. If the absolute value is greater than the first reference value, the difference value has a positive value, and if it is small, it has a negative value.

An accumulator consists of an adder 65 and a one symbol clock delay 66 to accumulate each symbol error value provided from the subtractor 64.

The divider 67 divides the accumulated value by inputting the output of the accumulator 66 in parallel and shifting the data inputted from the MSB to the LSB in response to the shift clock. The symbol counter 68 counts the frame sync symbol clock and the segment sync symbol clock to enable the output of the divider every predetermined number of symbols, thereby outputting an average error value.

That is, the error detector 60 detects an average value of the error obtained by comparing the level of the received synchronization symbols with a reference level.

The error evaluator 70 generates corresponding coarse gain control data when the average error value is greater than or equal to a predetermined range, and generates fine gain control data controlled in a direction in which the average error value becomes zero when it is within a predetermined range. .

The error evaluator 70 includes a most significant bit detector 71, an error comparator 72, and an up / down counter 73.

The most significant bit detector 71 inputs the most significant bit representing the sign of the error average value to detect whether the error average value is positive or negative.

Since the error comparator 72 matches the error value corresponding to each gain, the error comparator 72 determines the gain control value of the section corresponding to the detected error average value. When the AGC progresses by the determined gain control value and the detected error average value enters within a specific section, the gain control value at this time is set as the coarse gain control value. Subsequently, AGC is continued with the set gain control value, and fine gain control is performed until the error average value becomes zero.

The up / down counter 73 up / down counts to increase or decrease the gain control value provided from the error comparator 72 by one according to the sign determination of the most significant bit detector.

The output unit 80 includes a pulse width modulator 81 and a low pass filter 82. The pulse width modulator 81 inputs the output of the up / down counter 73 to output a pulse string having a corresponding pulse width. The low pass filter 82 low-pass filters the pulse train provided from the pulse width modulator 81 to generate a DC voltage signal, and the generated DC voltage signal is synchronized with the high frequency amplifier 10a of the tuner 10, the intermediate frequency filter and the synchronization. It is provided as a signal for controlling the gain of the intermediate frequency amplifier 12a of the detector 12.

The output unit 80 facilitates the integrated circuit by allowing the number of output pins to be 1 pin when the AGC circuit is integrated. In this case, the low pass filter 82 is composed of individual elements outside the integrated circuit.

As described above, in the present invention, in the present invention, only the synchronous symbol data is taken out of the received symbol data to detect an error, the detected error is evaluated, and when the predetermined range is exceeded, the coarse gain control is performed, and when entering the predetermined range. Fine gain control enables fast and precise gain control.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (9)

An analog-digital converter for converting received data symbols into corresponding digital values; An absolute value generator for obtaining an absolute value of the converted digital value; Error detection means for determining an average error value from absolute values corresponding to field synchronization symbols and segment synchronization symbols among the absolute values; Error evaluating means for generating corresponding coarse gain control data if the average error value is greater than or equal to a predetermined range, and generating fine gain control data controlled in a direction in which the average error value becomes zero if it is within a predetermined range; And And an output means for outputting a gain control signal corresponding to the coarse or fine gain control data. The method of claim 1, wherein the error detection means An input selector for selecting the absolute value and the first reference value in response to a recovered field synchronization symbol clock and a segment synchronization symbol clock; A subtractor for subtracting the first reference value from an absolute value input through the input selector; An accumulator for accumulating respective symbol error values of the subtractor; A symbol counter for counting recovered field sync symbol clocks and segment sync symbol clocks; And a divider for dividing the output data of the accumulator and outputting an average error value in response to the output of the symbol counter. The method of claim 2, wherein the input selector A first selector for selectively outputting the absolute value and the reference value of the synchronization symbol in response to a recovered field synchronization symbol clock and a segment synchronization symbol clock; And And a second selector for selectively outputting the output of the first selector and the absolute value in response to an enable signal provided from a clock recoverer. 4. The circuit of claim 3, wherein the circuit is And a third selector for selectively providing a first reference value in the enabled state and a second reference value in the disabled state in response to the enable signal provided from the clock recoverer. Automatic gain control circuit. 5. The automatic gain control circuit of claim 4, wherein the receiver is an 8 VSB receiver, wherein the first reference value is (5,0) and the second reference value is (4,0). . Converting the received data symbols into corresponding digital values; Obtaining an absolute value of the converted digital value; Determining an average error value from absolute values corresponding to field sync symbols and segment sync symbols among the absolute values; Generating corresponding coarse gain control data if the average error value is greater than or equal to a predetermined range, and generating fine gain control data controlled in a direction in which the average error value becomes zero if it is within a predetermined range; And And outputting a gain control signal corresponding to the coarse or fine gain control data. The method of claim 6, wherein the error detection step Selecting the absolute value and the first reference value in response to a recovered field synchronization symbol clock and a segment synchronization symbol clock; Subtracting the first reference value from the input absolute value; Accumulating respective symbol error values of the subtractor; And counting the recovered field synchronization symbol clock and the segment synchronization symbol clock and dividing the accumulated value in response to a counting value to output an average error value. 8. The method of claim 7, wherein said selecting step Selecting a reference value of the absolute value and the sync symbol in response to the recovered field synchronization symbol clock and the segment synchronization symbol clock; And And selecting the selected value and the absolute value in response to an enable signal provided from a clock recoverer. The method of claim 8, wherein the subtracting step And a second reference value in the enabled state and a second reference value in the disabled state in response to the enable signal provided from the clock recoverer.