KR20000044016A - Data communication system for detecting and correcting transmit error - Google Patents

Abstract

PURPOSE: A data communication system for detecting and correcting a transmit error, is provided to correct a communication error through a self correction, not to retransmit communication data generated the communication error. CONSTITUTION: A data communication system for detecting and correcting a transmit error, comprises a data transmitting circuit(100) and a data receiving circuit(200). The data transmitting circuit(100) generates a n bit of check data group satisfied with second order - 1referring to a N bit of transmit data inputted from a user processor. The data transmitting circuit(100) responds a proper subset of the check data group to each bit of the transmit data. The data transmitting circuit(100) selects a transmit data bit responded to a same check data bit, operates the selected bit logically, to generate a first check data, transmitting the generated data with the transmit data. The data receiving circuit(200) executes a same operation logic as the first check data referring to a N bit of transmit data of the transmit data transmitted from the data transmitting circuit(100), to generate a second check data. The data receiving circuit(200) selects a check data bit which is not consisted between the first and second check data, and detects a transmit data bit responded properly to the selected check data bit, as a transmit error bit. The data receiving circuit(200) obtains a complement to a binary value of the detected transmit error bit, to correct an error.

Description

Data communication system and error correction method that can detect and correct transmission error.

The present invention relates to an information communication system for transmitting and receiving data. In particular, the present invention relates to a data communication system capable of detecting and correctly correcting transmission errors occurring during data transmission and reception.

In general, in the data transmission system, an error occurs in the transmission data itself or in the transmission process, and thus, the reliability of the transmission data is often decreased. In this case, conventionally, a parity bit checking method for determining whether an error has occurred during transmission by examining the number of "1" s included in the transmission data sent from the transmitter in order to investigate an error that may occur during transmission of data. Was used.

An example of the conventional parity bit check method will be described with reference to FIGS. 1 and 2 as follows. 1 shows a conventional parity bit check circuit for detecting an error in transmission data, and FIG. 2 shows parity bits when odd parity is set in the parity bit check circuit of FIG. .

Parity bits have even parity and odd parity, and even parity is a method of determining parity bits such that the number of "1s" included in one data code is even. In parity bits, parity bits have an odd number of "1" s. How to determine.

Referring to FIG. 2, when the odd parity method is used, when there are an odd number of "1" s in the data bits D1-D8, the parity bit P is "0" and "1" is in the data bits D1-D8. If there is an even number, it can be seen that the parity bit P becomes "1". Referring to FIG. 1, a method of detecting a data transmission error by applying the odd parity bit method is described. Referring to FIG. 1, the data bits D1 through D8 and the parity bits P may include a plurality of EXOR gates. Q, the final value outputted by, should always be "1" in normal case. Therefore, if Q is " 0 ", it indicates that an error occurred during data transmission.

Such a conventional parity bit check method only knows whether an error has occurred during data transmission, but has a problem in that the error is correctly detected and cannot be corrected correctly.

That is, the conventional parity bit check method is difficult to apply to a system requiring high reliability and accuracy because the parity bit check detects an error and stops the data transmission and requests retransmission of the data. Do.

Accordingly, the present invention was devised to solve the above problems of the prior art, and an object of the present invention is to accurately detect a transmission error occurring during data transmission.

Another object of the present invention is to provide a communication system capable of correcting a transmission error correctly through a simple logical operation.

It is another object of the present invention to provide a method for correcting a transmission error that can be applied to a data communication system requiring high reliability and accuracy.

The communication system of the present invention for achieving the above object satisfies 2 ⁿ -1 ≥ N for N-bit transmission data (m ₀ , m ₁ , m ₂ ,... M _N ) input from a user processor. Generate n-bit check data set ({c ₀ , c ₁ , ... c _n }) and generate a true subset of this n-bit check data set {{c ₀ }, {c ₁ } ... {C _n }, {c ₀ , c ₁ },..., And {c _n-1 , c _n }... A data transmission circuit for generating first check data by selecting and performing logical operation on only a corresponding transmission data bit and transmitting the first check data together with the transmission data; The second check data by with respect to the data transmission circuit of the transmission data of the N-bit transmission data transmitted from the _{(m 0, m 1, m} 2, and and and and m _N) perform the same logical operation with the first check data, By generating (c ' ₀ , c' ₁ ,... c ' _n ) and comparing them with the first check data, only check data bits that do not coincide with each other are selected, and only the selected check data bits are unique. And a data receiving circuit for detecting a corresponding transmission data bit as a transmission error bit and correcting an error by taking a complement of the binary value of the transmission error bit.

The data transmission circuit includes a check data generation unit for generating the first check data, a data synthesizing unit for synthesizing transmission data by adding n bits of first check data to the N bits of transmission data, and the transmission data. It includes a transmitter for transmitting to the data receiving circuit through the transmission medium.

The data receiving circuit further includes a receiver for receiving transmission data transmitted from the data transmission circuit, and data separation for separating the received data from the receiver into N bits of transmission data and n bits of first check data. And a reception side check data generation unit for generating second check data from the N-bit transmission data, a comparison unit for comparing the first check data and the second check data, and a transmission error from the result of the comparison unit. And an error detector for detecting a bit, and an error correction unit for correcting a transmission error by replacing the binary value of the transmission error bit with its complement.

Further, transmission error correction method for achieving the object of the present invention is N bits from the transmission data 2 ⁿ - 1 ≥ ^N check data set of n bits that satisfy the ({c _0, c _1, and and and and c _n }), And the true subset except for the empty set of the n-bit check data set {{c ₀ }, {c ₁ }, ... {c _n }, {c ₀ , c ₁ }, ... • Exclusive-OR operation by matching {c _n-1 , c _n } ···· to each bit of transmission data and selecting only transmission data bits corresponding to the same check data bit. Generating first check data by performing; Transmitting the n-bit first check data to the transmission data and transmitting the same through the transmission medium; Generating n-bit second check data from the received N-bit transmission data in the same manner as in step (a); The check data bits (c _n ≠ c ' _n ) which are not identical to each other are compared by comparing the first check data of the received n bits with the second check data, and the transmission data bits uniquely corresponding to the check data bits are selected. A transmission error detection step of detecting a transmission error bit; And a transmission error correction step of correcting the transmission error by replacing the binary value of the transmission error bit detected in the transmission error detection step with its complement.

The second check data generating step includes: a data receiving step of receiving N + n bit transmission data (transmission data + first check data) through a transmission medium; A data separation step of separating the received N + n-bit transmission data into N-bit transmission data and n-bit first check data; And a check data generation step of generating second check data from the separated N bits of transmission data.

Other objects and advantages of the invention will be described below and will be appreciated by the practice of the invention. Furthermore, the objects and advantages of the invention can be realized in particular by the means and combinations indicated in the appended claims.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention and, together with the foregoing general description and the detailed description of the following preferred embodiments, serve to explain the principles of the invention. .

1 illustrates a conventional parity bit check circuit for detecting an error of transmission data.

FIG. 2 shows parity bits when odd parity is set in the parity bit check circuit of FIG.

Figure 3 shows a block diagram of a data communication system of the present invention.

FIG. 4 shows a detailed block diagram of the transmission data generation circuit applied to FIG.

5 is a flowchart illustrating a process of generating transmission data consisting of transmission data and first check data.

FIG. 6 is a detailed block diagram of a transmission error correction circuit applied to FIG. 3.

7 is a flowchart illustrating a process of detecting and correcting a transmission error performed in the transmission error correction circuit.

<Explanation of symbols for the main parts of the drawings>

100: data transmission circuit 200: data receiving circuit

300: transmission medium 110: transmitting user processor

250: receiving user processor 130: transmitting data generating circuit

230: transmission error correction circuit 150: transmitter

210: receiver

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, it should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to obscure the subject matter of the present invention.

Figure 3 shows a block diagram of a data communication system of the present invention.

As shown in FIG. 3, the data communication system of the present invention includes a data transmission circuit 100 for transmitting transmission data, a data receiving circuit 200 for receiving the transmitted transmission data, the data transmission circuit, and data reception. It consists of a transmission medium 300 which is a physical passage connecting the circuits.

The transmission medium 300 includes a wired medium such as a double helix or a coaxial cable that is guided to an intended place along a physical path in which the electromagnetic signal is artificially closed, or a wireless medium in which the electromagnetic signal is not intentionally induced.

The data transmission circuit 100 includes a transmission user processor 110 for generating transmission data and transmission data generation circuit 130 for adding transmission data to be transmitted to the reception side by adding check data, which will be described later, to the transmission data. And a transmitter 150 for transmitting the transmission data through the transmission medium.

Hereinafter, the transmission data generation circuit 130 applied to the data transmission circuit 100 will be described in detail with reference to FIGS. 4 and 5.

As shown in FIG. 4, the transmission data generating circuit 130 of the present invention includes a check data generating unit 131 and a data synthesizing unit 132.

Transmission data input from the user processor 110 is input to an input terminal of the check data generator 131. The transmission data refers to data containing information that a transmitting user wants to convey to a receiving user.

The check data generation unit 131 generates check data to be described later from the transmission data. This check data includes information for use when the receiving side detects and corrects a transmission error.

The number of bits and the bit value of the check data are determined based on the transmission data.

If the transmission data input from the user processor is composed of N bits, the number of bits of the check data is determined by Equation (1) below.

2 ⁿ -1 ≥ N (1)

That is, the number of bits of the check data is determined as an integer n that satisfies the above expression (1).

When the number of bits of the check data is determined, the check data generation section obtains a subset of the set consisting of these check data bits. In this case, the empty set is excluded from the subset. For example, if the transmission data consists of 8 bits (Mo, M1, M2, M3, M4, M5, M6, M7) and the number of bits of the check data is 4 bits, the set of check data bits is C = {Co, C1, C2, C3}, and a subset of this C subset is {Co}. {C1}, {C2}, {C3}, {Co, C1}, {Co, C2}, {Co, C3}, {C1, C2}, {C1, C3}, {C2, C3}, {Co , C1, C2}, {Co, C1, C3}, {Co, C2, C3}, {C1, C2, C3}, {Co, C1, C2, C3}.

When the subset consisting of the check data bits is determined, the subsets corresponding to the number of bits of the transmitted data in the 15 subsets are arbitrarily selected so as not to overlap, and each selected subset is arbitrarily associated with the transmitted data bits.

For example, Mo ⇔ {C3}, M1 ⇔ {Co, C1}, M2 ⇔ {Co}, M3 ⇔ {C2}, M4 ⇔ {C1}, M5 ⇔ {C2, C3}, M6 ⇔ {Co, C2 }, M7 대응 matches {C1, C3}.

Only the transmission data bits corresponding to the same check data bit among the transmission data bits corresponding to the subset of the check data bits are selected. For example, the transmission data bits corresponding to the check data bits C1 are M1, M4 and M7.

The selected transmission data bits M1, M4, and M7 are logically operated to correspond to the corresponding check data bits. That is, C1 = M1 M4 Perform M7. here, Is a symbol representing an exclusive-OR operation. The logical operation performed by the check data generation unit is not necessarily limited to the exclusive or operation, and of course, other logical operations may be adopted.

Obtaining the check data bit through the above process is as follows.

CO = M1 M2 M6

C1 = M1 M4 M7

C2 = M3 M5 M6

C3 = MO M5 M7

As such, when generation of check data is completed, the check data generation unit 131 applies the generated check data to the data synthesizing unit 132. Transmission data input from the user processor 110 is applied to the other input terminal of the data synthesizing unit 132.

The data synthesizing unit 132 synthesizes N + n bits of transmission data from N bits of transmission data and n bits of check data and applies the same to the transmitter.

When the transmission data is applied, the transmitter 150 transmits it to the data receiving circuit 200 through the transmission medium 300.

As shown in FIG. 3, the data receiving circuit 200 of the present invention includes a receiver 210, a transmission error correction circuit 230, and a receiving user processor 250.

The receiver 210 receives and transmits the transmission data transmitted through the transmission medium 300 to the transmission error correction circuit 230.

The transmission error correction circuit 230 receives transmission data from the receiver 210 and detects a transmission error occurring in the transmission process, and corrects the transmission error when a transmission error is detected.

Hereinafter, the transmission error correction circuit 230 of the present invention will be described in detail with reference to FIGS. 6 and 7.

As shown in FIG. 5, the transmission error correction circuit 230 of the present invention includes a data separator 231, a check data generator 232, a comparator 233, an error detector 234, and an error. The correction unit 235 is included.

The data separator 231 separates the received data of N + n bits into N bits of transmission data and n bits of transmission side check data. The separated N bits of transmission data are applied to the check data generation unit 232, and the remaining n bits of transmission data of the n bits are applied to the comparison unit 233.

The transmission data of N bits applied to the check data generation unit 232 generates the check side check data through the same process as that of the check data generation unit 130 of the transmission circuit 100 described above.

For example, transmission data M'o, M'1, M'2, M'3, M'4, M'5, M'6, and M'7 among the received data received through the receiver 210. Is 8 bits and the transmitter check data is 4 bits, the check data generator 230 generates 4 bits of receiver check data C'o, C'1, C'2, and C'3.

The receiving check data is determined by the logical operation of the transmission data bits as follows.

C'O = M'1 M'2 M'6

C'1 = M'1 M'4 M'7

C'2 = M'3 M'5 M'6

C'3 = M'O M'5 M'7

The reception check data thus determined is input to the comparison unit 233 and compared with the transmission check data. The comparison unit 233 compares the transmission check data and the reception check data inputted from the input terminal, and outputs mismatched reception check data to the error detection unit 234.

For example, when C'O = CO, C'1 = C1, C'2? C2, and C'3 = C'3, C'2 is output to the error detector 234.

The error detector 234 selects the transmission data bits uniquely corresponding to the input check side check data bits and detects them as transmission error bits. For example, in this case, the transmission data bit uniquely corresponding to C'2 is M'3.

Accordingly, the error detector 234 detects M'3 as a transmission error bit and applies it to the error correction unit 235.

When the transmission error bit is input from the error detection unit 234, the error correction unit 235 replaces the binary value of the transmission data bit corresponding to the transmission error bit among the transmission data applied from the data separation unit 231 to its complementary value. To the user processor 250. For example, in the above example, the error correction unit 235 transmits the data of the error corrected to the user processor 250 (M'o, M'1, M'2, M'3, M'4, M'5). , M'6, M'7). Here, M'3 represents a complement of M'3.

If there is no check data that does not match each other as a result of comparing the check side check data and the check side check data from the comparison unit 233, the error detection unit 234 does not output a transmission error bit because no transmission error occurred. The error correction unit 235 transfers the transmission data applied from the data separation unit 231 to the user processor 250 as it is.

A method of correcting a transmission error using the communication system of the present invention having the above-described configuration will now be described with reference to FIGS. 5 and 7.

The transmitting user processor 110 applies 8-bit transmission data as shown in Table 1 to the check data generating unit 131 of the transmission data generating circuit 130.

beat Mo M1 M2 M3 M4 M5 M6 M7 Binary value One 0 0 One 0 One 0 0

If 8-bit transmission data is applied, the check data generation unit obtains a 4-bit check data set [C = {Co, C1, C2, C3}] that satisfies 2 ^4-1 ? 8 (step S11).

Eight subsets corresponding to the number of bits of the transmission data of the 15 subsets of the set C are arbitrarily selected and correspond to each bit of the transmission data.

For example, Mo ⇔ {CO}, M1 ⇔ {C1}, M2 ⇔ {C2}, M3 ⇔ {C3}, M4 ⇔ {CO, C1}, M5 ⇔ {CO, C2}, M6 ⇔ {Co, C3 }, M7 대응 matches {C1, C2}. (Step S12)

Only the transmission data bits corresponding to the same check data bits are selected from the correspondence in step S12, and the first check data (transmission side check data) of 4 bits is generated by performing an exclusive-OR operation. (Step S13)

CO = Mo M4 M5 M6 = 0

C1 = M1 M4 M7 = 1

C2 = M2 M5 M7 = 1

C3 = M3 M6 = 1

12 bits of transmission data (Mo to M7, Co to C3) obtained by combining the first check data bit obtained in step S13 with the transmission data bit are transmitted through the transmission medium. (Step S14)

12 bits of received data received through the transmission medium are divided into 8 bits of transmission data and 4 bits of first check data as shown in Table 2 (Step S21).

beat M'o M'1 M'2 M'3 M'4 M'5 M'6 M'7 Binary value One 0 One One 0 One 0 0

By performing the same logical operation as the above steps S11 to S13 on the 8-bit transmitted data separated in step S21, the second check data of the following four bits is generated. (Step S22)

C'O = M'o M'4 M'5 M'6 = 0

C'1 = M'1 M'4 M'7 = 1

C'2 = M'2 M'5 M'7 = 0

C'3 = M'3 M'6 = 1

The first check data separated in step S21 and the second check data generated in step S22 are compared to select only check data bits that do not coincide with each other. (Step S23)

Since C'O = CO, C'1 = C1, C'2 ≠ C2, and C'3 = C'3, the check data bits that do not coincide with each other are C'2 ≠ C2.

The transmission data bit uniquely corresponding to the selected check data bit C'2 is detected as the transmission error bit. (Step S24)

In the above, the transmission data bit uniquely corresponding to C'2 is M'2, and thus the transmission error bit is M'2 = 1.

The error is corrected by taking the complement of the binary value of the transmission error bit detected in step S24. That is, the transmission error is corrected by taking M'2 = 0, which is a complement of M'2 = 1. (Step S25)

The circuit configuration shown in the accompanying drawings is an example, and other configurations may be adopted as long as the same function can be realized. The operation flow can also be arbitrarily changed.

In addition, the present invention is not limited to the above-described embodiment, and various modifications within the equivalent scope of the technical spirit of the present invention and the claims to be described below by those skilled in the art to which the present invention pertains. Of course, variations are possible.

As described above, the communication system of the present invention can secure the accuracy and reliability of the data communication by correcting the error through self-calibration without retransmitting the communication data when an error occurs.

Claims (6)

(1) ⁿ -bit check data set satisfying 2 ⁿ -1 ≥ N with respect to N bits of transmission data (m ₀ , m ₁ , m ₂ ,... M _N ) input from the user processor ({c _0, c _1, and and and and c _n}) to generate, and the n set of binary portion of the check data set of bits _{{{c 0}, {c} 1} and and and and {c _n}, {c ₀ , c ₁ },..., c _n-1 , c _n } ···} for each bit of the transmission data, and logically select only the transmission data bits corresponding to the same check data bit. A data transmission circuit for generating first check data and transmitting the first check data together with the transmission data; (2) performing the same logical operation as the first check data on N bits of transmission data (m ₀ , m ₁ , m ₂ ,... M _N ) of the transmission data transmitted from the data transmission circuit. 2 generate check data c ' ₀ , c' ₁ ,... C ' _n , and compare them with the first check data to select only check data bits that do not coincide with each other, And a data receiving circuit which detects a transmission data bit uniquely corresponding to the transmission error bit, and corrects an error by taking a complement of the binary value of the transmission error bit. Data communication system. The method of claim 1, The data transmission circuit (a) a check data generation unit for generating the first check data; (b) a data synthesizing unit for synthesizing transmission data by adding n bits of first check data to the N bits of transmission data; (c) a data communication system capable of detecting and correcting a transmission error, comprising a transmitter for transmitting the transmission data to a data receiving circuit through a transmission medium. The method of claim 1, The data receiving circuit (a) a receiver for receiving transmission data transmitted from said data transmission circuit; (b) a data separator for separating the received data from the receiver into N-bit transmission data and n-bit first check data; (c) a reception side check data generation unit for generating second check data from the N-bit transmission data; a comparison unit for comparing the first check data with the second check data; (e) an error detection unit for detecting a transmission error bit from the result of the comparison unit; and (f) error correction for correcting the transmission error by replacing the binary value of the transmission error bit with its complement. The method of claim 2 or 3, And a logical operation for generating the first check data and the second check data is an exclusive-OR operation. (a) n-bit check data sets ({c ₀ , c ₁ , ... c _n }) satisfying 2 ⁿ -1 ≥ N are generated from the N-bit transmission data, and the n-bit check data is generated. set of binary excluding empty part of the set _{{{c 0}, {c} 1} and and and and _{{c n}, {c 0} , c 1}, and and and and and _{{c n-1, c n} } and Generating first check data by corresponding to each bit of transmission data, selecting only transmission data bits corresponding to the same check data bits, and performing an exclusive-OR operation; ; (b) adding the n-bit first check data to the transmission data and transmitting the same through the transmission medium; (c) generating n-bit second check data from the received N-bit transmission data through the same process as in step (a) above; (d) comparing the first check data of the received n bits with the second check data, and selecting the check data bits (c _n ≠ c ' _n ) that do not coincide with each other and transmitting uniquely corresponding only to the check data bits. A transmission error detection step of detecting data bits as transmission error bits; and (e) a transmission error correction step of correcting the transmission error by replacing the binary value of the transmission error bit detected in the transmission error detection step with its complement. The method of claim 5, wherein the second check data generating step (f) a data receiving step of receiving N + n bits of transmission data (transmission data + first check data) through a transmission medium; (g) a data separation step of separating the received N + n-bit transmission data into N-bit transmission data and n-bit first check data; (h) a check data generation step of generating second check data from the separated N-bit transmission data.