KR20000043206A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20000043206A
KR20000043206A KR1019980059556A KR19980059556A KR20000043206A KR 20000043206 A KR20000043206 A KR 20000043206A KR 1019980059556 A KR1019980059556 A KR 1019980059556A KR 19980059556 A KR19980059556 A KR 19980059556A KR 20000043206 A KR20000043206 A KR 20000043206A
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South Korea
Prior art keywords
gmos
lvtgmos
well
pad
stack structure
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KR1019980059556A
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Korean (ko)
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황윤택
김현곤
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김영환
현대전자산업 주식회사
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Priority to KR1019980059556A priority Critical patent/KR20000043206A/en
Publication of KR20000043206A publication Critical patent/KR20000043206A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02425—Conductive materials, e.g. metallic silicides

Abstract

PURPOSE: A semiconductor device is provided to improve an electrostatic discharge(ESD) characteristic and reliability of a product, by preventing over current at a drain of a GMOS, caused by a parasitic bipolar transistor, between a GMOS and an LVTGMOS as well as between a drain region of the GMOS and a well pick-up, and by forming a current path to an NPN filed transistor. CONSTITUTION: A semiconductor device having a separate current path between a series stack structure connected by a GMOS and an LVTGMOS, and a pad, comprises a P-well, a first isolation layer, a P-well pick-up, a second isolation layer, an N-well pick-up, an N-well guarding, a series stack structure and a separate current path. The P-well is formed on a semiconductor substrate. The first isolation layer of an island shape is formed by the separated GMOS and LVTGMOS. The P-well pick-up is established in the lateral of the island-shaped isolation layer. The second isolation layer is established in the lateral of the P-well pick-up. The N-well guard ring is formed in the lateral of the second isolation layer. The series stack structure is connected to the GMOS and the LVTGMOS by a pad coupled to the drain region of the GMOS. The separate current path is formed between the pad and the GMOS and LVTGMOS, by having two NPN field transistors between the pad and the GMOS and LVTGMOS.

Description

반도체소자Semiconductor device

본 발명은 정전기 방전 ( electro static discharge, 이하 ESD 라 함 ) 보호 회로가 구비되는 반도체소자에 관한 것으로, 특히 ESD 재핑 ( zapping ) 시 갑자기 많은 전류가 인가되어서 집적회로의 내부회로에 손상을 주는 것을 막기 위하여, ESD 보호회로에서 들어온 전하들을 효과적으로 클램핑 ( clammping ) 하여 ESD 특성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with an electrostatic discharge (ESD) protection circuit, and in particular, to prevent damage to an internal circuit of an integrated circuit by suddenly applying a large amount of current during ESD zapping. To this end, the present invention relates to a technique capable of effectively clamping charges introduced from an ESD protection circuit to improve ESD characteristics.

일반적인 MOS 회로는 내부적으로 2.5 ∼ 5 볼트 내외의 전압으로 동작하게 설계되어 있다. 그러나, 그들은 여러 원인등으로 인해 그 이상의 높은 전압에 노출된 경우가 발생하게 되는데, 이러한 상황에서는 MOS 소자의 게이트산화막 파괴 현상, 접합 스파이크 ( junction spiking ) 현상등이 발생되어 소자가 완전히 파괴되거나 혹은 미세하게 손상을 받아 누설전류의 발생으로 신뢰성에 심각한 영향을 주게 된다.Typical MOS circuits are designed to operate internally at voltages of around 2.5 to 5 volts. However, they may be exposed to higher voltages due to various causes, such as gate oxide breakdown of the MOS device, junction spiking, or the like, and the device is completely destroyed or fine. This damage is seriously affected by the leakage current.

상기한 바와같이 높은 전압에 대한 반도체소자의 노출은 여러가지 원인이 있을 수가 있는데 그 중 대표적인 것이 우리가 소자를 손으로 다룰때 사람몸에서 발생되는 정전기가 소자로 흘러 들어가는 경우다. 일반적으로 사람몸에서는 2000 ∼ 수만 볼트의 정전기 전압이 발생한다.As described above, the exposure of a semiconductor device to high voltages can have various causes. One of them is a case in which static electricity generated in the human body flows into the device when we handle the device by hand. In general, the human body generates an electrostatic voltage of 2000 to tens of thousands of volts.

한편, 또 한가지는 반도체소자를 어떠한 장비나 소켓 ( socket ) 등에 꽂을때 그 장비의 접지상태가 불안정하면 순간적으로 전하가 핀을 타고 소자로 흘러 들어가게 될 것이다.On the other hand, when the semiconductor device is plugged into any equipment or socket, if the grounding state of the equipment is unstable, electric charge will flow to the device through the pin.

위에서 서술한 바와같이 사용자가 주의하지 않으면 반도체소자는 언제든지 정전기 등과 같은 유익하지 않은 고전압에 항상 노출될 위험성이 있다.As described above, if the user is not careful, the semiconductor device is always exposed to unfavorable high voltage such as static electricity.

이러한 정전기 피해를 막기 위하여 핸들링 ( handling ) 할때 안티-스테틱 튜브 ( anti-static tube ) 를 사용하거나 접지 밴드를 착용한채 핸들링하는 등 최소한의 예방을 할 수 있으나, 궁극적으로는 정전기 방지용 회로를 회로의 입력단 ( 게이트단) 에 앞서 구성하여야 한다.In order to prevent such static damage, it is possible to minimize the handling such as using anti-static tube or handling with grounding band when handling. It must be configured before the input terminal (gate stage) of.

최근들어, 반도체소자는 소자의 고집적화에 따라 두께가 점점 더 얇아져 보다 높은 ESD 내성을 필요로 하고 정전기 방전에 의한 영향을 더욱 더 심하게 받는다.In recent years, semiconductor devices have become thinner and thinner with higher integration, which requires higher ESD resistance and is more severely affected by electrostatic discharge.

그리고, 상기 ESD 는 메모리소자의 셀부에 비하여 훨씬 큰 디자인룰에 의하여 디자인되어 그에 따른 반도체소자의 고집적화를 더욱 어렵게 한다.In addition, the ESD is designed by a much larger design rule than the cell portion of the memory device, thereby making it more difficult to integrate the semiconductor device.

도 1 및 도 2 는 종래기술에 따른 반도체소자를 도시한 것으로, 도 1 은 GMOS 와 VLTGMOS 가 직렬로 연결된 시리즈 스택 ( series stack ) 구조의 ESD 방전 보호 회로도이고, 도 2 는 상기 도 1 의 레이아웃도이다.1 and 2 illustrate a semiconductor device according to the prior art, FIG. 1 is an ESD discharge protection circuit diagram of a series stack structure in which GMOS and VLTGMOS are connected in series, and FIG. 2 is a layout diagram of FIG. to be.

상기 도 2 는 GMOS (200)드레인과 LVTGMOS (300)로 연결된 시리즈 스택 구조의 ESD 보호회로의 레이아웃을 도시한 것으로서, 폐곡선 형태로 일정범위를 갖는 엔웰 가아드링(25)이 구비되고, 상기 엔웰 가아드링(25)의 내측으로 제2소자분리막(23), 피웰 픽업(21), 제1소자분리막(13)의 순서로 각각 구비되고, 상기 제1소자분리막(13) 영역 내에 GMOS(200)와 LVTGMOS(300)이 각각 구비되고, 상기 엔웰 가아드링(25) 내측에 포함된 부분과 상관없이 패드(100)가 구비된다. (도 2)FIG. 2 illustrates a layout of an ESD protection circuit having a series stack structure connected by a drain of the GMOS 200 and the LVTGMOS 300, and includes an enwell guard ring 25 having a predetermined range in a closed curve shape. The second device isolation layer 23, the pewell pick-up 21, and the first device isolation layer 13 are provided in the order of the inside of the dring 25, respectively, and the GMOS 200 and the GMOS 200 may be disposed in the region of the first device isolation layer 13. LVTGMOS (300) is provided respectively, the pad 100 is provided irrespective of the portion contained inside the enwell guard ring (25). (Figure 2)

이상에서 설명한 바와같이 종래기술에 따라 ESD 보호회로가 구비되는 반도체소자는, ESD 재핑시 GMOS 의 드레인영역에 과전류가 흐르게 되어 반도체소자의 ESD 레벨를 낮추고 그에 따른 반도체소자의 특성 및 신뢰성을 저하시킬 수 있는 문제점이 있다.As described above, in the semiconductor device having the ESD protection circuit according to the related art, an overcurrent flows in the drain region of the GMOS during the ESD zapping, thereby lowering the ESD level of the semiconductor device and thus degrading the characteristics and reliability of the semiconductor device. There is a problem.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, GMOS 와 LVTGMOS 가 직렬로 연결된 스택구조에 NPN 필드 트랜지스터를 추가하되, Vcc 를 강화하기 위하여 2개의 소오스 노드에 각각 Vss 와 Vcc 에 연결하고, GMOS 와 LVTGMOS 사이와 GMOS 드레인영역과 웰 픽업 사이에서의 기생 바이폴라 트랜지스터에 의한 GMOS 드레인에서의 과도전루를 막아주고, NPN 필드 트랜지스터로 전류통로를 만들어 줌으로써 ESD 특성을 강화시키고 제품의 신뢰성을 향상시키는 정전기 방전 보호 회로가 구비되는 반도체소자를 제공하는데 그 목적이 있다.In order to solve the above-mentioned problems of the prior art, the NPN field transistor is added to a stack structure in which GMOS and LVTGMOS are connected in series. However, in order to enhance Vcc, the present invention connects two source nodes to Vss and Vcc, respectively, and GMOS. Electrostatic discharge that enhances ESD characteristics and improves product reliability by preventing overcurrent in GMOS drain by parasitic bipolar transistor between LVTGMOS and GMOS drain region and well pick-up and making current path through NPN field transistor It is an object of the present invention to provide a semiconductor device provided with a protection circuit.

도 1 은 종래기술에 따른 정전기 방전 보호 회로를 도시한 회로도.1 is a circuit diagram showing a static discharge protection circuit according to the prior art.

도 2 는 도 1 에 따른 정전기 방전 보호회로를 도시한 레이아웃도.2 is a layout showing the electrostatic discharge protection circuit according to FIG.

도 3 은 본 발명에 따른 정전기 방전 보호 회로를 도시한 회로도.3 is a circuit diagram showing an electrostatic discharge protection circuit according to the present invention.

도 4 는 도 3 에 따른 정전기 방전 보호 회로를 도시한 레이아웃도.4 is a layout showing the electrostatic discharge protection circuit according to FIG.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

21,31,31' : 제1소자분리막 23,33,33' : 피웰 픽업 ( p-well pick-up )21,31,31 ': First element isolation membrane 23,33,33': P-well pick-up

25,35,35' : 제2소자분리막25,35,35 ': Second Device Separator

27,37,37' : 엔웰 가아드링 ( n-type guardring )27,37,37 ': n-type guardring

39 : NPN 필드 트랜지스터의 드레인39: drain of NPN field transistor

41 : NPN 필드 트랜지스터의 소오스 ( Vcc 또는 Vss )41: source of the NPN field transistor (Vcc or Vss)

43 : NPN 필드 트랜지스터의 소오스 ( Vss 또는 Vcc )43: Source (NP, Vcc) of NPN field transistor

100,400 : 패드 200,500 : GMOS100,400: Pad 200,500: GMOS

300,600 : LVTGMOS300,600: LVTGMOS

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자는,In order to achieve the above object, a semiconductor device according to the present invention,

GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와 패드 사이에 별도의 전류통로가 구비되는 반도체소자에 있어서,A semiconductor device having a separate current path between a pad and a series stack structure connected by GMOS and LVTGMOS,

반도체기판 상에 구비되는 피웰과,Pwell provided on the semiconductor substrate,

상기 GMOS 와 LVTGMOS 가 이격되어 형성된 섬형태의 제1소자분리막과,An island-shaped first device isolation layer formed by separating the GMOS and LVTGMOS;

상기 섬형태의 소자분리막의 외측에 구비되는 피웰 픽업과,A pewell pick-up provided outside the island-type device isolation film;

상기 피웰 픽업의 외측에 구비되는 제2소자분리막과,A second device isolation film provided outside the pewell pickup;

상기 다른 소자분리막의 외측에 구비되는 엔웰 가아드링과,An enwell guard ring provided at an outer side of the other device isolation film;

상기 GMOS 드레인 영역에 접속되는 패드로 구비되는 GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와,A series stack structure connected with a GMOS and an LVTGMOS provided by a pad connected to the GMOS drain region;

상기 패드와 GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조 사이에 두개의 필드 트랜지스터가 구비되되, 상기 두개의 필드 트랜지스터의 드레인을 통하여 연결되고, 상기 두개의 필드 트랜지스터의 소오스에 각각 구비되는 Vcc, Vss 가 연결되어 상기 패드와 GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조 사이에 별도의 전류통로가 포함되는 것과,Two field transistors are provided between the pad and a series stack structure connected by GMOS and LVTGMOS, and are connected through the drains of the two field transistors, and Vcc and Vss respectively provided in the source of the two field transistors are connected to each other. A separate current path is included between the pad and the series stack structure connected by GMOS and LVTGMOS,

상기 GMOS 와 LVTGMOS 는 10 ∼ 30 ㎛ 의 거리가 유지되는 것과,The GMOS and LVTGMOS is maintained at a distance of 10 to 30 ㎛,

상기 GMOS 드레인과 웰 픽업은 10 ∼ 30 ㎛ 의 거리가 유지되는 것과,The GMOS drain and the well pickup is maintained at a distance of 10 to 30 ㎛,

상기 필드 트랜지스터의 드레인영역과 가아드링은 10 ∼ 30 ㎛ 의 거리가 유지되는 것과,The drain region and the guard ring of the field transistor are maintained at a distance of 10 to 30 µm,

상기 두개의 필드 트랜지스터의 소오스는 각각 Vss, Vcc 에 연결되는 것과,The sources of the two field transistors are connected to Vss and Vcc respectively,

상기 두개의 NPN 필드 트랜지스터의 드레인영역에 피웰 대신 엔웰이 구비되는 것과,An enwell is provided in the drain regions of the two NPN field transistors instead of the pewell;

상기 NPN 필드 트랜지스터의 드레인 부분에 폴리실리콘이나 실리사이드로 버퍼층이 구비되는 것을 특징으로 한다.A drain layer of the NPN field transistor may be provided with a buffer layer made of polysilicon or silicide.

한편, 이상의 목적을 달성하기 위한 본 발명의 원리는,On the other hand, the principle of the present invention for achieving the above object,

GMOS 와 LVTGMOS 사이와, GMOS 드레인영역과 웰 픽업 사이에서의 기생 바이폴라 트랜지스터에 의한 GMOS 드레인에서의 과도전류를 막아주기 위하여, 상기 GMOS 와 LVTGMOS 사이와, GMOS 드레인영역과 웰 픽업 사이의 거리를 10 ∼ 30 ㎛ 정도로 유지하고,In order to prevent transient currents in the GMOS drain between the GMOS and the LVTGMOS and between the GMOS drain region and the well pickup by the parasitic bipolar transistor, the distance between the GMOS and the LVTGMOS and between the GMOS drain region and the well pick-up is 10 to 10%. Kept at about 30 μm,

상기 GMOS 와 LVTGMOS 의 시리즈 스택 구조와 패드 사이에 두개의 NPN 필드 드랜지스터가 구비되되, 이들의 소오스에 각각 Vcc, Vss 또는 Vss, Vcc 를 연결하여 전류통로를 만듬으로써 ESD 특성을 향상시키는 것이다.Two NPN field transistors are provided between the series stack structure and pads of the GMOS and LVTGMOS, and Vcc, Vss, or Vss and Vcc are connected to their sources, respectively, to improve the ESD characteristics.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3 및 도 4 는 본 발명에 실시예에 따라 정전기 방전 보호회로가 구비되는 반도체소자의 회로도 및 레이아웃도이다.3 and 4 are a circuit diagram and a layout diagram of a semiconductor device provided with an electrostatic discharge protection circuit according to an embodiment of the present invention.

상기 도 3 은, GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와 두개의 NPN 필드 트랜지스터로 구성된 ESD 보호 회로도로서, 상기 두개의 NPN 필드 트랜지스터의 드레인 노드에 패드가 접지되고, 상기 두개의 NPN 필드 트랜지스터의 소오스 노드에 각각 Vcc, Vss 가 연결되거나 Vss, Vcc 가 연결되어 Vcc 가 강화된 것이다.3 is an ESD protection circuit diagram comprising a series stack structure connected by a GMOS and an LVTGMOS and two NPN field transistors, wherein pads are grounded at drain nodes of the two NPN field transistors, and source nodes of the two NPN field transistors. Vcc and Vss are connected to each other, or Vss and Vcc are connected to each other to enhance Vcc.

상기 도 4 는, 상기 도 3 의 회로도에 따라 도시된 반도체소자의 레이아웃도로서, 폐곡선 형태로 일정범위를 갖는 엔웰 가아드링(37)이 구비되고, 상기 엔웰 가아드링(37)의 내측으로 제2소자분리막(35), 피웰 픽업(33), 제1소자분리막(31)의 순서로 각각 구비되고, 상기 제1소자분리막(31) 영역 내에 GMOS(500)와 LVTGMOS(600)이 각각 구비되고, 상기 엔웰 가아드링(37) 내측에 포함된 부분과 상관없이 패드(400)가 구비되며,4 is a layout diagram of the semiconductor device illustrated in accordance with the circuit diagram of FIG. 3, and includes an enwell guard ring 37 having a predetermined range in the form of a closed curve, and includes a second inside of the enwell guard ring 37. The device isolation film 35, the pewell pick-up 33, and the first device isolation film 31 are respectively provided in this order, and the GMOS 500 and the LVTGMOS 600 are respectively provided in the region of the first device isolation film 31. The pad 400 is provided irrespective of a portion included inside the enwell guard ring 37,

상기 엔웰 가아드링(37)과 이격되어 페곡선 형태로 일정범위를 갖는 엔웰 가아드링(37')이 구비되고, 상기 엔웰 가아드링(37')의 내측으로 제2소자분리막(35'), 피웰 픽업(33'), 제1소자분리막(31')의 순서로 각각 구비되고, 상기 제1소자분리막(31') 영역 내에 드레인(39), 제1소오스(41) 및 제2소오스(43)가 구비되되, 상기 드레인(39)의 양측으로 일정간격 이격되어 상기 제1소오스(41) 및 제2소오스(43)가 구비됨으로써 두개의 NPN 필드 트랜지스터가 구비된다. 여기서, 상기 제1,2 소오스(41,43)는 각각 Vss, Vcc 에 연결되거나 Vcc, Vss 에 연결된다. 그리고, 상기 NPN 필드 트랜지스터의 드레인(39)은 엔웰 가아드링(37')과 10 ∼ 30 ㎛ 거리가 유지된다.An enwell guard ring 37 ′ spaced apart from the enwell guard ring 37 and having a predetermined range in a curved shape is provided, and the second device isolation layer 35 ′ and the pewell inside the enwell guard ring 37 ′. The pickup 33 'and the first device isolation film 31' are provided in order, and the drain 39, the first source 41, and the second source 43 are disposed in the region of the first device isolation film 31 '. Is provided, and the first source 41 and the second source 43 are spaced apart at predetermined intervals on both sides of the drain 39 to provide two NPN field transistors. Here, the first and second sources 41 and 43 are connected to Vss and Vcc or Vcc and Vss, respectively. The drain 39 of the NPN field transistor is maintained at a distance of 10 to 30 μm from the enwell guard ring 37 ′.

그리고, 본 발명에 따른 ESD 보호 회로는, ESD 재핑시 GMOS 드레인과 LVTGMOS 사이의 기생 바이폴라 트랜지스터가 작동하면서 GMOS 드레인 쪽에서 과도전류를 발생할 뿐만아니라 GMOS 드레인과 웰 픽업 사이에서 기생 바이폴라 트랜지스터 동작에 의한 전류 통로로 인하여 GMOS 드레인 에서 과도전류가 발생될 수 있으므로, 기생 바이폴라 트랜지스터에 의한 전류 통로를 막기 위하여 GMOS 와 LVTGMOS 사이의 스페이스와 GMOS 드레인과 웰 픽업 사이의 스페이스를 10 ∼ 50 ㎛ 로 하고, NPN 필드 트랜지스터에 Vcc 를 강화해 전류통로를 만들어 주기 위하여 2개의 소오스 노드에 각각 Vss 와 Vcc 를 연결하거나 Vcc 와 Vss 를 연결함으로써 ESD 특성을 강화시킬 수 있다.In addition, the ESD protection circuit according to the present invention, when the parasitic bipolar transistor between the GMOS drain and LVTGMOS is operated during ESD zapping, not only generates a transient current at the GMOS drain side, but also a current path by the parasitic bipolar transistor operation between the GMOS drain and the well pickup. Due to this, transient current may be generated in the GMOS drain, so that the space between the GMOS and LVTGMOS and the space between the GMOS drain and the well pickup are set to 10 to 50 μm to prevent the current path by the parasitic bipolar transistor. In order to make the current path by strengthening Vcc, ESD characteristics can be strengthened by connecting Vss and Vcc to the two source nodes, or by connecting Vcc and Vss, respectively.

한편, 상기 NPN 필드 트랜지스터의 드레인영역에 피웰이나 엔웰을 선택하여 형성할 수 있으며, 상기 NPN 필드 트랜지스터의 드레인 부분에 폴리실리콘이나 실리사이드로 버퍼층을 구비하여 과도전류에 의한 열을 분사시켜 후속 콘택공정시 스파이킹 현상을 방지함으로써 ESD 레벨을 향상시킨다.On the other hand, it is possible to select and form a pwell or an enwell in the drain region of the NPN field transistor, and a buffer layer is formed of polysilicon or silicide in the drain portion of the NPN field transistor to inject heat caused by a transient current during the subsequent contact process. Improves ESD levels by preventing spikes.

이상에서 상세히 기술한 바와 같이 본 발명에 따른 반도체소자는, GMOS 와 LVTGMOS 사이와, GMOS 드레인영역과 웰 픽업 사이의 간격을 넓히고, 패드와 GMOS 와 LVTGMOS 가 직렬로 연결된 시리즈 스택 구조 사이에 두개의 NPN 필드 트랜지스터를 구비하여 전류통로를 형성함으로써 ESD 특성을 향상시킬 수 있는 효과가 있다.As described in detail above, the semiconductor device according to the present invention includes two NPNs between the GMOS and the LVTGMOS, the gap between the GMOS drain region and the well pickup, and the pad and the series stack structure in which the GMOS and LVTGMOS are connected in series. The field transistor is provided to form a current path, thereby improving the ESD characteristics.

Claims (7)

GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와 패드 사이에 별도의 전류통로가 구비되는 반도체소자에 있어서,A semiconductor device having a separate current path between a pad and a series stack structure connected by GMOS and LVTGMOS, 반도체기판 상에 형성된 피웰과,A pewell formed on the semiconductor substrate, 상기 GMOS 와 LVTGMOS 가 이격되어 형성된 섬형태의 제1소자분리막과,An island-shaped first device isolation layer formed by separating the GMOS and LVTGMOS; 상기 섬형태의 소자분리막의 외측에 구비되는 피웰 픽업과,A pewell pick-up provided outside the island-type device isolation film; 상기 피웰 픽업의 외측에 구비되는 제2소자분리막과,A second device isolation film provided outside the pewell pickup; 상기 다른 소자분리막의 외측에 구비되는 엔웰 가아드링과,An enwell guard ring provided at an outer side of the other device isolation film; 상기 GMOS 드레인 영역에 접속되는 패드로 구비되는 GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조와,A series stack structure connected with a GMOS and an LVTGMOS provided by a pad connected to the GMOS drain region; 상기 패드와 GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조 사이에 두개의 NPN 필드 트랜지스터가 구비되되, 상기 두개의 NPN 필드 트랜지스터의 드레인을 통하여 연결되고, 상기 두개의 NPN 필드 트랜지스터의 소오스에 각각 구비되는 Vcc, Vss 가 연결되어 상기 패드와 GMOS 와 LVTGMOS 로 연결된 시리즈 스택 구조 사이에 별도의 전류통로가 포함되는 반도체소자.Two NPN field transistors are provided between the pad and a series stack structure connected by GMOS and LVTGMOS, and are connected through drains of the two NPN field transistors, respectively, Vcc and Vss respectively provided in the sources of the two NPN field transistors. Is connected to the pad and a semiconductor device comprising a separate current path between the series stack structure connected by GMOS and LVTGMOS. 제 1 항에 있어서,The method of claim 1, 상기 GMOS 와 LVTGMOS 는 10 ∼ 30 ㎛ 의 거리가 유지되는 것을 특징으로 하는 반도체소자.The GMOS and LVTGMOS is a semiconductor device, characterized in that the distance of 10 to 30 ㎛ is maintained. 제 1 항에 있어서,The method of claim 1, 상기 GMOS 드레인과 웰 픽업은 10 ∼ 30 ㎛ 의 거리가 유지되는 것을 특징으로 하는 반도체소자.And the GMOS drain and the well pick-up are kept at a distance of 10 to 30 µm. 제 1 항에 있어서,The method of claim 1, 상기 NPN 필드 트랜지스터의 드레인영역과 가아드링은 10 ∼ 30 ㎛ 의 거리가 유지되는 것을 특징으로 하는 반도체소자.And the drain region and the guard ring of the NPN field transistor are kept at a distance of 10 to 30 mu m. 제 1 항에 있어서,The method of claim 1, 상기 두개의 NPN 필드 트랜지스터의 소오스는 각각 Vss, Vcc 에 연결되는 것을 특징으로 하는 반도체소자.And the sources of the two NPN field transistors are connected to Vss and Vcc, respectively. 제 1 항에 있어서,The method of claim 1, 상기 두개의 NPN 필드 트랜지스터의 드레인영역에 피웰 대신 엔웰이 구비되는 것을 특징으로 하는 반도체소자.And an enwell instead of a pewell in the drain regions of the two NPN field transistors. 제 1 항에 있어서,The method of claim 1, 상기 NPN 필드 트랜지스터의 드레인 부분에 폴리실리콘이나 실리사이드로 버퍼층이 구비되는 것을 특징으로 하는 반도체소자.And a buffer layer made of polysilicon or silicide in the drain portion of the NPN field transistor.
KR1019980059556A 1998-12-28 1998-12-28 Semiconductor device KR20000043206A (en)

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