KR20000042693A - Method for obtaining synchronization of pseudo noise code by using digital interface filter - Google Patents

Abstract

PURPOSE: A method for obtaining synchronization of a pseudo noise code(PN code) by using a digital interface filter, is provided to calculate easily by using a memory, when calculating average during a given time for synchronization gain after performing digital interface filtering of I and Q data which are quadrature-modulated through one adder. CONSTITUTION: A method for obtaining synchronization of a pseudo noise code(PN code) by using a digital interface filter, comprises the steps as follows. I and Q data which are quadrature-modulated are reversely diffused, and digital interface filtering is performed by respectively adding the reversely diffused I and Q data with one adder. Results of the added I and Q data are square-operated during an optional given time, and an operation result is stored. Updating is performed, by adding a square-operated result during a presently given time and the operation result stored after calculated during the former given time. Synchronization is confirmed, by detecting a highest value position of data among data having higher value than an optional threshold value among the stored data.

Description

Synchronous Acquisition Device for Pseudo Noise Code Using Digital Matching Filter and Its Method

The present invention relates to a PN code synchronous acquisition device and a method using a digital matched filter, and more particularly, to select the quadrature modulated I and Q data and multiply the pseudo noise code at each position. The present invention relates to a device for synchronizing a pseudo-noise code, which can reduce the complexity of hardware by adding a single adder and filtering the same, and a computer-readable recording medium having recorded thereon a program for executing the method.

The transmitter of the system using the DS / CDMA scheme spreads the input data with an arbitrary pseudo noise code (PN Code) and transmits it, and the receiver performs an operation of synchronizing with the pseudo noise code used for the transmitted input data. . This is called synchronous acquisition, which is a process that must be performed before demodulating data.

Asynchronous method is recommended in the next generation mobile communication system (IMT-2000) of asynchronous type which is currently being standardized, and when using this asynchronous method, it is necessary to obtain fast synchronous.

Accordingly, the present invention selects quadrature modulated I and Q data, multiplies the pseudo noise code at each position, adds it to one adder, and digitally matches and filters the pseudo noise code, thereby reducing the complexity of hardware. An object of the present invention is to provide a synchronous acquisition device and a method thereof and a computer-readable recording medium having recorded thereon a program for executing the method.

1 is a flowchart of a method for synchronizing a PN code according to the present invention.

Figure 2 is a block diagram of a synchronization acquisition device of a PN code according to the present invention.

3 is a timing diagram of a synchronization acquisition device of a PN code according to the present invention;

* Explanation of symbols for the main parts of the drawings

21, 22, 27, 28, 30, 33: latch 23: selector

24: shift register 25: PN code multiplication unit

26,31: Adder 29: Square Root

32; Tri-state buffer

34: Dual Port Random Access Memory (DPRAM)

In the synchronization acquisition method according to the present invention for achieving the above object, in the synchronization acquisition method of the pseudo noise code, by despreading orthogonally modulated I and Q data, one for each of the despread I and Q data A first step of digital matching filtering by adding with an adder of; A second step of storing the result of the calculation after performing a squared operation on the result of the added I data and the Q data for a given time; A third step of adding and updating a result of the squared operation during the current given time and the operation result calculated and stored during the previous given time; And a fourth step of identifying synchronization by finding a position of the highest value among the data larger than a certain threshold value among the stored data.

In addition, a synchronization acquisition device according to the present invention for achieving the above object, the synchronization acquisition device of the pseudo-noise code, de-spreading means for sequentially selecting and despreading orthogonally modulated I and Q input data; First adding means for digitally matching filtering the despreaded output with one adder for each of the I and Q data; Square calculation means for performing a square operation on data of I and Q filtered by the first adding means; An average value calculating means for calculating an average value by adding the output of the square calculating means and the output of the square calculating means calculated during any given time; And central processing means for controlling the operation of the average value calculating means and comparing the value stored in the average value calculating means with an arbitrary threshold value to confirm synchronization.

Meanwhile, the present invention provides a function of digitally matching and filtering a quadrature modulated I and Q data to a synchronous acquisition device including a processor, and then adding one adder to each of the despread I and Q data. and; A square-valued operation of the result of the added I data and the Q data for any given time, and then storing the result of the calculation; A function for adding and storing a squared result of the current given time and a calculated result calculated and stored during the previous given time; And a computer-readable recording medium having recorded thereon a program for executing a function of locating the highest value among data larger than an arbitrary threshold value among the stored data to secure synchronization.

A receiver using a digital matched filter filters quadrature modulated I and Q data, and then processes them through a square root. Take this result and compare it to any threshold, and find the position of the highest value, and it is considered to have acquired synchronization. In the present invention, the filtering operation of the I and Q data can be performed through one adder, and the average value of the filtering data can be obtained for synchronization acquisition. According to the present invention, the complexity of the hardware can be reduced, and the performance of the DS / CDMA system can be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a flowchart of a method for synchronizing a PN code according to the present invention.

I and Q data, which are modulated at right angles from a transmitter in a DS / CDMA system, are generally over-sampled. The receiver selects and uses these I and Q data. In the present invention, when I and Q data are latched and filtered by a clock for selecting input data, I data filtering and Q data filtering can be performed using one adder. In the DS / CDMA system, when multiple users are used, the filtering data is averaged at a given time interval for more accurate synchronization, and memory is used for this purpose. Since data is continuously input in time, according to the present invention, digital matching filtering is performed in a predetermined time unit. In addition, the filter output value output in a predetermined time unit is stored in the memory. In the present invention, the filtered data is stored in the correct location of the memory according to the time unit at a given time interval.

Referring to Figure 1 looks at in detail the synchronization acquisition method according to an embodiment of the present invention.

First, the input I data and the Q data are latched respectively (10), and then the I and Q data are alternately selected (11) to digitally filter each of the I and Q data (12). In the present invention, the data obtained by multiplying the pseudo noise code with respect to each of the I and Q data is added to filter the data of each of the I and Q.

The filtered I and Q data calculate the average for a given time for more accurate synchronization. The process is as follows.

Each filtered data of I and Q is computed via a square root (13), and the result of the operation is stored in memory (14). Then, digitally match the I and Q data for a given time interval (15), and then squarely compute the filtered data of I and Q, and add the result of the squared operation and the result of the previous calculated and stored result. Repeat the process of saving to memory.

When the given time is over, if the highest value is found among the stored thresholds, it is determined that synchronization is obtained (15). Otherwise, if there is no data exceeding the threshold, it is repeated from the beginning of the filtering operation.

2 is a block diagram of a PN code synchronous acquisition device according to an embodiment of the present invention, where 21, 22, 27, 28, 30, and 33 are latches, 23 are selectors, and 24 are shifts. A register, 25 denotes a PN code multiplier, 26 and 31 respectively, an adder, 29 a square root, 32 a three-state buffer, and 34 a dual port random access memory (DPRAM).

The quadrature modulated inputs I and Q data are latched in the first latch 21 and the second latch 22, respectively, by the first clock Clk_1 as the selection clock. The outputs of the first latch 21 and the second latch 22 are selected and alternately output by the selector 23 operated by the control of the first clock Clk_1, which is the selection clock. In the embodiment of the present invention, a selector is implemented using a 2 × 1 multiplexer (MUX).

The output of the selector 23 is input to the input of the shift register 24, and the data input by the second clock Clk_2 twice as fast as the first clock Clk_1 is shifted. The output of the shift register 24 is multiplied by the PN code at each position by the PN code multiplier 25 composed of a plurality of multipliers, and the output of each multiplier is input to the first adder 26. The first adder 26 adds the output of each multiplier, thereby performing digital match filtering. The filtering data of the I data among the digital match-filtered outputs by the first adder 26 is latched to the third latch 27 at the rising edge of the first clock Clk_1, and the filtering data of the Q data is first filtered. It is latched in the fourth latch 28 at the falling edge of the clock Clk_1. The outputs of the latched third latch 27 and the fourth latch 28 are respectively input to the input terminal of the square root 29 to obtain the magnitude of the filtering result. The square root 29 performs a square arithmetic operation on the input I filtering data and the Q filtering data, respectively, and the result is latched in the fifth latch 30 by the first clock Clk_1. The process of filtering the I and Q data results in a given time ( t _slot ) For a certain interval ( t _c ) And the result is stored in memory. Here, given time ( t _slot ) Is an interval ( t _c Is an integer multiple of). That is, t _c ) Denotes one chip spacing. In an embodiment of the present invention, an addition operation is performed at a half chip spacing ( t _slot , The result is stored in the dual port memory (DPRAM) 34. In general, only one time, i.e. t _slot ) Does not perform digital match filtering for t _slot Will be filtered. In this case, the first given time ( t _slot ) And store the result for a second time t _slot ) Is added to the first filtered result. In FIG. 2 the second adder 31 is given the second given time ( t _slot ), Starting at the second given time ( t _slot Filtering results calculated during the first time t _slot Is added to the calculated result, and updated at the same position of the same address.

Looking more specifically at this process, the first given time ( t _slot The result of the square root 29 is output at regular intervals and stored in the dual port RAM 34 through the second adder 31 and the tri-state buffer 32. And given a time ( t _slot After the operation is completed, the address (Address_L), the chip enable signal (CE_L) and the read / write signal (RW_B_L) are inputted through the left port of the dual port RAM 34, and stored in the dual port RAM 34. First given time ( t _slot ) Are sequentially output and latched in the sixth latch 33. The output of the sixth latch 33 and the output of the fifth latch 30 are added by the second adder 31. Through this process, the first given time ( t _slot ) And the second given time ( t _slot ) Is calculated and stored in the memo area with the same address. Here, a tri-state buffer 32 is used to prevent the output of the second adder 31 from being input into the data input / output stage of the memory while reading data from the memory. The tri-state buffer 32 inverts the read / write signal and uses it as a control signal. The latch clock of the sixth latch 33 uses a read / write signal and a chip enable signal in a logic combination. In general, reads are made at the time when the same clock rises, and writes are made at the time when the same clock falls. Through this process, t _slot ) And the current time ( t _slot The calculated results are added while repeating reads and writes at 1/2 chip intervals.

Given time ( t _slot After the operation by the second adder is completed, the interrupt signal INT is input from the dual port RAM 34 to the CPU, indicating that the calculation is completed. At this time, the central processing unit reads the data stored in the memory through the right port, and recognizes that it is synchronized when the highest value is found among the read data that exceeds a given threshold. If there is no value exceeding the threshold, synchronization is performed again by performing the filtering operation from the beginning.

3 is a timing diagram of a synchronization acquisition device of a PN code according to the present invention.

All signals in the timing diagram of FIG. 3 are shown in consideration of delay based on the second clock Clk_2.

As can be seen from the figure, the frequency of the first clock Clk_1 as the selection clock is half of the frequency of the second clock Clk_2. The output MF_OUT of the square root 29 is output every one period of the first clock Clk_1, and this result is the input of the second adder 31. The data Data_L_Read which reads and latches the data stored at the Address_L address is input to another input terminal of the second adder 31, and the result of the second adder 31 is again written to the Address_L address. This process takes a given time ( t _slot Continued for a while. The chip enable signal CE_L has the same period as the second clock, and the read / write signal has the same period as the first clock.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention as described above, the digitally matched filtering of quadrature modulated I and Q data is performed through one adder, and when calculating an average for a given time to obtain synchronization, the hardware can be easily calculated using a memory. The complexity is significantly reduced, and manufacturing costs are reduced.

Claims (11)

In the method of acquiring the synchronous noise code, Despreading the quadrature modulated I and Q data, and then digitally matching and filtering the despread I and Q data by adding one adder to each of the despread I and Q data; A second step of storing the result of the calculation after performing a squared operation on the result of the added I data and the Q data for a given time; A third step of adding and updating a result of the squared operation for the current given time and the operation result calculated and stored during the previous given time; And A fourth step of identifying synchronization by finding the position of the highest value among the data larger than a certain threshold value among the stored data Synchronous acquisition method of pseudo noise code comprising a. The method of claim 1, The first step, Latching quadrature modulated I and Q data, respectively; A sixth step of sequentially selecting the latched I and Q data; A seventh step of multiplying a pseudo noise code at a predetermined position for each of the selected I and Q data; And An eighth step of digital match filtering the data of each of I and Q by adding the multiplied data Synchronous acquisition method of the pseudo noise code comprising a. In the synchronization acquisition device of the pseudo noise code, Despreading means for sequentially selecting and despreading rectangularly modulated I and Q input data; First adding means for digitally matching filtering the despreaded output with one adder for each of the I and Q data; Square calculation means for performing a square operation on data of I and Q filtered by the first adding means; An average value calculating means for calculating an average value by adding the output of the square calculating means and the output of the square calculating means calculated during any given time; And Central processing means for controlling the operation of the average value calculating means, and comparing the value stored in the average value calculating means with an arbitrary threshold value to confirm synchronization. Synchronous acquisition device of the pseudo noise code having a. The method of claim 3, wherein The despreading means, First and second latching means for latching quadrature modulated I and Q data, respectively; Selection means for sequentially selecting outputs of the first and second latch means; Shift means for shifting the output of the selection means; And A plurality of multiplication means for multiplying and outputting each output of the shift means by a pseudo noise code Synchronous acquisition device of a pseudo noise code, characterized in that it comprises a. The method according to claim 3 or 4, The square calculation means, Third and fourth latching means for latching respective data of I and Q filtered by the first adding means, respectively; Fifth latch means for latching the squared output Synchronous acquisition device of a pseudo noise code, characterized in that it further comprises. The method of claim 5, The average value calculating means, Second adding means for adding the output of the square calculating means and the square calculated data during the previous given time stored; Tri-state buffering means for controlling the output state of the data calculated by said adding means; Dual port memory means for storing the output of the tri-state buffering means under the control of the central processing means and outputting the stored data; And Sixth latch means for latching the output of said dual port memory means and outputting it to said second adding means. Synchronous acquisition device of a pseudo noise code, characterized in that it comprises a. The method of claim 6, The first to fifth latch means, And a first clock used as a selection control signal of the selection means as a latch clock. The method of claim 7, wherein The shift means, And a second clock twice as fast as the first clock as a shift clock. The method of claim 3, wherein The central processing means, And a synchronous acquisition device for synchronizing noise by finding a position of the highest value among values larger than an arbitrary threshold value among the values stored in the average calculating means. The method of claim 8, The sixth latch means, And a read / write signal and a chip enable signal of the dual port memory means are used as a latch clock. In a synchronous acquisition device having a processor, Despreading orthogonally modulated I and Q data, and then digitally matching filtering by adding one adder to each of the despread I and Q data; A square-valued operation of the result of the added I data and the Q data for any given time, and then storing the result of the calculation; A function for adding and storing a squared result of the current given time and a calculated result calculated and stored during the previous given time; And A function to secure the synchronization by finding the position of the highest value among the data larger than any threshold value among the stored data. A computer-readable recording medium having recorded thereon a program for executing the program.