KR20000041167A - High-speed burn-in test board for integrated circuit product - Google Patents

Abstract

PURPOSE: A high-speed burn-in test board is provided to be capable of testing in a high speed by removing a cause of an electromagnetic induction voltage noise and a parasite load capacitance. CONSTITUTION: In a high-speed burn-in test board, a ferrite core is inserted between an input/output terminal and an input/output part of a burn-in test equipment, or at an interconnection line for an input/output terminal of a socket for a test on a test board, in order to prevent an electromagnetic noise. Printed circuit board patterns(1,2) of a power supply and a ground voltage are divided according to each test product group(A,B to n), and switches(6-1 to 6-n) are respectively installed between power and ground supply lines of each product group and a power supply device so as to supply the power supply voltage and the ground voltage only to a product group to be tested.

Description

Fast Burn-in Test Boards for Integrated Circuit Products

In general, semiconductor products, especially memory devices and micro-processor products, often have an initial failure of potential. To detect them, they input an electrical signal in an atmosphere at 125 ° C and operate for a specific time (this is called a dynamic burn-in test). After that, the temperature is lowered to about 75 ° C. to 85 ° C. and a burn-in test (Test After Burn-in, hereinafter referred to as test burn-in) is performed to select defective products generated during the dynamic burn-in test. These tests are carried out sequentially as they are. Briefly describing their tests, the dynamic burn-in test simultaneously operates all parallels of the EUT loaded in the burn-in test equipment in a high temperature (125 ° C) environment in order to accelerate the latent defective product. At the end of the test, only the temperature is lowered to check the product characteristics, which is the test burn-in. These tests are connected in parallel by dividing the number of simultaneous tests (Parallel) into test product groups as shown in [Fig. 1] and [Fig. 5A] by the number of burn-in test equipment I / O channels. As shown in FIG. 5D], a specific test product group divided by the number of I / O channels is sequentially tested while selecting 15 (Scan signals), and during the dynamic burn-in test, 15-1, 15-2, 15- of 15 n Select all and test. In other words, 15-1 is selected and the test product group 'A' is selected, and 15-2 is selected and the test product group 'B' ... 15-n is selected to test sequentially with the test product group 'n'.

Conventional burn-in boards and burn-in test equipment have the following two problems as described above in the test. One of them is the parasitic capacitance existing inside the printed circuit board of the burn-in test board and inside the product, which acts as a load on the output side of the burn-in test equipment. As described above, the parallel test in the burn-in test includes a parasitic load capacity (Parasitic Capacitance) 12 and 22 existing in each terminal of the product as shown in FIG. 3A and a through hole for each terminal on the burn-in test board printed circuit board ( The parasitic load capacities 11 and 21 due to the through holes become the load on the output side of the burn-in test equipment, which becomes a barrier to the realization of the high speed burn-in test. For this reason, the values of the time constants (RC) of these parasitic load capacities are increased so that the rising time and falling time of the input signal are long, so that the input signal is high at 42-a, [Fig. 4B]. It is because it is distorted like 42-b, making high speed test impossible. Conventionally, in order to improve the rising time and the falling time due to this cause, the parts of the through hole are attached to the through-hole type, but these methods alone are used in the product of FIG. 3A. Parasitic load capacity of through hole for IC socket and parasitic load capacity of each terminal parasitic inside the product, that is, 11, 21, 12, 22 cannot be solved.

Another problem is that the input / output pins (I / O pins) of the C-MOS IC products have an N-channel output part and an N-channel TR structure as shown in FIG. 6A. Or it is an input connected to the gate of the P-channel TR. Due to this structure, when the input signal to the I / O pin of the C-MOS product changes (logic '1' to '0' or logic '0' to '1'), the input signal Depending on the polarity of the P-channel TR, or N-channel TR of the output section 'Short Circuit' (see Fig. 9) reference instantaneously occurs. Because of this 'short circuit' phenomenon, the instantaneous current (Ipc) through 4-1, which is the output impedance of the test equipment driver 4 burn-in at 1 (+ voltage) and 2 (-voltage) connected to the TR. Or Inc) flows. Due to the electromagnetic wave (EMI) generated by this instantaneous current change, induced voltage noise as shown in FIG. 6C is generated in the adjacent terminal. In addition, since many products are connected in parallel to one output driver to perform burn-in test, the current burn-in test board, the instantaneous current at the connector 20 point of FIG. The sum of the instantaneous currents and the intensity of the electromagnetic wave is increased by the number of parallel terminals. Therefore, the instantaneous current flowing excessively in an input / output terminal (I / O pin) as shown in [Fig. 6a] generates an electromagnetic wave (EMI), and the electromagnetic wave induces the adjacent terminal as shown in [Fig. 6c] and [7]. Voltage noise is generated largely. This induced voltage noise may cause the latch-up that occurs under the structure of the C-MOS IC, causing damage to the product during the burn-in test, and greatly affecting the detection of defective products in the test burn-in. . That is, since the logic value of the input signal changes instantaneously at the point where the induced voltage noise is generated as shown in [Fig. do.

The present invention is a fast burn-in test that improves the problem of increasing the rising time and falling time of the input signal and the electromagnetic wave problem at the input and output terminals by the parasitic capacitance. The burn-in test board and the output of the burn-in test equipment.

First, conventionally, when the test burn-in as shown in FIG. 1, the power supply voltage (product power supply and external load power supply, later referred to as power supply voltage) supply line (pattern of the printed circuit board) is branched to each product on the burned-in test board. Has been tested. For this reason, the power supply voltage was also supplied to the test product group waiting for the test, thereby increasing the weight of 12, 22 and 11, 21 (parasitic load capacity) of [FIG. 3A]. In order to avoid the weighting of the present invention, the + power supply voltage and the-power supply voltage (ground) are separated for each test product group as shown in FIGS. 2A, 2B, 5B, and 5C. It was possible to select whether to supply or cut off the power supply voltage depending on whether the test product group was tested. As a reason, the parasitic load capacities on the burn-in test board are 11, 21, and 12, 22 as shown in [Fig. 3A]. It is to make open circuit by making open circuit with -n switch. Moreover, since test burn-ins test many products in parallel, their parasitic load capacity increases as the number of parallel test products increases as described above.

The present invention separates the printed circuit board pattern of the power supply voltage (including ground) for the test product group as 200 and 300 of FIG. 3C as a means of eliminating the parasitic load capacity, and selects only the power supply voltage of the test product group. 6-1, 6-2 ... 6-n of [Fig. 2a], [Fig. 2b] and [Fig. 5b], [Fig. 5c] to the supply voltage supply device or the supply line of the supply voltage to be supplied with The supply voltage for the product under test can be selectively supplied according to the state of the test product group (under test or during test standby). As a method of implementing this, the most important is to check the pattern of the printed circuit board of 1 and 2 (for power supply voltage (+,-) of each test product group) of [Fig. 5B] and [Fig. 5C] on the burn-in test board. It is separated by the test product group as shown in 200, 300 of FIG. Then, each separated pattern (Pattern) is electrically controlled mechanical switches (such as mechanical relays), such as 6-1, 6-2 ... 6-n of Figs. 5b and 5c, or By attaching a solid-state switch, it is possible to select the supply voltage (+,-) for each test product group. To illustrate in more detail, when testing the test product group 'A' as shown in [Fig. 2a] and [Fig. 2b] of the power supply voltage (1, 2) separated by each test product group, turn on 6-1, the test standby The power supply 6-n of the test product group 'n' is turned off so that the parasitic load capacity of the test product group 'n' does not work. On the contrary, when testing the test product group 'n', 6-n is turned on. By turning off the power supply switch of the test product group 'A', 6-1, during the test standby, the parasitic load capacity of the test product group 'A' is prevented from working.

As a solution to the electromagnetic noise, a ferrite core 9 (or 10) is manufactured as shown in FIG. 7A, in which the conventional method such as FIG. 1 uses only insulation resistance 3 between products. Insert between I / O pin and I / O channel of burn-in test equipment of each test socket of each product on burn-in test board as shown in Fig. 7b and 7c. It is inserted into connecting line for input / output terminal.

1 is a conceptual diagram of a power supply voltage of a conventional burn-in test board and a product,

2a and 2b is a conceptual diagram of the power supply voltage of the burn-in test board and the product of the present invention,

3A is a conceptual diagram of generation of parasitic load capacity on a conventional burn-in test board,

3B is a cross-sectional view of the parasitic capacitance load on a conventional burn-in test board,

Figure 3c is a cross-sectional view of the generation of parasitic load capacity when the power supply voltage for each test product group of the present invention,

4A is a circuit diagram illustrating separation of a supply voltage (+,-) and a parasitic load capacity;

4B illustrates the rise time and fall time of the input signal due to parasitic load capacitance.

5A is a conceptual diagram of a test product group and a power supply voltage (+,-) separation diagram according to a test product group;

FIG. 5B is an exemplary diagram in which the means for selecting a separate power supply voltage for each test product group is installed on a burn-in test board. FIG.

Figure 5c is an exemplary diagram when the function of the separate power supply voltage selection by test product group is installed in the burn-in test equipment,

5D illustrates an example of a control signal for selection of a separated power supply voltage;

6A is an internal structure and instantaneous current relationship diagram of input / output signal terminals (I / O pins) of the product;

6B is a diagram illustrating a relationship between an input signal and an instantaneous current of an input / output terminal (I / O pin) of a product;

6C is a diagram illustrating noise generation of adjacent terminals by instantaneous currents of input and output terminals (I / O pins),

7A is a diagram when the Ferrite Core is inserted into the burn-in test equipment output;

7B is a diagram in which a SMD type Ferrite Core is attached to a burn-in test board.

7C is a diagram illustrating a case where a ferrite core for each insulation resistance of the burn-in test board is inserted;

FIG. 8A is an exemplary diagram when the ferrite core and the power supply voltage selection switch and the switch control circuit of the present invention are mounted on a burn-in test board. FIG.

FIG. 8B is an illustration of a case where the ferrite core of the present invention, a selection switch of a power supply voltage, and a switch control circuit are installed outside a burn-in test board; FIG.

9 is a reference relating to a short circuit / short current.

(Explanation of symbols for the main parts of the drawing)

1: + power supply line 2, 2-1, 2-2:-power supply line (ground)

3: Insulation resistance between product terminals 4: Output part for I / O terminal

4-1: Output impedance of output driver for I / O terminal

41: Input signal of input / output terminal

42: Input signal at parasitic capacitance load

42-a: Falling signal of input signal under parasitic capacitance load

42-b: Rise time of input signal under parasitic capacitance load

43: Input signal when only one test product group is selected

5: Output terminal for input terminal 51: Input signal of input terminal

6-1, 6-2, 6-n: Separate power supply voltage selection switch

9: ring type ferrite core 10: smd type ferrite core

11: Parasitic load capacity generated between the printed circuit board and the + supply voltage

12: Parasitic load capacity generated between the inside of the product terminal and the + supply voltage

15: Test signal selection signal (Scan Signal)

15-1: Selection signal of test product group 'A'

15-2: Selection signal of test product group 'B'

15-n: Selection signal of test product group 'n'

20: Connector for connecting burn-in test board and burn-in test equipment

21: Parasitic load capacity generated between the inside of the printed circuit board and the power supply voltage

22: Parasitic load capacity generated between the product terminal and-power supply voltage

30: burn-in test board

31: The sum of the parasitic capacity loads generated between the internal and external positive supply voltage

32: Total parasitic capacity load generated between the internal and external -power supply voltage

60: Decoder for control of power voltage selection switch for test product group

100: Tested product 200, 300: Printed circuit board of separated power supply voltage

In the configuration of the present invention, in suppressing the generation of parasitic load capacity at each test product terminal, test burn-in is performed as shown in FIG. 5A with 1 (+ power supply voltage supply line) and 2 (-supply voltage (ground) supply line). Priority shall be given to the separate structure of each test product group on the board. And this can be electrically selected as necessary (6-1, 6-2, 6-n of [Fig. 5b] [Fig. 5c] is equipped with a burn-in test as shown in [Fig. 8b] or [Fig. 8a] and In other words, this is a structure installed on the burn-in test board, that is, if the power supply voltage can be separately supplied by the test product group in the burn-in test equipment, as shown in FIG. 5C and FIG. Only the + supply voltage supply line) and 2 (the-supply voltage (ground) supply line) are separated from each other, otherwise the structure is provided in the burn-in test board as shown in Figs. 5B and 8A. In the case of-supply voltage (grounding) on the board, the entire PCB layer is used as the ground of the product, and it may be used as a common for all test product groups.

Conventional burn-in test boards and burn-in test equipment have limitations for high-speed testing because of the effects of parasitic load on the burn-in test board and the induced voltage noise of adjacent terminals by electromagnetic waves at the input and output terminals.

As described above, the present invention eliminates the causes of these parasitic load capacities and electromagnetic wave induced voltage noise to enable a high speed test. As a result, high-speed test is possible with burn-in test equipment, so test items that could be tested only with expensive test equipment can be tested with lower-cost burn-in test equipment. Therefore, the investment cost of the test equipment can be greatly reduced.

Claims (2)

A burn-in test board for an integrated circuit product (IC), wherein a printed circuit board pattern of a + supply voltage supply line and a-supply voltage (ground) supply line for an EUT is separated for each test product group. In addition, it is equipped with a solid state switch or a mechanical switch that can be turned on and off using a signal such as a test signal of the test equipment of the test equipment, if necessary, with a separate + power voltage supply line and ground. One time test board. Output driver of the burn-in test equipment using a ferrite core or a current retardative diode (CRD) which suppresses the flow of instantaneous current in order to suppress electromagnetic noise. And burn-in test board with Ferrite Core or CRD (Current Regulative Diode) attached to the output pin of the product.