KR20000038821A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to prevent degradation of an electrostatic discharge protection circuit. CONSTITUTION: A method for fabricating a semiconductor device comprises forming n-MOS transistors on a memory cell region(c) and an electrostatic discharge(ESD) protection region(d) of a p-substrate(30), forming a silicide layer(36) on a gate and a diffusion region(33, 35), forming a first lay-insulating layer(37), forming a first and a second contact hole at the same time by removing a portion of the first lay-insulating layer, wherein the first contact hole is formed to expose a portion of the silicide layer on the diffusion region and the second contact hole is formed to expose a portion of the silicide layer on the ESD protection region, forming a first and a second plug(38, 39) by filling the contact holes, forming a second lay-insulating layer(40), forming a via hole exposing the first plug(38), forming a conductive layer by filling the via hole, and forming a bit line(42) by patterning the conductive layer.

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a gate edge at a drain contact portion of an NMOS field effect transistor, which is used as an ESD protection circuit in a product in which a salicide is formed. ISIS protective circuit fabrication of semiconductor device which prevents degradation of ESDI protective circuit by delaying ESDI pulse due to resistance decrease caused by outdiffusion phenomenon due to salicide formation in the drain region up to the edge) It is about a method.

As semiconductor devices are highly integrated, impurity regions and wiring widths used as source and drain regions are reduced. As a result, the semiconductor device has a problem in that the resistance of the impurity region and the wiring increases, thereby lowering the operation speed.

Therefore, when wiring of elements in the semiconductor device is made of a low resistance material such as aluminum alloy and tungsten, or formed of polycrystalline silicon as in the gate electrode, silicide or salicide may be formed to reduce the resistance. When the silicide layer is formed on the gate electrode formed of polycrystalline silicon, the silicide layer is formed on the surface of the impurity region to reduce the resistance.

The input / output terminals of the semiconductor device are susceptible to breakdown by electrostatic discharge due to a drop in breakdown voltage due to a transient voltage or a thin gate oxide film. That is, when the drain region has low resistance due to silicide formation, the applied voltage is not evenly distributed and is concentrated in the lightly doped drain (LDD) region, thereby destroying the semiconductor device. Therefore, an ESD protection transistor is formed to prevent electrostatic discharge destruction by evenly spreading the applied voltage by increasing the resistance of the impurity region used as the source and drain regions and the gate electrode formed of polycrystalline silicon in the input / output terminals.

However, in the case where the transistor used in the ESD protection circuit is formed of an NMOS transistor and a salicide is formed, the salicide is formed not only on the gate but also on the upper surface of the drain and the source. At this time, the sheet resistance of the n + section before silicide formation is reduced from several tens of Ω to several Ω after silicide formation. Therefore, when the ESDI pulse is applied to the ESD circuit through the input / output pad, a high current flows toward the silicide of the drain and concentrates the current at the gate edge of the n-type junction, which is mainly a part where the parasitic bipolar transistor operates. do.

When the current is concentrated only on a specific portion of the silicon substrate, the MOS transistor is destroyed by the voltage of the isdy pulse applied, and thus the operation as the protection circuit cannot be performed. References (Ajiith Amerasekera, Charvaka Duvvury, "The Impact of Technology Scaling on ESD Robustness and Protection Circuit Design" EOS / ESD procee., Pp.237-245,1994) suggest that silicides are more likely It is pointed out that the pulse causes about five times the device degradation.

1A to 1D are cross-sectional views illustrating a manufacturing process of an ESD protection circuit of a semiconductor device according to the prior art. At this time, the region "a" is a memory cell formation region and the region "b" is an ESD protection circuit formation region.

Referring to FIG. 1A, a field oxide film 11 is formed on a predetermined portion of a p-type silicon substrate 10 as a semiconductor substrate by a method such as LOCOS or shallow trench isolation (STI), and then a gate insulating film 12 formed of an oxide film, NMOS transistors formed of a gate 13 formed of polysilicon doped with impurities, an n-type impurity diffusion region 15, a gate sidewall spacer 14 made of an insulating film, and the like are formed in regions a and b, respectively.

Referring to FIG. 1B, a thin cobalt metal layer is formed on the entire surface of the substrate, and then heat-treated to form a silicide layer 16 on the impurity diffusion region 15 and the upper surface of the gate 13 of the substrate. At this time, the formed silicide or salicide layer is composed of CoSi ₂ and serves to reduce the contact resistance.

Referring to FIG. 1C, the first interlayer insulating layer 17 for interlayer insulation is deposited on the entire surface of the substrate 10 including the silicide layer 16 and then planarized.

A photolithography process is performed on the first interlayer insulating layer 17 to expose the surface of the silicide layer 16 located on the upper surface of the common impurity diffusion region 15 between the transistors of the memory cell formation region a. Form a hole.

Then, doped polysilicon is deposited on the entire surface of the first interlayer insulating layer 17 by CVD to fill the contact holes, and then patterned to form the bit line pads 18.

Referring to FIG. 1D, a second interlayer insulating layer 19 for controlling a step is formed on the first interlayer insulating layer 17 to cover the bit line pad 18.

The upper surface of the bit line pad 18 is exposed by removing a predetermined portion of the second interlayer insulating layer 19 to form a via hole, and then a polysilicon doped with a second hole is filled with the second interlayer insulating layer 19. ) And then patterned to complete plug 20 and bit line 21.

As described above, in the ESD protection circuit of the conventional semiconductor device, when the transistors used in the ESD protection circuit are formed as NMOS transistors and the salicides are formed, the current of the ESD protection pulse is applied when the current is concentrated only at a specific part of the silicon substrate. There is a problem in that the MOS transistor is destroyed by the voltage, so that the operation as the protection circuit cannot be performed.

Accordingly, an object of the present invention is due to an out-diffusion phenomenon caused by salicide formation in the drain region from the drain contact portion to the gate edge of an NMOS field effect transistor used as an ESD protection circuit in a product where salicide is formed. The present invention provides a method for manufacturing an ESD protection circuit of a semiconductor device which prevents degradation of the ESD protection circuit by delaying the ESD pulse.

SUMMARY OF THE INVENTION A method of manufacturing an ESD protection circuit of a semiconductor device according to the present invention for achieving the above objects includes a gate insulating film and a gate on a first conductive semiconductor substrate having a memory cell formation region and an ESD protection circuit formation region separated by a first insulating layer. Forming a second conductivity type MOS transistor comprising a second conductivity type impurity diffusion region and a gate sidewall spacer formed of a second insulating film on the semiconductor substrate of the memory cell formation region and the ESD protection circuit formation region, respectively; Forming a silicide layer on the gate upper surface and the surface of the second conductivity type impurity diffusion region, forming a first interlayer dielectric layer on the semiconductor substrate to cover the transistor on which the silicide layer is formed, and a first interlayer dielectric layer; A portion of the silicide layer of the impurity diffusion region of the memory cell formation region is exposed by removing a predetermined portion of the The key is formed simultaneously with the second contact hole exposing a part of the silicide layer of the impurity diffusion region of the first contact hole and the ESD protection circuit forming region, and filling the first contact hole and the second contact hole. Forming a first plug and a second plug having a second plug; forming a second interlayer insulating layer on the first interlayer insulating layer so as to cover the first plug and the second plug; Forming a via hole exposing the plug, forming a conductive layer to fill the via hole on the second interlayer insulating layer, and patterning the conductive layer to form a bit line.

1A to 1D are cross-sectional views of an ISD protective circuit manufacturing process of a semiconductor device according to the related art.

2A to 2D are cross-sectional views of a manufacturing process of an ESD protective circuit of a semiconductor device according to the present invention.

In the present invention, the drain contact of the NMOS transistor used as the ESD protection circuit is formed at the same time as the contact hole forming process for forming the bit line pad of the memory cell formation region, and then the doped polysilicon is deposited to form a silicide-drain. And electrically connect to form a contact of the ESD protection circuit region.

The formation of silicide in the source / drain regions causes the breakdown of a specific region where current is concentrated when the ESD voltage is applied to the protection circuit. Therefore, even when silicide is formed in the drain region as in the present invention, when doped polysilicon having a relatively high resistance is deposited on the contact portion with the drain, the delay phenomenon of the Isdy pulse with a fast rising time is reduced. To induce. This delay provides time margin for bipolar transistor action across the drain caption. In general, when silicide is not formed in the source / drain region, the NMOS constituting the ESD protection circuit increases as the drain contact to gate space increases, that is, the resistance of the region increases. It is well known that the uniform turn-on at the drain junction of the transistor increases, leading to an increase in the ESD failure voltage.

In the present invention, uniform turn-off is performed using doped polysilicon having a relatively high resistance without using a material such as tungsten having a small resistance, which generally uses contact plugs of a drain and a source of an NMOS transistor used as an ESD protection circuit. Can be induced.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views of an ISD protective circuit manufacturing process of a semiconductor device according to the present invention. At this time, the area "c" is a memory cell formation area and the area "d" is an ESD protection circuit formation area of the input / output terminal.

Referring to FIG. 2A, a field oxide film 31 is formed on a predetermined portion of a p-type silicon substrate 30, which is a semiconductor substrate, by a method such as LOCOS or shallow trench isolation (STI), followed by a gate insulating film 32 formed of an oxide film, NMOS transistors formed of a gate 33 formed of polysilicon doped with impurities, an n-type impurity diffusion region 35, a gate sidewall spacer 34 made of an insulating film, and the like are formed in regions c and d, respectively.

Referring to FIG. 2B, a thin cobalt metal layer is formed on the entire surface of the substrate, and then a heat treatment is performed to form the silicide layer 36 on the impurity diffusion region 33 and the upper surface of the gate 33 of the exposed substrate. At this time, the formed silicide or salicide layer is composed of CoSi ₂ and serves to reduce the contact resistance.

Referring to FIG. 2C, the first interlayer insulating layer 37 for interlayer insulation is deposited on the entire surface of the substrate 30 including the silicide layer 36 and then planarized.

Then, a photolithography process is performed on the first interlayer insulating layer 37 to protect the surface of the silicide layer 36 located on the upper surface of the common impurity diffusion region 35 between the transistors of the memory cell formation region c and the ESD protection. A contact hole is formed in which the silicide layer 36 formed on the surface of the impurity diffusion region 35 in the circuit formation region d is exposed.

Then, doped polysilicon is deposited on the entire surface of the first interlayer insulating layer 37 by CVD to fill the contact holes of the memory cell forming region c and the ESD protection circuit forming region d with photolithography. Patterning is performed by photolithography to simultaneously form the bit line pad 38 and the ESD contact plug 39.

Referring to FIG. 2D, a second interlayer insulating layer 40 may be formed on the first interlayer insulating layer 37 to cover the bit line pad 38 and the ISD contact plug 39 to control the level difference. do.

The upper surface of the bit line pad 38 is exposed by removing a predetermined portion of the second interlayer insulating layer 40 to form a via hole, and then a conductive layer such as polysilicon doped to fill the via hole is interposed therebetween. Deposited on the insulating layer 40 and then patterned by photolithography to complete the plug 41 and the bit line 42. At this time, the bit lines 42 are formed only in the memory cell formation region c.

Accordingly, the present invention provides a reduction in resistance due to out-diffusion caused by the formation of salicide in the drain region from the drain contact portion to the gate edge of an NMOS field effect transistor used as an ESD protective circuit in a product where salicide is formed. The deterioration of the low-ESD protection circuit is prevented by delaying the ES-DE pulse.

Claims (4)

A second structure including a gate insulating film, a gate, a second conductive impurity diffusion region, and a gate sidewall spacer formed on the first conductive semiconductor substrate having the memory cell forming region and the ESD protection circuit forming region separated by the first insulating film. Forming a conductive MOS transistor on the semiconductor substrate in the memory cell formation region and the ESD protection circuit formation region, respectively; Forming a silicide layer on the exposed upper surface of the gate and the surface of the second conductivity type impurity diffusion region; Forming a first interlayer insulating layer on the semiconductor substrate so as to cover the transistor on which the silicide layer is formed; A first contact hole exposing a portion of the silicide layer of the impurity diffusion region of the memory cell formation region to remove a predetermined portion of the first interlayer insulating layer and the impurity diffusion region of the ESD protection circuit formation region Simultaneously forming a second contact hole exposing a part surface of the silicide layer; Forming a first plug and a second plug having conductivity to fill the first contact hole and the second contact hole; Forming a second interlayer insulating layer on the first interlayer insulating layer so as to cover the first plug and the second plug; Forming a via hole exposing the first plug in the second interlayer insulating layer; Forming a conductive layer on the second interlayer insulating layer to fill the via hole; And forming a bit line by patterning the conductive layer. The method of claim 1, wherein the first plug and the second plug are formed of doped polysilicon. The method of claim 1, wherein the bit line is formed only in the memory cell formation region. The method of manufacturing a semiconductor device according to claim 1, wherein the silicide layer is formed of salicide using cobalt.