KR20000037516A - Universal serial bus core and method for monitoring the same - Google Patents

Abstract

PURPOSE: A universal serial bus core and a method for monitoring the universal serial bus core are provided to accomplish a test mode of a universal series bus core by using a duplicate circulating detecting circuit. CONSTITUTION: A first and a second multiplexers(120,130) receive first and second input signals which reply to a test activating signal for monitoring a circuit and start the operation of an activated test mode, and third and fourth input signals. First and second test circuits process the signals which is outputted from the first and second multiplexers, and generate first and second signature signals which correspond to the first to fourth input signals. A third multiplexer(180) selects one of the first and second signature signals. A fourth multiplexer receives the first and second signature signals from the third multiplexer(180), and outputs test data according to a test mode.

Description

UNIVERSAL SERIAL BUS CORE HAVING MONITORING FUNCTION REDUNDANCY CHECKING CIRCUIT AND MONITORING METHOD OF THE SAME

TECHNICAL FIELD The present invention relates to test monitoring circuits for integrated circuits, and more particularly, to an apparatus and method for scanning test specific internal circuits of a USB core using CRC circuits.

As integrated circuits become more versatile and complex, it becomes increasingly difficult to test them, and in designing integrated circuits, it is difficult to achieve as many fault coverages as desired. To overcome this, a scan design is created.

A scan design, a boundary scan design, chains sequential elements into a circuit to create a long-listed shift register that can be used to control or block blocks inside the circuit. It is used for observability to improve fault coverage of integrated circuits.

However, this method must have each register as long as the scan chain. After shifting serially input data to each next register to set the desired value, normal operation is performed and each register value is shifted again.

Therefore, the test time of the integrated circuit is lengthened by comparing each expected value with the result after normal operation outside of the integrated circuit, which also increases the size of the test vector.

Referring to FIG. 1, an integrated circuit with scan chains includes a combinational logic 20 and a scan test circuit. Combination logic 20 has various internal circuits (not shown) depending on the functionality of the integrated circuit. And the scan test circuit has scan chains for testing the internal circuits of the combinational logic, which are formed of shift registers 10, 12 according to the length of the scan chain. The shift registers 10 and 12 are terminals SI and Q for inputting and outputting scan data input / output data SCAN_IN and SCAN_OUT, respectively, and a selection terminal for inputting a selection signal SCAN_SEL for enabling an operation of an arbitrary shift register. SEL).

Referring to the scan test operation, the shift registers 10 and 12 first set the configuration data of corresponding internal circuits to a desired value to form a test vector. The test data (SCAN_IN) is serially received according to the test vector.

At this time, the selection signal SCAN_SEL is enabled so that the shift register can operate. The number of shifts is equal to the length of the scan chain. That is, the clock signal CLK corresponding to the length of the scan chain is received and shifted. After the shifting is finished, the selection signal SCAN_SEL is disabled and the clock signal CLK is operated in the normal mode. The scan test circuit then operates normally, and each register stores data according to the test result from the combinational logic of the integrated circuit. The fault coverage can be determined according to the data output from the corresponding internal circuits of the combinational logic.

Subsequently, as in the first operation, the shift register is operated to output the stored data in series through the output terminal. A scan test of the integrated circuit is performed each time this data is output against the expected value.

Therefore, when the scan test is performed by the above method, as many test vectors as the product of the number of internal circuits and the length of the scan chain are required.

In addition, inserting a test circuit during manufacturing to test a specific part of an integrated circuit is called BIST (Built In Self Test). One method of BIST is to use Multiple Input Signature Register (MISR). As shown in Figs. 2 to 3, when a bit string is serially input to a register chain formed by a specific generation polynomial G (x), a shift register provided with a predetermined number of bit strings is provided. Via. Each register value then stores specific values, which represent the characteristics of the bit strings passed up to that point. Therefore, if the bit strings are different, this property value is also different.

Referring to FIG. 2, another example scan test circuit includes a scan circuit 30 and a MISR 40. The scan circuit 30 has the same operation as that of the data input of the scan test circuit shown in FIG. That is, with scan chains and correspondingly formed of shift registers.

The MISR 40 receives data output in series from the scan circuit 30 and extracts characteristics of the data. At this time, the data extracted by extracting the characteristics of the data is called a signature. The signature is then used to receive output data from the scan circuit. The data before and after the input is different according to the arrangement characteristics of the input data order.

Specifically, the MISR 40 is composed of registers 41, 42, 43, and 45 and the XOR gate 44 by the order of the generated polynomial G (x), as shown in FIG.

Accordingly, the data output from the MISR 40 has the number of patterns ^{equal to} two ^orders of magnitude (two ^orders ). For example, the MISR 40 of FIG. 3 is a case where the generated polynomial is G (x) = X ⁴ + X ³ +1.

Accordingly, the MISR 40 forms serial output data as short signature data (SIGNATURE), and performs only a scan test by comparing only the data during the scan test. Therefore, the length of the test vector is shorter than that of the conventional scan test operation, and the test can be made easier.

However, the above-described scan test methods may generate a specific internal circuit having a low coverage corresponding to a specific circuit inside the integrated circuit. In addition, since the insertion of the MISR circuit occupies an area on the integrated circuit, a problem arises in that the size of the entire integrated circuit is increased.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and to provide an apparatus and method for implementing a test circuit by using an interface between a CRC circuit and a microcontroller of an integrated circuit.

1 is a block diagram showing the configuration of a typical scan test circuit;

2 is a block diagram showing a configuration of a scan test circuit using a general MISR;

3 is a block diagram showing the configuration of the MISR shown in FIG. 2;

4 is a block diagram showing a peripheral configuration of a USB core for performing a scan test using a CRC circuit according to the present invention;

5 is a block diagram showing the configuration of the CRC5 circuit shown in FIG. 4;

6 is a block diagram showing the configuration of the CRC16 circuit shown in FIG. 4; And

7 is a flowchart illustrating a procedure of performing a scan test of a USB core using a CRC circuit according to the present invention.

Explanation of symbols on the main parts of the drawings

100: USB core 110: specific internal circuit

120: first multiplexer 130: second multiplexer

140: first CRC circuit 160: second CRC circuit

180: third multiplexer 190; Second multiplexer

According to an aspect of the present invention for achieving the above object, in a test circuit for monitoring a specific internal circuit of the integrated circuit, connected to a microcontroller for monitoring an integrated circuit having a plurality of CRC circuits: A first / second input signal that initiates operation of the activated test mode in response to a test activation signal for monitoring the particular internal circuit and a first receiving third / fourth input signals from the particular internal circuit respectively; A second multiplexer; First and second test circuits which receive signals output from the first / second multiplexer and internally process them and generate first / second signature signals corresponding to the first to fourth input signals; A third multiplexer which receives the first and second signature signals and a specific register address from the microcontroller, and selects and outputs one of the first and second signature signals; And a fourth multiplexer which receives the first or the second signature signal from the third multiplexer and outputs test data according to the test mode in response to the test activation signal.

In a preferred embodiment of this aspect, the test circuit of the integrated circuit is a circuit for testing a universal serial bus core.

In a preferred embodiment of this aspect, the first / second test circuit comprises: registers of an order of a predetermined generation polynomial for the test mode; Logic gates provided at first and third register input terminals of the register; A fifth / sixth multiplexer which receives the first / second input signal and the output signal of the registers and outputs the first / second signature signal in response to a control signal controlling the output of the test circuit. do.

The first and second test circuits include: registers of an order of a predetermined generation polynomial for the test mode; One of the registers includes logic gates provided at first and third register input terminals.

In a preferred embodiment of this feature, the first and second test circuits are provided as redundant cyclic check circuits.

According to another aspect of the present invention for achieving the above object, it is connected with a microcontroller to test a specific internal circuit of an integrated circuit having a first and a second CRC circuit, and under the control of the microcontroller the specific internal CLAIMS 1. A method for monitoring circuitry, comprising: initializing the particular internal circuitry; Activating a test mode for testing the particular internal circuit from the microcontroller; Operating the particular internal circuit in response to the activated test mode; Receiving a specific register address from the microcontroller and selecting one of the first or second CRC circuits; The integrated circuit may be monitored by receiving the signature signal of the selected first or second CRC circuit and outputting test data generated by the test mode.

Therefore, according to the present invention, in order to monitor a specific internal circuit of the integrated circuit, the test mode is performed using the CRC circuit, and the output data is monitored.

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 illustrates a peripheral circuit configuration of a USB core for monitoring according to the present invention. It is connected to a microcontroller for monitoring a USB core having a plurality of CRC circuits, and includes an interface circuit for monitoring a specific internal circuit of the USB core.

Referring to the drawings, the USB core 100 includes a CRC5 circuit 140 and a CRC16 circuit 160. The USB core 100 is composed of a combination circuit having a plurality of specific internal circuits 110. In addition, the specific internal circuits 110 include a plurality of nodes (eg, node 1, node 2, etc.) for important functions.

The CRC5 circuit 140 and the CRC16 circuit 160 are cyclic redundancy checking circuits, and the CRC5 circuit 140 is configured by a generated polynomial G (X) = X ⁵ + X ² +1. The CRC16 circuit 160 is constructed by a generation polynomial G (X) = X ¹⁶ + X ¹⁵ + X ² +1.

In addition, the interface circuit includes a plurality of multiplexers 120, 130, 180, and 190 between a microcontroller (not shown) for controlling a test mode and a specific internal circuit 110 of the USB core 100. It is provided. The microcontroller is controlled to operate the test mode of the specific internal circuit.

The first multiplexer 120 and the second multiplexer 130 initiate operation of the activated test mode in response to a test activation signal test_mode for monitoring the specific internal circuit 110 from the microcontroller. The third and fourth input signals are respectively received from the first (CRC5_in) / second input signal (CRC16_in) and the corresponding nodes (node1, node2) of the specific internal circuit.

The CRC5 circuit 140 and the CRC16 circuit 160 receive signals output from the first 120 / second multiplexer 130, process them internally, and apply the signals to the first to fourth input signals. Generate a corresponding first / second signature signal. If the test mode is not in the test mode, the CRC5 circuit 140 and the CRC16 circuit 160 each perform an original corresponding function to generate output signals functions 1 and 2.

The third multiplexer 180 receives the first and second signature signals and a specific register address from the microcontroller, and selects and outputs one of the first or second signature signals.

The fourth multiplexer receives the first or second signature signal from the third multiplexer 180 and outputs test data Data_out according to the test mode in response to the test activation signal test_mode.

Specifically, referring to FIG. 5, the CRC5 circuit 140 includes as many registers as the order of the generated polynomial. That is, five registers 142 to 150 are provided by the fifth order polynomial. The first and second XOR gates 154 and 156 and the fifth multiplexer 152 provided in the input terminal D of the first register 142 and the third register 146 among the registers 142 to 150. ).

Therefore, when the test mode is activated, the registers 142 to 150 receive the input signal CRC5_in and store data by the test therein, and the fifth multiplexer 172 outputs the CRC5 circuit 140. The first signature is output in response to the control signal CRC_OUT_CTRL for controlling.

Referring to FIG. 6, the CRC16 circuit 160 includes as many registers 162 to 170 as the order of the generated polynomial. That is, 16 registers 162 to 170 are provided by the 16th order polynomial. The third and fourth XOR gates 174 and 176 and the sixth multiplexer 172 provided at the input terminal D of the first register 162 and the third register 166 among the registers 162 to 170. ). And the operation of these registers 162-170 is the same as their respective operation of the CRC5 circuit 140.

Therefore, in the test mode of the USB core 100, the CRC circuits 140 and 160 are used as the MISR to test a specific internal circuit 110 of the USB core 100 to obtain a signature. When a certain time elapses, the specific internal circuit 110 of the USB core 100 may be monitored by outputting test data through the interface circuit of the microcontroller.

7 is then connected with a microcontroller (not shown) to test the specific internal circuitry 110 of the USB core 100 having the CRC5 circuit 140 and the CRC16 circuit 160 and control of the microcontroller. The procedure for monitoring the specific internal circuit 110 is shown. This procedure shows a program in which the microcontroller is executed.

Referring to the drawing, in step S200, a reset signal is applied to the USB core 100 to initialize the specific internal circuit 110. In operation S210, the test mode for testing the specific internal circuit 110 is activated from the microcontroller. That is, a test activation signal test_mode is output to the first, second, and fourth multiplexers 120, 130, and 190.

In operation S220, the specific internal circuit 110 is operated for a predetermined time corresponding to the activated test mode. In operation S230, a specific register address (select) is output from the microcontroller to the third multiplexer 180, and the received third multiplexer 180 is either the CRC5 circuit 140 or the CRC16 circuit 160. Choose one. That is, the register address (select) is a signal for controlling to select one of the CRC5 circuit 140 and the CRC16 circuit 160.

In operation S240, the signature signal of the selected CRC5 circuit 140 or the CRC16 circuit 160 may be received and output test data according to the test mode operation, thereby monitoring a specific internal circuit of the USB core.

As described above, the present invention can broaden the application range of the scan design when a plurality of combination circuits provided in the USB core are performed by performing a test mode using the CRC circuits provided in the USB core. By selecting a node of critical function and testing it with a microcontroller, specific internal circuitry can be monitored.

Claims (5)

A test circuit for monitoring a specific internal circuit of the integrated circuit, the test circuit being connected to a microcontroller for monitoring an integrated circuit having a plurality of CRC circuits: A first / second input signal that initiates operation of the activated test mode in response to a test activation signal for monitoring the particular internal circuit and a first receiving third / fourth input signals from the particular internal circuit respectively; A second multiplexer; First and second test circuits which receive signals output from the first / second multiplexer and internally process them and generate first / second signature signals corresponding to the first to fourth input signals; A third multiplexer which receives the first and second signature signals and a specific register address from the microcontroller, and selects and outputs one of the first and second signature signals; And a fourth multiplexer which receives the first or second signature signal from the third multiplexer and outputs test data in the test mode in response to the test activation signal. The method of claim 1, And the test circuit of the integrated circuit is a circuit for testing a universal serial bus core. The method of claim 1, The first / second test circuit is: As many registers as the order of a predetermined polynomial for the test mode; Logic gates provided at first and third register input terminals of the register; A fifth / sixth multiplexer which receives the first / second input signal and the output signal of the registers and outputs the first / second signature signal in response to a control signal controlling the output of the test circuit. An integrated circuit test circuit. The method according to claim 1 or 3, And the first and second test circuits are provided as a cyclic redundancy circuit (CRC). A method for monitoring a particular internal circuit connected with a microcontroller for testing a specific internal circuit of an integrated circuit having a first and a second CRC circuit, the control of the microcontroller being: Initializing the specific internal circuitry; Activating a test mode for testing the particular internal circuit from the microcontroller; Operating the particular internal circuit in response to the activated test mode; Receiving a specific register address from the microcontroller and selecting one of the first or second CRC circuits; And receiving the signature signal of the selected first or second CRC circuit and outputting test data by operating the test mode to monitor the integrated circuit.