KR20000033908A - Semiconductor memory device with static burn-in test circuit - Google Patents

Abstract

PURPOSE: A semiconductor memory device with static burn-in test circuit is provided to supply a stress voltage of a cell by adapting a static burn-in test circuit to multi-bit flash memory device and to enable a high voltage supply part to operate stably by separating the high voltage supply part in normal operation in order to increase the credit of element. CONSTITUTION: A semiconductor memory device with static burn-in test circuit comprises a cell array part which includes a plurality of cells, a high voltage supply part which supplies high voltage when reading, programming and erasing cells, an address buffer and n precharge part which receives and buffers an external address and precharges bit line, a low decode part which controls word line of the cell array part according to address outputted from the address buffer and precharge part, a column decode part which controls column gate and sense amplifier according to the address buffer and precharge part, a data input/output buffer part which connects a data of cell with the outside when programming and reading cells and a static burn-in test part which provides a control voltage to the low decode part in the static burn-in test.

Description

Semiconductor memory device with static burn-in test circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, a static burn-in test circuit is constructed so that a static burn-in test circuit suitable for causing external power to be applied directly to a word line during static burn-in may be applied. A flash memory device having an in test circuit.

Hereinafter, a semiconductor memory device according to the related art will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a flash memory device according to the related art.

As shown in FIG. 1, the cell array unit 11, the high voltage supply unit 12 for supplying a high voltage at the time of read, program and erase of a cell, and an address input from the outside An address buffer and precharge unit 13 to receive and buffer a row decoder 14 to control a word line of the cell array unit 11 by receiving an address output from the address buffer and precharge unit 13. ) And a column decoder unit 17 which receives an address output from the address buffer and the precharge unit 13 and controls the Y-gate 15 and the sense amplifier 16 of the cell array unit 11. And a data input / output buffer unit 18 for programming the data of the cell or connecting to the outside at the time of reading.

The row decoder 14 receives the word line control voltages VWL and VSGY and the erase line control voltage VES from the high voltage supply unit 12 for programming and erasing the cell.

The column decoder unit 17 receives the VPD voltage from the high voltage supply unit 12 and applies the program voltage to the drain side of the cell.

2 is a cross-sectional view showing a general flash memory cell.

2 shows a structure of a flash memory cell using three-layer polycrystalline silicon, in which the first layer of polycrystalline silicon forms a floating gate 21, the second layer of polycrystalline silicon forms an erase gate 22, and a third Layer polycrystalline silicon forms the control gate 23.

The erase gate 22 is wired perpendicularly to the control gate 23, the floating gate 21 is wired to the drain side, and a select transistor is formed on the source side as the gate of the third layer of polycrystalline silicon.

In general, flash memory cells using three-layer polycrystalline silicon use hot electron injection, which is the same as the conventional ultraviolet erasing type, and use field emission due to the tunnel effect during erasing.

When programming to a memory cell, applying 8V to drain, 0V to source, and 12V to control gate, a high electric field is formed from source to drain, which has high energy in the vicinity of the drain region, and becomes a so-called hot electron, crossing the energy barrier of the oxide film. Electrons are injected into the floating gate.

This increases the threshold voltage of the cell. At this time, 3V is applied to the erase gate to alleviate voltage stress.

Such a conventional flash memory device realizes a high speed program and a high speed erase by constructing a high voltage generator which is a booster circuit during program and erase.

However, the above conventional flash memory device has the following problems.

Multibit, low-power products require significantly higher wordline control voltages at read time.

Therefore, during the static burn-in test, a voltage higher than the voltage applied to the word line should be applied for the charge gain stress test of the cell. The use of a negative electrode causes damage to the high voltage supply, and also increases the amount of leakage current, resulting in a problem in which the desired voltage level is not properly supplied.

In other words, junction leakage occurs frequently at high temperatures. Especially, the word line control voltage is a source voltage of the word line driver, so there is a large junction. The junction of the junction exceeds the pump supply capability of the high voltage supply. In this case, the stress voltage of the desired word line cannot be applied.

The present invention has been made to solve the above problems, it is possible to supply a stress voltage of the cell by applying a static burn-in test circuit to a multi-bit flash memory device, and to separate the high voltage supply in use during normal operation Accordingly, an object of the present invention is to provide a semiconductor memory device having a static burn-in test circuit that enables stable operation of a high voltage supply unit and improves device reliability.

1 is a block diagram of a flash memory device according to the prior art

2 is a cross-sectional view showing a general flash memory cell

3 is a block diagram illustrating a semiconductor memory device including the static burn-in test circuit of the present invention.

4 is a detailed circuit diagram of the static burn-in test circuit of FIG. 3.

5 is an operation timing diagram of the static burn-in test circuit of the present invention.

Explanation of symbols for main parts of the drawings

31 cell array unit 31a static burn-in voltage control unit

31b: local pump part 31c: voltage clamp part

31d: Word line control voltage connection 32: High voltage supply

33: address buffer and precharge section 34: row decoder section

35: Y-gate 36: sense amplifier

37: column decoder section 38: data input / output buffer section

39: static burn-in test unit

A semiconductor memory device having a static burn-in test circuit according to the present invention for achieving the above object includes a cell array unit comprising a plurality of cells, read, program, and erase of a cell. A high voltage supply unit for supplying a high voltage, an address buffer and precharge unit for receiving and buffering an external address and precharging a bit line, and a word line of a cell array unit according to an address output from the address buffer and precharge unit. A row decoder section for controlling the column gate section for controlling a column gate (Y-Gate) and a sense amplifier of a cell according to the addresses output from the address buffer and the precharge section; A data input / output buffer unit to be connected and a control voltage (VWL, VSGY) are provided to the row decoder unit during a static burn-in test. It characterized in that the unit comprises a test-table tick time.

Hereinafter, a semiconductor memory device having a static burn-in test circuit of the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a block diagram illustrating a semiconductor memory device including the static burn-in test circuit of the present invention, and FIG. 4 is a detailed circuit diagram of the static burn-in test circuit of FIG. 3.

First, as shown in FIG. 3, the cell array unit 31, the high voltage supply unit 32 for supplying a high voltage during read, program, and erase of the cell, and an external address A row for controlling the word line of the cell array unit 31 according to the address buffer and precharge unit 33 for receiving and buffering the bit line and precharging the bit line, and the address output from the address buffer and precharge unit 33. The column decoder unit 37 for controlling the column gate (Y-Gate) 35 and the sense amplifier 36 of the cell according to the decoder unit 34 and the addresses output from the address buffer and the precharge unit 33. And a control voltage (VWL, VSGY) to the data input / output buffer unit 38 for connecting the data of the cell to the outside during programming or reading, and the row decoder unit 34 during the static burn-in test. Static burn-in test unit 39 is configured to include.

According to such a configuration, the control voltage for controlling the low decoder unit 34 is output from the high voltage supply unit even during the static burn-in test, but in the present invention, the static burn-in test unit 39 is provided separately. Therefore, during the static burn-in test, the static burn-in test unit 39 provides the control voltage to the row decoder unit 34 instead of the high voltage supply unit 32.

The static burn-in test circuit according to the semiconductor memory device including the static burn-in test circuit of the present invention will be described in detail as follows.

4 is a detailed configuration diagram of the static burn-in test circuit according to the present invention. The static burn-in test voltage control unit 39a, the local pump unit 39b, the voltage clamp unit 39c, and the word line are shown in FIG. It consists of the control voltage connection part 39d.

Here, the static burn-in test voltage control unit 39a includes a first inverter INV1 for inverting an applied TWEPB signal, a first logic element 41 for logically performing an applied TWLST signal, and a TWLSTP signal. And a second inverter INV2 for inverting the output of the first logic element 31, a second logic element for inputting and outputting the output of the first inverter INV1 and the output of the second inverter INV2. An IOPAD signal serially connected to an output terminal of the first transistor PM1 and a first transistor PM1 selectively outputting a power supply voltage according to an output signal of the second logic element 41a And a third transistor NM1 connected between an output terminal and a ground terminal of the second transistor PM2 and whose operating state is determined according to the IOPAD signal. .

Here, the first and second transistors PM1 and PM2 are PMOS transistors, and the third transistor NM1 is an NMOS transistor.

The local pump unit 39b includes a third inverter INV3 connected to an output terminal of the second transistor PM2 of the static burn-in voltage control unit 39a, and an output of the second logic element 31a. A fourth transistor NM2 for selectively switching the ground voltage to an input terminal of the third inverter INV3 by operating the signal, and a fifth switch for selectively switching the ground voltage according to an output signal of the third inverter INV3. The transistor NM3, the sixth transistor NM4 that is always on by the power supply voltage VDD and outputs a ground voltage applied through the fifth transistor NM3, and a source is supplied to VCCTPAD. A seventh transistor PM3 connected and operated by an output signal of the sixth transistor NM4 to output the VCCTPAD signal, and an eighth transistor operated by a VCCTPAD signal output through the seventh transistor PM3 PM4 and the seventh track A fourth inverter connected to an output terminal of the jitter PM3 and inverting an output signal of the ninth transistor NM5 and the third inverter INV3 which are always kept on by the power supply voltage VDD. (INV4), a tenth transistor NM6 connected to an output terminal of the ninth transistor NM5 and controlled by an output signal of the fourth inverter INV4, and a source connected to the VCCTPAD, and the seventh transistor. An eleventh transistor PM5 controlled by the output signal of the PM3 and a twelfth transistor connected to the drain of the eleventh transistor PM5 and always kept on by the power supply voltage VDD. NM7, a thirteenth transistor NM8 having a drain connected to the drain of the twelfth transistor NM7 and a source connected to the ground terminal VSS, and controlled by an output signal of the seventh transistor PM3; The source is connected to the power supply voltage (VDD) terminal and the gate A fourteenth transistor HNM1 connected in common with the source, a fifteenth transistor HNM2 controlled by an output signal of the fourteenth transistor HNM1, a drain of the fourteenth transistor HNM2, and the eleventh transistor; The first MOS capacitor MC1 connected between the drain of the transistor PM5, the sixteenth transistor HNM3 having a gate and a source connected to the drain of the fifteenth transistor HNM2 in common, and the fifteenth transistor HNM2. A second MOS capacitor MC2 connected between the drain of the transistor and the drain of the eleventh transistor PM5, the seventeenth transistor HNM4 having a gate and a source connected to the drain of the sixteenth transistor HNM3 in common, and The third MOS capacitor MC3 is connected between the drain of the sixteenth transistor HNM3 and the drain of the seventh transistor PM3.

Here, the seventh, eighth transistors PM3 and PM4 and the eleventh transistor PM5 are PMOS transistors, and the fourteenth, fifteenth, sixteenth, and seventeenth transistors HNM1, HNM2,

HNM3 and HNM4) are high voltage NMOS transistors.

Subsequently, the voltage clamp unit 39c includes a plurality of high voltage NMOS transistors HNM5, HNM6, and HNM7 connected between the output terminal of the seventeenth transistor HNM4 and the VCCTPAD.

Subsequently, the word line control voltage connection unit 39d is controlled by the voltage at the node A point, and the high voltage transistor HNM8 selectively outputs the control voltage VWL to the row decoder unit 34, and the node A point. And a high voltage transistor HNM9 that is controlled by a voltage of and outputs a control voltage VSGY to the row decoder 34.

A high voltage NMOS transistor (HNM10) is further configured to control the voltage at node A by selectively switching the clamped voltage to a ground terminal.

The operation timing diagram of the static burn-in test circuit configured as described above is shown in FIG. 5.

Referring to Figure 5 describes the operation of the static burn-in test circuit of the present invention.

As shown in Fig. 5, in the static burn-in mode, the TWLST and TWLSTP signals become high level, and the TWEPB signals become low level.

Thereafter, a periodic clock pulse is applied to the IOPAD, and the VCCTPAD, which is an externally applied voltage, applies a charge gain stress voltage of the cell.

Therefore, the local pump unit 39c operates so that the voltage at the node A becomes a voltage sufficient to output the charge gain stress voltage to the word line control voltages VWL and VSGY of the row decoder unit 34.

That is, the 9V charge gain stress voltage applied to the IOPAD is output to the word line control voltages VWL and VSGY of the row decoder unit 34 by the voltage 13V at the node A point.

Therefore, during the static burn-in test, the static burn-in test circuit unit can supply the word line control voltage to the row decoder unit 34.

On the other hand, as shown in the figure, a sufficient voltage (13V) is made at the node A point, the process of outputting the word line control voltage (VWL, VSGY) by the voltage of the node A point.

As described above, the semiconductor memory device having the static burn-in test circuit of the present invention has the following effects.

When the static burn-in test circuit is applied to the multi-bit flash memory chip, it can supply the stress voltage of the stable cell, and it can be used separately from the high voltage circuit used in the normal operation to ensure the stable operation of the high voltage circuit. The reliability of programming, erasing operation can be improved.

Claims (7)

A cell array unit comprising a plurality of cells, A high voltage supply unit for supplying a high voltage at the time of reading, programming, and erasing the cell; An address buffer and precharge unit for receiving and buffering an external address and precharging a bit line; A row decoder unit controlling a word line of a cell array unit according to an address output from the address buffer and the precharge unit; A column decoder to control a column gate (Y-Gate) and a sense amplifier of a cell according to the address output from the address buffer and the precharge unit; A data input / output buffer unit for connecting data of a cell to an external device during programming or reading; And a static burn-in test circuit for providing a control voltage (VWL, VSGY) to the row decoder unit during a static burn-in test. The static burn-in test unit of claim 1, wherein the static burn-in test unit controls the test voltage in the static burn-in mode, and a local pump that pumps the test voltage to a sufficiently high voltage. And a voltage clamp part for clamping the voltage applied to the VCCTPAD to a predetermined voltage, and a word line control voltage connection part for selectively transferring the pumped voltage to the word line. A semiconductor memory device having a. 3. The static burn-in test voltage control unit of claim 2, wherein the static burn-in test voltage control unit comprises a first inverter for inverting a TWEPB signal, a first logic element for logic operation of an applied TWLST signal and a TWLSTP signal, and an output of the first logic element. A second inverter for inverting, a second logic element for inputting and logically performing an output of the first inverter and an output of the second inverter, and a first for selectively outputting a power supply voltage according to an output signal of the second logic element A second transistor connected in series with an output terminal of the first transistor and having an operating state determined according to an input IOPAD signal, and connected between an output terminal and a ground terminal of the second transistor and operating states according to the IOPAD signal. A semiconductor memory device having a static burn-in test circuit comprising a third transistor (NM1) to be determined. 4. The semiconductor memory device according to claim 3, wherein the first and second transistors are PMOS transistors, and the third transistors are NMOS transistors. 4. The semiconductor memory device according to claim 3, wherein the first and second logic elements are NAND gates. The input terminal of the third inverter of claim 2, wherein the local pump unit operates a third inverter connected to an output terminal of the second transistor of the static burn-in voltage control unit and an output signal of the second logic device. A fourth transistor for selectively switching to a fifth transistor, a fifth transistor for selectively switching a ground voltage according to an output signal of the third inverter, and a power supply voltage VDD to maintain an on state at all times. A seventh transistor connected to a sixth transistor for outputting a ground voltage applied through the transistor and operated by an output signal of the sixth transistor to output the VCCTPAD signal, and a VCCTPAD signal output through the seventh transistor It is connected to an eighth transistor and an output terminal of the seventh transistor, and is always in an on state by a power supply voltage VDD. A ninth transistor, a fourth inverter for inverting the output signal of the third inverter, a tenth transistor connected to an output terminal of the ninth transistor and controlled by an output signal of the fourth inverter, and a source An eleventh transistor connected to the VCCTPAD and controlled by an output signal of the seventh transistor, a twelfth transistor connected to a drain of the eleventh transistor and always kept on by a power supply voltage VDD; A thirteenth transistor having a drain connected to a drain of the twelfth transistor, a source connected to a ground terminal VSS, controlled by an output signal of the seventh transistor, a source connected to a power supply voltage VDD, A fourteenth transistor having a gate connected to the source in common, a fifteenth transistor controlled by an output signal of the fourteenth transistor, A first MOS capacitor connected between the drain of the fourteenth transistor and the drain of the eleventh transistor, a sixteenth transistor having a gate and a source in common with the drain of the fifteenth transistor, a drain of the fifteenth transistor and the A second MOS capacitor connected between the drain of the eleventh transistor, a seventeenth transistor having a gate and a source connected to the drain of the sixteenth transistor in common, and a drain connected between the drain of the sixteenth transistor and the drain of the seventh transistor. A semiconductor memory device having a static burn-in test circuit comprising three MOS capacitors. The method of claim 6, wherein the fourteenth, fifteenth, sixteenth, and seventeenth transistors are high voltage NMOS transistors, and the seventh, eighth transistors are PMOS transistors, and the fourth, fifth, sixth, and seventh transistors. And the ninth, tenth, twelfth, and thirteenth transistors are NMOS transistors.