KR20000031595A - Automatic micro-tuning apparatus and method for vsb television - Google Patents

Abstract

PURPOSE: An automatic micro-tuning apparatus for VSB television is provided to store each compensation error of a tuning data in a memory by each channel, and apply the stored compensation error at the tuning of the corresponding channel, so that it can perform a rapid and stable tuning, and help a rapid carrier recovery in detecting waves of the high frequency signals transmitted to the digital television. CONSTITUTION: An automatic micro-tuning apparatus comprises a digital tuner(100), an SAW filter(200), an intermediate frequency wave detector(300), a phase error voltage detector(400), an A/D converter(500), a synchronizer & equalizer(600), a channel decoder(700), a microprocessor(800) and a memory(900). The digital tuner(100) supplies intermediate frequency signals by tuning the high frequency signals input through an antenna. The wave detector(300) generates detected baseband signals by tracing the high frequency carrier by using frequency error between a crystal oscillator and an internal voltage adjustment oscillator. The phase error voltage detector(400) detects the phase error voltage on the frequency of the crystal oscillator and the voltage adjustment oscillator in an intermediate frequency signal detection start and steady state mode.

Description

Automatic fine tuning apparatus and method of residual sideband type digital TV

The present invention relates to an apparatus and method for automatic fine tuning of a residual sideband type digital TV to help stable and fast carrier recovery and to stabilize signal characteristics in the detection of high frequency signals received by a VSB digital TV. The present invention relates to an automatic fine tuning apparatus and method for a residual sideband type digital TV which stores a correction error of tuning data in a memory for each channel and applies the correction error at the time of channel tuning to perform fast and stable tuning.

FIG. 1 is a channel selection circuit diagram of a conventional digital TV. As shown in FIG. 1, a high frequency carrier of a VSB modulated signal corresponding to tuning data is input from an antenna when inputting tuning data, and is generated by frequency converting the signal. A digital tuner 100 for outputting the intermediate frequency signal IF, a saw filter 200 for performing Nyquist filtering on the intermediate frequency signal IF output from the digital tuner 100, and a crystal in the initial mode After being locked in the oscillation frequency of the oscillator 330, after the stabilization time, the controller receives the input from the saw filter 200 in the normal mode and becomes a normal frequency PLL and locks the pilot signal of the intermediate frequency. An IF detector 300 that detects and outputs a baseband signal I, and an analog / digital converter 500 that quantizes the baseband signal I detected by the IF detector 300 to digital. In this case, the analog / digital converter 500 recovers the segment sync similar to the horizontal sync and the field sync similar to the vertical sync from the quantized data, and removes the ghost signal sequence using the sequential columns in the recovered field sync. A synchronization and equalizer unit 600, a channel decoder 700 for outputting a channel-decoded transport stream by decoding and deinterleaving on the segment sync and field sync and signal data output from the sync and equalizer unit 600, and each for channel selection. The microprocessor unit 800 controls the operation of the unit.

As shown in FIG. 2, the IF detector 300 receives an intermediate frequency output from the saw filter 200 and amplifies the amplifier to a predetermined level and outputs the amplifier 311 from the amplifier 311. IF switch 312 for selecting the intermediate frequency or the frequency oscillated from the crystal oscillator 330 according to the mode selection signal input from the microprocessor unit 800, and the oscillation frequency output from the voltage adjusting oscillator 321 The baseband component (I) of the positive side is mixed with the delayer 316 which receives the input by delaying the phase by 90 °, and the oscillation frequency delayed by the delayer 316 and the frequency output from the IF switch 312. A second mixer for generating a baseband component (Q) on the negative side by mixing a first mixer 314 for generating a) and an oscillation frequency of the voltage controlled oscillator 321 and a frequency output from the IF switch 312. A mixer 315 and the first mix A low pass filter 317 for low-pass filtering the baseband component I on the plus side output from 314, a limiter 318 for limiting an output level of the low pass filter 317, and the limiter 318. A third mixer 319 for synthesizing the phase error component by synthesizing the signal through the second mixer and the baseband component Q through the second mixer 315, and making the DC voltage adjustable by low-passing the phase error component. The amplifier according to the phase error low pass filter 320 for varying the frequency of the voltage adjusting oscillator 321 and the baseband component I of the positive side input from the synchronous and equalizer 600. It consists of an AGC adjustment unit 322 which performs IF AGC of the intermediate frequency gain of 311, and performs high frequency gain adjustment of the digital tuner 100 (RF AGC).

Looking at the prior art configured in this way in detail as follows.

When providing the tuning data corresponding to the channel from the microprocessor unit 800 during the channel search, the digital tuner 100 tunes the high frequency carrier of the VSB modulated signal corresponding to the tuning data, and frequency-converts the tuned signal. To generate an intermediate frequency signal IF and output it to the saw filter 200.

Here, the digital tuner 100 generally uses a double converted tuner to reduce interference with NTSC signals.

The intermediate frequency IF finally output from the digital tuner 100 has a center frequency of 44 MHz in total.

The intermediate frequency signal IF output from the digital tuner 100 provides a signal generated by Nyquist filtering by the saw filter 200 to the IF detector 300.

Then, if the mode selection signal is input from the microprocessor unit 800, the IF detector 300 performs intermediate frequency amplification and then detects the mode selection signal.

However, since the pilot frequency of the digitally modulated VSB signal in the digital tuner 100 is a suppressed fine carrier wave, in order to easily follow the frequency in the IF detector 300, a crystal oscillator 330 having the same frequency oscillation as the pilot frequency is first used. The input stage is switched to the crystal oscillator 330 so as to lock the frequency generated in the first stage.

At this time, the mode selection signal input from the microprocessor unit 800 is a start mode.

In the start mode, the IF detector 300 is locked to the oscillation frequency oscillated by the crystal oscillator 330 and after the stabilization time passes, the microprocessor unit 800 selects the mode corresponding to the normal mode. Output the signal.

Then, the IF detector 300 outputs the baseband signal I detected when it is locked to the pilot frequency of the intermediate frequency signal output from the saw filter 200 to the analog / digital converter 500. .

The baseband signal I has a symbol rate of about 10.76 M symbols / second.

The baseband signal I detected by the IF detector 300 is received by the analog / digital converter 500 and quantized digitally and provided to the synchronization and equalizer 600.

Accordingly, the synchronization and equalizer unit 600 may include a segment sync similar to a horizontal synchronization unit from the digital data provided by the analog / digital converter 500 under control provided from the microprocessor unit 800 through an IIC bus. To recover the field sink similar to the vertical synchronization, the ghost signal sequence is removed using the sequence string in the field sink.

Accordingly, the synchronization and equalizer unit 600 outputs the digital data, the segment sync and the field sync from which the ghost signal sequence is removed to the channel decoder 700.

Accordingly, the channel decoder 700 performs a channel decoding process including trellis decoding, deinterleaving, Reed-Solomon decoding, randomization removal, and the like on the sync and digital data output from the synchronization and equalizer unit 600. Output the stream.

Referring to the operation described above briefly once again, if the microprocessor unit 800 provides the tuning data for the channel to the digital tuner 100, the digital tuner 100 receives a high frequency signal input from the antenna The filter is output through the saw filter 200 to the IF detector 300.

Then, the IF detector 300 detects a desired IF signal from the high frequency signal, digitally quantizes through the analog / digital converter 500, and removes ghosts from the synchronization and equalizer 600, and the channel. The decoder 700 finally outputs the transport stream which has been subjected to channel decoding.

The channel is searched by repeating the above operation.

The detection operation of the IF detector 300 will be described in detail with reference to FIG. 2 as follows.

First, when the intermediate frequency signal IF of the saw filter 200 is input to the IF detector 300, the amplifier 311 of the IF detector 300 is amplified to a predetermined level and output to the IF switch 312. do.

As another input of the IF switch 312, a frequency corresponding to the pilot frequency of the intermediate frequency signal IF is input from the crystal oscillator 330.

In this case, when the microprocessor unit 800 gives a mode selection signal corresponding to the start mode, the IF switch 312 is switched to the crystal oscillator 330.

Therefore, the IF switch 312 provides the oscillation frequency oscillated from the crystal oscillator 330 to the first mixer 314 and the second mixer 315, respectively.

At this time, the voltage adjusted oscillator 321 outputs the initial oscillation frequency to the second mixer 315 and the delay unit 316, respectively.

Then, the delay unit 316 delays the initial oscillation frequency input from the voltage adjusting oscillator 321 by 90 degrees to provide the first mixer 314, and thus the first mixer 314 is a crystal oscillator. The oscillation frequency of 330 and the initial oscillation frequency of the voltage-regulated oscillator 321 are mixed by generating a baseband component (I) of the positive side by mixing the frequency of which the phase is delayed by 90 degrees, and the second mixer 315 is The oscillation frequency of the crystal oscillator 330 and the initial oscillation frequency of the voltage adjusted oscillator 321 are mixed to generate and output a baseband component Q on the negative side.

The voltage regulated oscillator 321 is configured to oscillate freely at an intermediate voltage, and when the 9V voltage is used, the initial oscillation is performed at 4.5V.

The baseband component (I) on the positive side is low-passed through the low pass filter 317, and is again provided to the third mixer 319 by removing the frequency exceeding a predetermined level through the limiter 318.

Then, the third mixer 319 mixes the baseband component Q of the negative side mixed in the second mixer 315 and the frequency input from the limiter 318 to obtain a phase error component to obtain a phase error low. Output to the pass filter 320.

The phase error component obtained above corresponds to the frequency error of the crystal oscillator 330 and the voltage adjusted oscillator 321.

Accordingly, the phase error low pass filter 320 provides the DC voltage obtained by filtering the phase error component received from the third mixer 319 to the voltage adjusting oscillator 321.

Then, the voltage adjusting oscillator 321 changes the oscillation frequency by the DC voltage received from the low pass filter 320 to approach the frequency of the crystal oscillator 330.

Since the oscillation frequency of the crystal oscillator 330 oscillates at the suppressed pilot carrier frequency, the oscillation frequency of the voltage regulated oscillator 321 approaches the pilot frequency in advance through this start mode.

When the stabilization time elapses while performing such an operation, the microprocessor unit 800 outputs a mode selection signal corresponding to the normal mode to the IF switch 312.

Then, the IF switch 312 is switched to the intermediate frequency signal output through the amplifier 311 and provided to the first mixer 314 and the second mixer 315, respectively.

At this time, the oscillation frequency close to the pilot frequency is generated by the voltage adjusting oscillator 321 to the second mixer 315 and the delay unit 316, respectively.

Accordingly, the retarder 316 is delayed by 90 degrees and outputted to the first mixer 314.

Accordingly, the first mixer 314 mixes the frequency obtained by delaying the phase of the oscillation frequency close to the pilot frequency of the voltage-regulated oscillator 321 by 90 degrees obtained by the digital tuner 100 and the saw filter 200. And outputs it as the positive side baseband component (I), and the second mixer 315 mixes the oscillation frequency close to the pilot frequency of the voltage adjusting oscillator 321 with the negative side baseband component (Q). And print it out.

Subsequently, as described above, the output I of the first mixer 314 passes through the low pass filter 317 and the limiter 318 to the baseband component Q on the negative side of the third mixer 319. ) And the phase error component is output to the low pass filter 320.

This phase error component corresponds to the pilot carrier frequency of the intermediate frequency signal input to the IF detector 300 and the frequency error of the voltage adjusting oscillator 321.

The frequency error is filtered to the low pass filter 320, and a DC voltage corresponding to the filtered frequency is provided to the voltage adjusting oscillator 321 to vary the oscillation frequency so that it is easily followed by a pilot carrier frequency to perform a PLL operation. The detected baseband signal I is output.

When the synchronization and equalizer 300 detects the level of the data converted by the analog / digital converter 500 and provides it to the AGC adjuster 322, the AGC adjuster 322 according to the input level of the amplifier ( The middle frequency gain IF AGC of 311) is adjusted, and the high frequency gain RF AGC of the digital filter 100 is adjusted.

However, in the prior art as described above, the PLL detection is effective when the intermediate frequency signal for the channel tuned through the tuner is divided into the start mode and the normal mode, but when the frequency error is large, the PLL lock is normally closed. If the time is long and severe, that is, if the error is out of the PLL's following range, the lock is lost and detection is not possible. Also, if there is a frequency error in the tuner, the intermediate frequency signal at the output stage is lost. Since the bands of the signal input to the Saw filter and the IF detector are distorted, not only accurate characteristics are generated, but also phase noise is generated.

Therefore, an object of the present invention for solving the conventional problems as described above is to obtain an error signal in the detection of the intermediate frequency signal during automatic channel search, and to perform fine tuning by fine-tuning the tuning data using the obtained error signal The present invention provides an apparatus and method for automatic fine tuning of a residual sideband type digital TV.

It is another object of the present invention to provide an automatic fine tuning apparatus and method for a residual sideband type digital TV which stores a correction error of tuning data in a memory for each channel and performs fast and accurate tuning with reference to this value during channel tuning. In providing.

1 is a channel selection circuit diagram of a conventional digital TV.

2 is a circuit diagram of an automatic fine tuning apparatus of a conventional residual sideband type digital TV.

Figure 3 is a circuit diagram of the automatic fine tuning device of the present invention residual sideband system digital TV.

4 is an operation flowchart for an automatic fine tuning method of the present invention residual sideband type digital TV.

5 is a frequency characteristic diagram according to the error of the intermediate frequency signal after tuning in FIG.

6 is a flowchart illustrating an example in which the corrected tuning data is applied when a channel change command is input.

*** Explanation of symbols for main parts of drawing ***

100: digital tuner 200: saw filter

300: IF detector 400: phase error voltage detector

410: DC amplifier 420: detection switch

500: A / D conversion unit 600: synchronization and equalizer unit

700: channel decoder 800: microprocessor unit

900: memory

In order to achieve the above object, the present invention tunes a high frequency signal input through an antenna in a digital tuner, and then detects a signal in an IF detector from a frequency-converted intermediate frequency signal and quantizes it digitally through an analog / digital converter. In the channel selection apparatus of the residual sideband digital TV which detects the synchronization through the synchronization and equalizer unit and the channel decoder and finally outputs the channel-decoded transport stream, the IF detector detects the start mode when the intermediate frequency signal is detected. In the normal mode, a tuning error is compared by comparing a phase error voltage detector for detecting phase error voltages with respect to the frequency of the crystal oscillator and the voltage adjusting oscillator, and a difference between the phase error voltage detected by the phase error voltage detector and a tuning error tolerance. To correct the tuning data It is characterized in that it is configured to further include a memory for storing tuning error data obtained from the microprocessor unit, the microprocessor unit to the channel address.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a circuit diagram of an automatic fine tuning apparatus of a residual sideband type digital TV according to the present invention. As shown in FIG. 3, a high frequency carrier of a VSB modulated signal corresponding to tuning data is input from an antenna when tuning data is input. Nyquist filtering is performed on the digital tuner 100 for outputting the intermediate frequency signal IF generated by frequency conversion of the signal and the intermediate frequency signal IF output from the digital tuner 100. After the soak filter 200 and the oscillation frequency of the crystal oscillator 330 are locked in the initial mode, the stabilization time passes and the input is received from the saw filter 200 in the normal mode, thereby becoming a normal frequency PLL. The IF detector 300 detects and outputs the baseband signal I that is locked to the pilot signal of the intermediate frequency, and the baseband signal I detected by the IF detector 300 is digital. Recovers the segment sync similar to the horizontal sync and the field sync similar to the vertical sync from the analog / digital converting unit 500 and the data quantized by the analog / digital converting unit 500. A synchronization and equalizer unit 600 which removes the ghost signal sequence using the sequence sequence within the channel, and outputs a transport stream decoded by decoding and deinterleaving the segment sync and field sync and signal data outputted from the sync and equalizer unit 600. A phase error voltage detector 400 for detecting a phase error voltage with respect to the frequencies of the crystal oscillator and the voltage adjusting oscillator in the channel decoder 700 and the IF detector 300 in the start mode and the normal mode when the intermediate frequency signal is detected. And tuning by comparing the difference between the phase error voltage detected by the phase error voltage detection unit 400 and the tuning error tolerance value. The microprocessor unit 800 is configured to obtain an error and correct the tuning data when searching for a channel, and the memory 900 stores the tuning error data obtained by the microprocessor unit 800 at a corresponding channel address.

The phase error voltage detector 400 controls the DC amplifier 410 and the microprocessor 800 to amplify the DC voltage corresponding to the phase error output from the IF detector 300 to a detectable level. According to the detection switch 420 for switching the voltage amplified by the DC amplifier 410 to the next stage and the voltage transferred through the detection switch 420 into digital data values. The analog / digital converter 430 outputs to the microprocessor 800 is configured.

Referring to the operation and effect of the present invention configured as described in detail as follows.

When the channel is first searched and the tuning data is provided from the microprocessor unit 800 to the digital tuner 100 in the channel up process, the tuning is performed by the digital tuner 100.

Then, the microprocessor unit 800 provides a mode selection signal corresponding to the starter mode to the IF switch 312 of the IF detector 300 so as to be switched to the crystal oscillator 330. (S1)

The IF switch 312 provides an oscillation frequency corresponding to the pilot frequency of the intermediate frequency signal IF from the crystal oscillator 330 to the first mixer 314 and the second mixer 315, respectively.

Then, the first mixer 314 of the delay 316 delayed by 90 degrees with respect to the oscillation frequency of the crystal oscillator 330 and the initial oscillation frequency of the voltage controlled oscillator 321 through the IF switch 312 The frequency is mixed and output as the baseband component (I) on the positive side, and the second mixer 315 mixes the oscillation frequency of the crystal oscillator 330 and the initial oscillation frequency of the voltage controlled oscillator 321 in a positive phase. To the baseband component Q on the negative side.

At this time, the voltage-regulated oscillator 321 is configured to freely oscillate at an intermediate voltage. For example, when the 9V voltage is used, the initial oscillation is performed at 4.5V. In other words, if there is no phase error, the phase error voltage of 4.5V will come out.

The baseband component I output from the first mixer 314 is a baseband component Q of the second mixer 315 in the third mixer 319 via the low pass filter 317 and the limiter 318. And the phase error component is output therefrom.

Here, the phase error component corresponds to the frequency error between the crystal oscillator 330 and the voltage adjusted oscillator 321.

The phase error component is filtered by the low-pass filter 320 for phase error, and is filtered to become an adjustable DC voltage, thereby approaching the frequency of the crystal oscillator 330 by varying the oscillation frequency of the voltage adjusting oscillator 321. .

In addition, the DC voltage output from the phase error low pass filter 320 is output to the DC amplifier 410 of the phase error voltage detector 400.

At this time, since the input resistance of the DC amplifier 410 is large, the influence on the PLL path of the IF detector 300 is minimized.

The DC amplifier 410 receives the DC voltage output from the phase error low pass filter 320 and amplifies the DC voltage to a predetermined level to provide the detection switch 420.

At this time, when the detection switch 420 is turned on in the microprocessor processor 800 (S2), the analog / digital converter 430 converts the DC voltage amplified by the DC amplifier 410 into a digital value to convert the micro signal into the micro. Provided to the processor 800.

Then, the microprocessor unit 800 reads the digital value of the DC voltage at this time, stores it in the internal register A (S3), and then turns off the detection switch 420 to block the PLL path.

The process so far is almost independent of the characteristics of each channel, so it may be performed only once in some cases.

After a slight stabilization time, the microprocessor unit 800 outputs a mode selection signal corresponding to the normal mode to the IF switch 312 (S5).

Then, the IF switch 312 is switched to the intermediate frequency signal output through the amplifier 311 and provided to the first mixer 314 and the second mixer 315, respectively.

At this time, the oscillation frequency close to the pilot frequency is generated by the voltage adjusting oscillator 321 to the second mixer 315 and the delay unit 316, respectively.

Accordingly, the retarder 316 is delayed by 90 degrees and outputted to the first mixer 314.

Accordingly, the first mixer 314 mixes the frequency obtained by delaying the phase of the oscillation frequency close to the pilot frequency of the voltage-regulated oscillator 321 by 90 degrees obtained by the digital tuner 100 and the saw filter 200. And outputs it as the positive side baseband component (I), and the second mixer 315 mixes the oscillation frequency close to the pilot frequency of the voltage adjusting oscillator 321 with the negative side baseband component (Q). And print it out.

The output I of the first mixer 314 is mixed with the baseband component Q on the negative side of the third mixer 319 through the low pass filter 317 and the limiter 318, and thus, the phase error component therefrom. The low pass filter 320 is output.

This phase error component corresponds to the pilot carrier frequency of the intermediate frequency signal input to the IF detector 300 and the frequency error of the voltage adjusting oscillator 321.

The frequency error is a DC voltage that is adjustable in the low pass filter 320, thereby changing the oscillation frequency of the voltage adjusting oscillator 321 to easily follow the frequency of the carrier, thereby performing a PLL operation, and detecting the detected baseband signal (I). Will be output.

At this time, the microprocessor 800 detects the presence of a synchronization signal, which can be known by reading the sync detection status register of the synchronization and equalizer 600 through the IIC bus.

As a result of the detection, if the synchronization signal does not exist, the microprocessor unit 800 proceeds to the start mode of step S1 again. If the synchronization signal exists, the microprocessor unit 800 turns on the detection switch 420 of the phase error voltage detector 400. (S7)

Then, the analog / digital converter 430 outputs the phase error voltage digital value output through the phase pass low pass filter 320 of the IF detector 300 and the DC amplifier 410 of the phase error voltage detector 400. Converted to and provided to the microprocessor unit 800.

Then, the microprocessor unit 800 reads the voltage provided by the analog / digital converter 430 and stores the voltage in the register B of the internal memory (S8).

After storing the voltage in this manner, the microprocessor unit 800 turns off the detection switch 420 to be cut off from the PLL path (S9).

Thereafter, the microprocessor unit 800 calculates a difference between voltages stored in the internal registers A and B and stores the difference in the register C.

Then, the value stored in the register C (hereinafter abbreviated as C) is compared with the tuning error tolerance value T set appropriately (S10).

As a result of the comparison, if the C value is larger than the tuning error tolerance value (T), it means that the actual pilot carrier frequency of the intermediate frequency signal is higher than the oscillation frequency of the crystal oscillator 330, and in this case is sent to the digital tuner 100. The tuning data is reduced by one step and output. (S11)

Then, the C value is reduced by the PLL path of the IF detector 300.

On the contrary, if the C value is smaller than the -T value, this means that the actual pilot carrier frequency of the intermediate frequency signal is lower than the oscillation frequency of the crystal oscillator 330. In this case, the tuning data sent to the digital tuner 100 is 1. Step up to output (S12)

Then, the C value is reduced by the PLL path of the IF detector 300.

The above process is repeated until the absolute value of C (C) becomes smaller than the value of T, and when C is smaller than T, it is within the tolerance so that the tuning error data is stored in memory ( And stored in the corresponding channel address (900). (S13)

The memory 900 uses EEPROM that can be read and written.

If the channel is not the last channel, all of the digital channels are stored while repeating the same operation as described above, and the tuning error data of the corresponding channel is stored.

If the above operation is repeated and the tuning error for the corresponding channel is stored in the memory 900 and the next channel is searched, as shown in FIG. 6, the microprocessor unit 800 is stored in the memory 900. The tuning data is corrected using the error, and the corrected tuning data is provided to the digital tuner 100 so that stable tuning is performed.

After all, when there is no error component as shown in Fig. 5 (a), it does not matter if the Saw filter 200 and the signal component is exactly matched to apply the Nyquist filter characteristics suitable for VSB, as shown in Fig. 5 (b) Likewise, when the frequency of the intermediate frequency signal at the output terminal of the digital tuner 100 is misaligned and mismatched with the saw filter 200, the distorted component of the signal is formed, and the tuning data is transmitted through the phase error voltage detector 400. By correcting, the signal is shifted to the intermediate frequency characteristic of FIG.

Therefore, the present invention has an effect that stable and fast tuning is achieved by automatically correcting the tuning data according to the error of the intermediate frequency signal for each channel.

Claims (5)

After tuning the high frequency signal input through the antenna, the digital tuner 100, which provides a frequency converted intermediate frequency signal through the saw filter 200, and using the frequency error of the crystal oscillator 100 and the internal voltage adjustment oscillator And the IF detector 300 outputs the detected baseband signal I by following the carrier of the high frequency signal, and digitally quantizes the detected signal through the analog / digital converter 500 and then synchronizes the signal. And a channel selection apparatus of a residual sideband digital TV which detects synchronization through an equalizer 600 and a channel decoder 700 and finally outputs a transport stream decoded by the IF detector. Phase error voltage detection unit for detecting the phase error voltage with respect to the frequency of the crystal oscillator and the voltage adjusting oscillator in the start mode and the normal mode when detecting the intermediate frequency signal ( 400 and the microprocessor unit 800 for comparing the difference between the phase error voltage detected by the phase error voltage detector 400 and the tuning error tolerance to obtain a tuning error and correcting the tuning data when searching for the channel; And a memory (900) for storing the tuning error data obtained by the microprocessor unit (800) at a corresponding channel address. The microprocessor unit of claim 1, wherein the phase error voltage detector 400 amplifies the DC voltage corresponding to the phase error output from the IF detector 300 to a detectable level. The detection switch 420 which is turned on or off under the control of 800 and switches the voltage amplified by the DC amplifier 410 to the next stage, and the voltage transmitted through the detection switch 420 is a digital data value. The automatic side-tuning device of the residual sideband type digital TV, characterized in that consisting of an analog / digital conversion unit 430 is converted to and output to the microprocessor unit 800. 2. The apparatus of claim 1, wherein the memory (900) is an EEPROM capable of reading and writing. In the start mode for detecting the presence or absence of the intermediate frequency signal during the channel search, the first step of storing the phase error voltage (A) corresponding to the frequency error of the crystal oscillator and the voltage adjusting oscillator, and in the normal mode after a predetermined stabilization time has elapsed. A second step of detecting the presence or absence of the synchronization signal; a third step of repeating the first step if the synchronization signal is not detected; and storing the phase error voltage B in the normal mode when the synchronization signal is detected; A fourth step of obtaining a difference (C = BA) with respect to the voltages obtained in the first and third steps, and comparing the voltage difference (C) and the preset tuning error tolerance value (T). And a sixth step of storing the tuning error in the case of a second channel, and a sixth step of storing the last channel by repeating the operations of the first to fifth steps. Automatic fine tuning is a method of vestigial sideband way digital TV. 5. The method of claim 4, wherein the fifth step includes the first step of reducing the tuning voltage by one step if the voltage difference C obtained in the fourth step is larger than the tuning error tolerance value T, and reducing the voltage difference. A second step of increasing the tuning data by one step if the difference C is smaller than the tuning error tolerance value (-T) to reduce the voltage difference, and the voltage difference C being smaller than the absolute value of the tuning error tolerance value. Or a third step of storing the tuning error at the corresponding channel address, if equal to the same.