KR20000027930A - Surface treatment method of conductive patterns for preventng oxidation - Google Patents
Surface treatment method of conductive patterns for preventng oxidation Download PDFInfo
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- KR20000027930A KR20000027930A KR1019980045975A KR19980045975A KR20000027930A KR 20000027930 A KR20000027930 A KR 20000027930A KR 1019980045975 A KR1019980045975 A KR 1019980045975A KR 19980045975 A KR19980045975 A KR 19980045975A KR 20000027930 A KR20000027930 A KR 20000027930A
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- conductive layer
- conductive pattern
- surface treatment
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- treatment method
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004381 surface treatment Methods 0.000 title claims abstract description 12
- 230000003647 oxidation Effects 0.000 title claims description 10
- 238000007254 oxidation reaction Methods 0.000 title claims description 10
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 8
- 239000010937 tungsten Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims abstract description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 4
- 238000011065 in-situ storage Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 4
- 230000003064 anti-oxidating effect Effects 0.000 abstract 1
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000035515 penetration Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910007991 Si-N Inorganic materials 0.000 description 1
- 229910006294 Si—N Inorganic materials 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 도전층 패턴 형성시 동시에 상기 도전층 패턴 주위에 질화막을 형성하므로서 토폴로지 결함(Topology Deformation)을 억제하고 안정적인 도전층 패턴을 형성할 수 있는 반도체 소자에서 산화방지를 위한 도전층 패턴의 표면처리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, in a semiconductor device capable of suppressing topology defects and forming a stable conductive layer pattern by forming a nitride film around the conductive layer pattern at the same time when the conductive layer pattern is formed. The present invention relates to a surface treatment method of a conductive layer pattern for preventing oxidation.
일반적으로 메모리 소자 공정에서 Cl2+ O2나 CF4가스를 사용하여 폴리실리콘, 텅스텐 실리사이드 또는 텅스텐으로 형성되는 도전층을 식각한다. 이후, 유전체막(ONO; oxide/nitride/oxide) 형성 공정과 BPSG 형성 공정을 실시한다. 이때 공정이 매우 고온에서 실시되고, 또한 반응 가스와 희생 산화막(native oxide) 또는 BPSG 형성 공정에 의한 불순물(impurity) 침투가 발생하게 한다. 따라서 도전층 패턴 표면이 산화되어 선 부피 팽창이나 이에 상응하는 스트레스를 받게 되어서 추후 공정에서 정의되는 캐패시터 등에 결함이 발생하게 된다.In general, Cl 2 + O 2 or CF 4 gas is used in a memory device process to etch a conductive layer formed of polysilicon, tungsten silicide or tungsten. After that, a dielectric film (ONO; oxide / nitride / oxide) forming process and a BPSG forming process are performed. At this time, the process is performed at a very high temperature, and also impurity penetration by the reactant gas and the sacrificial oxide or BPSG forming process occurs. Therefore, the surface of the conductive layer pattern is oxidized and subjected to linear volume expansion or corresponding stress, so that a defect occurs in a capacitor or the like defined in a later process.
BPSG에 의해 발생되는 문제는 ONO막에서 질화막 두께를 조절하여 불순물 침투를 방지할 수 있지만, 캐패시터 용량이 변하므로 두께 변화에 한계를 갖게 된다. 또한 ONO막 형성 공정중에 발생하는 산화 현상을 피하기 어렵게 되었다.The problem caused by BPSG can prevent impurity penetration by adjusting the thickness of the nitride film in the ONO film, but has a limitation in the thickness change because the capacitor capacity is changed. Moreover, it became difficult to avoid the oxidation phenomenon which occurs during the ONO film formation process.
따라서, 본 발명은 상기한 문제점을 해결하기 위해, 도전층 패턴 형성과 동시에 상기 도전층 패턴 주위에 질화막을 형성하여 토폴로지 결함을 억제하고 안정적인 도전층 패턴을 형성하므로서 소자의 신뢰성을 향상시킬 수 있는 반도체 소자에서 산화방지를 위한 도전층 패턴의 표면처리 방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problems, the present invention can form a nitride film around the conductive layer pattern simultaneously with the formation of the conductive layer pattern to suppress topology defects and to form a stable conductive layer pattern, thereby improving the reliability of the device. It is an object of the present invention to provide a surface treatment method of a conductive layer pattern for preventing oxidation in a device.
상기한 목적을 달성하기 위한 본 발명은 반도체 소자를 형성하기 위한 도전층이 제공되는 단계; 및 상기 도전층의 패터닝시 플라즈마 분위기의 챔버에 NH3가스를 주입하고, 이로 인하여 도전성 패턴 주위에 얇은 질화막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is a step of providing a conductive layer for forming a semiconductor device; And injecting NH 3 gas into the chamber in the plasma atmosphere during patterning of the conductive layer, thereby forming a thin nitride film around the conductive pattern.
도 1은 본 발명에 따른 반도체 소자에서 산화방지를 위한 도전층 패턴의 표면처리 방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a surface treatment method of a conductive layer pattern for preventing oxidation in a semiconductor device according to the present invention.
도 2(a) 및 도 2(b)는 도전층 패턴의 표면처리를 위한 메카니즘을 설명하기 위한 도면.2 (a) and 2 (b) are diagrams for explaining a mechanism for surface treatment of a conductive layer pattern.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
10 : 반도체 기판 11 : 폴리실리콘층(텅스텐층)10 semiconductor substrate 11 polysilicon layer (tungsten layer)
12 : 텅스텐 실리사이드층(텅스텐층)12: tungsten silicide layer (tungsten layer)
13 : 반사방지층 20 : 도전층 패턴13 antireflection layer 20 conductive layer pattern
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1은 본 발명에 따른 반도체 소자에서 산화방지를 위한 도전층 패턴의 표면처리 방법을 설명하기 위한 단면도이며, 도 2(a) 및 도 2(b)는 도전층 패턴의 표면처리를 위한 메카니즘을 설명하기 위한 도면이다.1 is a cross-sectional view illustrating a surface treatment method of a conductive layer pattern for preventing oxidation in a semiconductor device according to the present invention, and FIGS. 2 (a) and 2 (b) illustrate a mechanism for surface treatment of a conductive layer pattern. It is a figure for demonstrating.
종래의 반도체 소자의 도전층 패턴은 폴리실리콘이 주로 사용되었으며, 최근에는 텅스텐이나 텅스텐 실리사이드가 사용되고 있다. 이와 같은 구조는 도 1에 도시되었는데, 도 1은 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(10)상에 폴리실리콘층 또는 텅스텐층(11), 텅스텐 실리사이드 또는 텅스텐층(12) 및 반사방지층(13)을 순차적으로 형성하여 도전성 패턴(20)을 형성한 것을 나타낸다. 상기한 도전층 패턴(20)을 형성하기 위해서는 반응성 이온 식각(RIE; Reactiev Ion Etch) 장비에서 Cl2+ O2가스나 C2F6가스를 사용하여 식각하므로서 형성한다.Polysilicon is mainly used as a conductive layer pattern of a conventional semiconductor device, and recently, tungsten or tungsten silicide is used. Such a structure is shown in FIG. 1, which illustrates a polysilicon layer or tungsten layer 11, a tungsten silicide or tungsten layer 12 and reflection on a semiconductor substrate 10 on which various elements for forming a semiconductor element are formed. It shows that the electroconductive pattern 20 was formed by forming the prevention layer 13 sequentially. In order to form the conductive layer pattern 20, the conductive layer pattern 20 is formed by etching using a reactive ion etching (RIE; Reactiev Ion Etch) device using Cl 2 + O 2 gas or C 2 F 6 gas.
산화방지를 위한 도전성 패턴(20)의 표면처리는 도전성 패턴 형성시 사용되는 반응성 이온 식각 장비에 NH3가스라인을 설치하고, 인-시투(In-Situ) 방식으로 진행된다.Surface treatment of the conductive pattern 20 for preventing oxidation is carried out in an in-situ method by installing an NH 3 gas line in the reactive ion etching equipment used when forming the conductive pattern.
여기서, 도전성 패턴(20)의 표면처리의 메카니즘에 대해 언급한다.Here, the mechanism of surface treatment of the conductive pattern 20 is mentioned.
반응성 이온 식각에 의해 도전성 패턴이 형성될 때, NH3가스가 플라즈마 분위기의 챔버(chamber)에 계속 주입된다. 주입된 NH3는 플라즈마에 의하여 부분적으로 NH2기와 H 기(radical)로 분해되고, NH2기는 도 2(a)에 도시된 바와 같이 도전층 패턴의 표면과 반응하여 W-NH2나 Si-NH2를 형성한다. 이때, 도전층 패턴의 표면은 산화막과 결합된 상태, 또는 댕글링 본드(dangling bond; 결합되어 있지 않은 화학 결합 손) 상태로 존재한다. 산화막과 결합된 도전층 패턴은 플라즈마에 의해 NH2와 치환 반응이 일어나고, 댕글링 본드를 형성하고 있는 도전층 패턴은 NH2와 직접 빠르게 반응한다.When the conductive pattern is formed by reactive ion etching, NH 3 gas is continuously injected into the chamber of the plasma atmosphere. The injected NH 3 by a plasma is a partially NH 2 group and H group (radical) is decomposed into, NH 2 groups Figure 2 (a) to react with the surface of the conductive layer pattern, as shown in the W-NH 2 or Si- Forms NH 2 . At this time, the surface of the conductive layer pattern is present in the state of being bonded to the oxide film or in a dangling bond (unbonded chemical bond hand) state. The conductive layer pattern combined with the oxide film reacts with NH 2 by plasma, and the conductive layer pattern forming the dangling bond reacts directly with NH 2 quickly.
상기한 반응은 반응 시간이 길수록, NH3압력이 증가할수록, 챔버 온도가 높을수록, 플라즈마 전력이 높을수록 촉진된다. 뿐만 아니라, 도 2(b)에 도시된 바와 같이 NH2의 수소(H)가 NH2기와 반응하여 W-N이나 Si-N을 형성하여 얇은 질화막을 형성한다. 이 질화막은 후속 공정에서 불순물 확산방지막이나 산화방지막 역할을 하여 후속 공정을 안정적으로 실시할 수 있도록 한다.The reaction is promoted as the reaction time is longer, the NH 3 pressure is increased, the chamber temperature is higher, and the plasma power is higher. In addition, FIG. 2 (b) the hydrogen (H) of the NH 2 as shown in the NH 2 group and react to form a thin nitride film to form a WN or Si-N. This nitride film acts as an impurity diffusion preventing film or an antioxidant film in a subsequent process so that the subsequent process can be stably performed.
상술한 바와 같이, 본 발명에 의하면 전도성 패턴의 산화를 방지할 수 있으므로 후속 공정에 따른 부피 팽창이나 스트레스를 방지할 수 있어 금속배선이나 캐패시터 형성 등을 안정적으로 형성하는데 탁월한 효과가 있다.As described above, according to the present invention, since the oxidation of the conductive pattern can be prevented, it is possible to prevent volume expansion or stress caused by a subsequent process, and thus has an excellent effect of stably forming metal wiring or capacitor formation.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045975A KR20000027930A (en) | 1998-10-29 | 1998-10-29 | Surface treatment method of conductive patterns for preventng oxidation |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980045975A KR20000027930A (en) | 1998-10-29 | 1998-10-29 | Surface treatment method of conductive patterns for preventng oxidation |
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| KR20000027930A true KR20000027930A (en) | 2000-05-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10410878B2 (en) | 2017-10-31 | 2019-09-10 | American Air Liquide, Inc. | Hydrofluorocarbons containing —NH2 functional group for 3D NAND and DRAM applications |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10410878B2 (en) | 2017-10-31 | 2019-09-10 | American Air Liquide, Inc. | Hydrofluorocarbons containing —NH2 functional group for 3D NAND and DRAM applications |
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