KR20000027650A - Method for manufacturing semiconductor devices - Google Patents
Method for manufacturing semiconductor devices Download PDFInfo
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- KR20000027650A KR20000027650A KR1019980045607A KR19980045607A KR20000027650A KR 20000027650 A KR20000027650 A KR 20000027650A KR 1019980045607 A KR1019980045607 A KR 1019980045607A KR 19980045607 A KR19980045607 A KR 19980045607A KR 20000027650 A KR20000027650 A KR 20000027650A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 비트라인(Bitline)을 소자분리 영역 형성시에 같이 형성함으로써 폴디드 비트라인 (Folded Bitline)구조를 만들어 소자의 제조공정 단계를 줄일 수 있고, 전체적인 토폴로지(Topology)를 낮춰 후속 공정의 난이도도 줄임으로써 반도체 소자의 제조공정 수율을 향상시킬 수 있는 고집적 반도체 기억 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, by forming a bitline together at the time of forming a device isolation region, a folded bitline structure can be formed to reduce the manufacturing process steps of the device. The present invention relates to a method for manufacturing a highly integrated semiconductor memory device capable of improving the manufacturing process yield of a semiconductor device by reducing the topology and reducing the difficulty of subsequent processes.
일반적으로 반도체 기억소자가 고집적화되어 그 크기가 작아짐에 따라, 보다 많은 집적을 용이하게 하기위한 여러 가지 수단이 강구되고 있다. 이에 따른 여러 가지 방안중에서 가장 간단한 것은 소자의 크기를 줄이는 것이다. 그런데, 소자의 크기를 줄여주는 데에는 공정장비에 따른 한계가 있다.In general, as semiconductor memory devices are highly integrated and their sizes are reduced, various means for facilitating more integration have been devised. The simplest of the various approaches is to reduce the size of the device. However, there is a limit to the process equipment in reducing the size of the device.
상기 한계를 극복하기 위한 방법중의 하나는 사용하는 층(layer)의 수를 늘리는 방법이다. 이러한 방법의 대표적인 것으로 폴디드비트라인 구조의 디램(dram) 셀 (Cell)에서 비트라인 콘택을 형성하는 부분을 확보하는 것을 예로 들 수 있다. 소자활성영역(Active area)을 하나의 직사각형 형태로 형성하지 않고 Z형이나 T형 형태로 형성하여 비트라인 콘택 형성 영역을 확보하는 것은, 소자가 작아짐에 따라 끝부분의 형태가 원래의 설계대로 형성되지 않음으로 해서 문제가 있다.One way to overcome this limitation is to increase the number of layers used. A representative example of such a method is to secure a portion forming a bit line contact in a DRAM cell of a folded bit line structure. To secure the bitline contact formation area by forming the Z-type or T-type without forming the active area in one rectangular shape, the shape of the end portion is formed as the original design as the device becomes smaller. If not, there is a problem.
또 하나의 해결책으로 사용할 수 있는 방안으로, 한 번의 콘택 공정과 한 번의 중간층(Contact Pad)을 형성하는 방법을 들 수 있다. 그러나 이 방법은 사용하는 층의 수를 늘리게 됨에 따라, 단차가 증가하며 이는 후속 공정의 난이도를 증가시키는 문제점을 가지게 된다.Another solution that can be used as a solution is one contact process and one method for forming a contact pad. However, as this method increases the number of layers used, the step increases, which increases the difficulty of subsequent processes.
이하 첨부된 도면을 참조하여 종래의 기술에 대해 설명하기로 한다.Hereinafter, a conventional technology will be described with reference to the accompanying drawings.
도 1A 내지 도 1C 는 종래 기술에 따른 기억소자의 제조방법을 도시한 평면도(각도의 도a) 및 단면도(각도의 도 b,c.d )를 도시한 것으로, 단면도는 각도 평면도에서 A-A',B-B',C-C'로 표시한 위치에서 절단한 상태를 도시한 도면이다.1A to 1C show a plan view (angle Fig. A) and a cross-sectional view (angle Fig. B, cd) showing a manufacturing method of a memory device according to the prior art. It is a figure which shows the state cut | disconnected at the position shown by B-B 'and C-C'.
도 1A 를 참조하면, 반도체 기판(10) 상부에 소자 사이의 분리를 위한 절연막(24)을 형성한 후, 게이트 절연막(21)을 형성하고, 워드라인(30,25(절연막))을 형성한 후, 접합영역(16)을 형성하고, 전체구조 상부에 절연막을 덮은 후, 이방성 식각하여 절연막 스페이서(Spacer,27)를 형성한다.Referring to FIG. 1A, after the insulating film 24 for separating the devices is formed on the semiconductor substrate 10, the gate insulating film 21 is formed, and the word lines 30 and 25 (insulating film) are formed. After that, the junction region 16 is formed, the insulating film is covered over the entire structure, and then anisotropically etched to form the insulating film spacers 27.
이때 상기 워드라인 도전막(30) 상부에는 식각 장벽으로 사용되는 절연막(25)이 형성되어 있다.In this case, an insulating film 25 used as an etch barrier is formed on the word line conductive layer 30.
또한 상기에서 스페이서 형성 절연막은 질화막 또는 질화막과 산화막의 적층으로 할 수 있다.In the above description, the spacer forming insulating film may be formed by stacking a nitride film or a nitride film and an oxide film.
도 1B 를 참조하면, 전체구조 상부에 층간 절연막(22)을 형성하고, 상기 절연막(22)을 리소그라피공정과 식각공정을 거쳐 식각함에 의해 콘택 플러그(Contact Plug,35)를 형성하고, 콘택 패트(Contact Pad, 31)도 리소그라피와 식각 공정을 거쳐 형성 한다.Referring to FIG. 1B, an interlayer insulating film 22 is formed on an entire structure, and a contact plug 35 is formed by etching the insulating film 22 through a lithography process and an etching process to form a contact pad. Contact pads 31 are also formed through lithography and etching processes.
이때 상기 도면에서는, 콘택 플러그(35)를 비트라인 콘택이 형성될 부분뿐만 아니라 저장전극 콘택이 형성될 부분에도 형성한다.In this case, the contact plug 35 is formed not only at the portion where the bit line contact is to be formed but also at the portion where the storage electrode contact is to be formed.
도 1C 를 참조하면, 전체구조 상부에 소정두께의 층간 절연막(23)을 형성하고, 비트라인 콘택(40)을 형성한 후, 비트라인 (32)을 형성한다.Referring to FIG. 1C, an interlayer insulating film 23 having a predetermined thickness is formed on the entire structure, a bit line contact 40 is formed, and then a bit line 32 is formed.
상기 도 1C 에 도시된 기술에서는, 추가로 2번의 리도그라피 공정(콘택 플러그, 콘택 패드 형성시)이 필요하며, 콘택 패드(31)층을 형성하기 위하여 층간 절연막(22)을 사용함으로써 소자의 전체적인 단차가 증대되는 단점이 있다.In the technique shown in FIG. 1C, two additional lithography processes (at the time of forming contact plugs and contact pads) are required, and the overall structure of the device is formed by using the interlayer insulating film 22 to form the contact pad 31 layer. There is a disadvantage that the step is increased.
또한, 비트라인(32)을 형성하기 위해서도 층간 절연막이 필요하여 전체적인 단차는 더욱 증대되게 되는 단점이 있다.In addition, since the interlayer insulating film is required to form the bit line 32, there is a disadvantage that the overall step is further increased.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위하여 종래 기술에 비해 콘택 패드 및 비트라인 형성에 의해 발생하는 단차를 줄여주면서도 공정의 난이도를 경감시켜 반도체 소자 제조에 따른 비용을 절감할 수 있고, 소자의 제조공정 수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention can reduce the cost of the semiconductor device manufacturing by reducing the difficulty of the process while reducing the step caused by the contact pad and the bit line formed in order to solve the above-mentioned conventional problems, It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of improving the yield and reliability of the device manufacturing process.
도 1A 내지 도 1C 는 종래기술에 따른 반도체 소자의 제조방법을 도시한 도면으로서, 상기 각 도면에 있어서, 도(a)는 평면도, 도(b,c.d)는 단면도임1A to 1C are diagrams illustrating a method of manufacturing a semiconductor device according to the prior art, in which each figure is a plan view, and FIGS. B and c are sectional views.
도 2A 는 본 발명의 방법에 따라 제조된 반도체 기억소자의 평면도Fig. 2A is a plan view of a semiconductor memory device manufactured in accordance with the method of the present invention.
도 2B 내지 도 2J 는 상기 도 2A 의 평면도에서 A-A', B-B' 및 C-C'로 표시한 위치에서 절단한 상태를 각각 도시한 단면도2B to 2J are cross-sectional views each showing a state of cutting at positions marked A-A ', B-B' and C-C 'in the plan view of FIG. 2A.
도 2CA 내지 도 2EA 및 도 2EB 는 상기 도 2C 내지 도 2E 의 각각 다른 실시예를 도시한 단면도2CA to 2EA and 2EB are cross-sectional views showing different embodiments of the above FIGS. 2C to 2E.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
10 : 반도체 기판 16 : 소오스/드레인 접합10 semiconductor substrate 16 source / drain junction
17,19 : 질화막 18 : 산화막17,19: nitride film 18: oxide film
21 : 게이트 절연막 22,23,25,26,27,28 : 절연막21: gate insulating film 22, 23, 25, 26, 27, 28: insulating film
24 : 소자분리 절연막 30 : 워드라인 도전막24: device isolation insulating film 30: word line conductive film
31 : 콘택패드 도전막 32 : 비트라인 도전막31: contact pad conductive film 32: bit line conductive film
33 : 다결정실리콘 35 : 플러그 콘택33 polycrystalline silicon 35 plug contact
40 : 비트라인 콘택40: bitline contact
이상의 목적을 달성하기 위한 본 발명의 반도체 소자 제조방법의 특징은,Features of the semiconductor device manufacturing method of the present invention for achieving the above object,
반도체 기판 상부에 분리 절연막을 형성하는 공정과,Forming a separation insulating film on the semiconductor substrate;
소자분리 영역으로 예정된 부분의 반도체 기판 상부를 식각하는 공정과,Etching the upper portion of the semiconductor substrate, which is intended as the device isolation region;
소자분리 절연막 및 비트라인으로 사용될 도전막을 형성하는 공정과,Forming an isolation film and a conductive film to be used as a bit line;
연마공정으로 상기 소자 분리 영역에만 상기 절연막과 비트라인 도전막을 남기는 공정과,Leaving the insulating film and the bit line conductive film only in the device isolation region by a polishing step;
산화공정으로 상기 비트라인 상부에 산화막을 형성하는 공정과,Forming an oxide film on the bit line by an oxidation process;
소자 활성영역의 정의를 위해 상기 소자 활성영역에 형성되어 있는 절연막을 제거하는 공정과,Removing an insulating film formed in the device active region to define a device active region;
게이트 절연막, 워드라인 및 접합영역을 차례로 형성하는 공정과,Sequentially forming a gate insulating film, a word line, and a junction region;
전체 구조 상부에 층간 절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire structure;
상기 층간 절연막에 플러그 콘택을 정의하고 식각하는 공정과,Defining and etching a plug contact in the interlayer insulating film;
플러그 콘택으로 사용될 도전막을 형성하는 공정과,Forming a conductive film to be used as a plug contact;
에치백 공정으로 콘택 플러그를 형성하는 공정을 포함하는 것이다.It includes a step of forming a contact plug by the etch back process.
이하, 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대한 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 2A 는 본 발명에 따른 기억소자의 제조방법을 도시한 평면도이고,2A is a plan view showing a method of manufacturing a memory device according to the present invention;
도 2B 내지 도 2J 는 상기 도 2A 의 A-A', B-B' 및 C-C' 선에 따른 단면도로서, 각도의 (a)는 A-A' 선, 각도의 (b)는 B-B' 선, 각도의 (c)는 C-C' 선에 따른 단면도이다.2B to 2J are sectional views taken along the lines A-A ', BB' and CC 'of FIG. 2A, wherein angle (a) is the AA' line, and angle (b) is the BB 'line, and the angle (c ) Is a cross-sectional view along the CC 'line.
먼저, 상기 도 2A 는 본 발명에 따른 기억소자의 평면도이다. 앞서 설명한 종래기술의 도 1C 의 (a)와 비교해 볼 때, 비트라인콘택(40)과 플러그 콘택(35)이 생략되어 있는 평면도처럼 보이는데, 실제 공정진행상 도 1C 의 (a) 에서의 콘택 패드(31)처럼 표시된 층이 플러그 콘택으로 사용될 것이므로, 비트라인 콘택(40)과 콘택 패드(31)가 생략된 평면도이다.First, FIG. 2A is a plan view of a memory device according to the present invention. Compared with (a) of FIG. 1C of the related art described above, the bit line contact 40 and the plug contact 35 are shown as a plan view in which the contact line is omitted, and the contact pad (a) in FIG. Since the layer indicated as 31 will be used as the plug contact, the bit line contact 40 and the contact pad 31 are omitted.
제 2B 도를 참조하면, 반도체 기판 (10) 상부에 산화막(18) 및 질화막(19)을 차례로 형성한후, 소자 분리 영역의 반도체 기판(1) 상부를 식각한다.Referring to FIG. 2B, after the oxide film 18 and the nitride film 19 are sequentially formed on the semiconductor substrate 10, the upper portion of the semiconductor substrate 1 in the device isolation region is etched.
도 2C 를 참조하면, 절연막(24)과 비트라인으로 사용될 다결정실리콘(33)를 차례로 형성한다. 이때, A-A'로 표시한 위치에서의 소자 분리영역의 폭은 절연막 (24)만 형성될 경우에는 완전히 채워지는 폭이고, B-B′로 표시한 위치에서의 소자 분리 영역의 폭은 절연막(24)만 형성될 경우에는 완전히 채워지지 않는 폭이어야 한다.Referring to FIG. 2C, an insulating film 24 and a polysilicon 33 to be used as a bit line are sequentially formed. At this time, the width of the device isolation region at the position indicated by A-A 'is the width that is completely filled when only the insulating film 24 is formed, and the width of the device isolation region at the position indicated by BB' is the insulation layer 24. If only) is to be formed, the width shall not be completely filled.
도 2D 를 참조하면, 화학적 기계적 연마(Chemical Mechanical Polishing ; 이하 CMP 라 함)를 이용한 연마공정을 거쳐 비트라인 도전막(33)과 절연막(24)을 소자분리 영역에만 남긴다.Referring to FIG. 2D, the bit line conductive layer 33 and the insulating layer 24 are left only in the device isolation region through a polishing process using chemical mechanical polishing (hereinafter referred to as CMP).
도 2E 를 참조하면, 산화 공정을 거치면서 소자 활성영역에서는 질화막이 상부를 가리고 있어 산화막이 형성되지 않고, 비트라인 부분에만 산화막(26)이 형성된다.Referring to FIG. 2E, the nitride film is covered in the upper portion of the device active region during the oxidation process, so that the oxide film is not formed, and the oxide film 26 is formed only in the bit line portion.
도 2F 를 참조하면, 상부의 질화막(19)과 산화막(18)을 벗겨낸 후, 이어서 게이트 절연막(21)을 형성한다.Referring to FIG. 2F, the upper nitride film 19 and the oxide film 18 are peeled off, and then the gate insulating film 21 is formed.
도 2G 를 참조하면, 워드라인 도전막(30)과 식각 장벽으로 사용될 절연막(25)을 차례로 형성한다.Referring to FIG. 2G, the word line conductive layer 30 and the insulating layer 25 to be used as an etch barrier are sequentially formed.
도 2H 를 참조하면, 워드라인 식각 공정을 거치고, 접합영역(16)을 형성한 이후에, 스페이서(27)형성 공정을 거친다Referring to FIG. 2H, after the word line etching process is performed and the junction region 16 is formed, the spacer 27 is formed.
도 2I 를 참조하면, 전체구조 상부에 층간 절연막(22)을 형성한다.Referring to FIG. 2I, an interlayer insulating film 22 is formed on the entire structure.
도 2J 를 참조하면, 상기 층간 절연막(22)에 플러그 콘택홀을 정의하고, 도전막을 형성한후 에치백 공정을 거쳐 콘택 플러그(35)를 형성한다.Referring to FIG. 2J, a plug contact hole is defined in the interlayer insulating layer 22, a conductive film is formed, and a contact plug 35 is formed through an etch back process.
이때, 상기 도 2J 의 (c)(상기 도 2A 의 C-C' 선에 따른 단면도)에서 보는 바와 같이, 비트라인(32)과 소자 활성영역의 연결이 이루어진다.At this time, as shown in (c) of FIG. 2J (sectional view taken along the line C-C 'of FIG. 2A), the bit line 32 is connected to the device active region.
한편, 도 1C , 도 2A 및 도 2J 를 비교해 보면, 도 1C 에서 도시된 종래 기술에서는, 비트라인 콘택을 소자 활성영역 바깥에 형성하기 위해 추가로 2번의 리도그래피 공정(플러그 콘택, 콘택 패드)이 필요하며, 콘택 패드층과 비트라인을 형성하기 위하여 층간 절연막을 사용함으로써 소자의 전체적인 단차가 증대되는 단점이 있다.On the other hand, comparing FIGS. 1C, 2A, and 2J, in the prior art shown in FIG. 1C, two additional lithographic processes (plug contacts, contact pads) are performed to form the bit line contacts outside the device active region. There is a need to use an interlayer insulating film to form a contact pad layer and a bit line, thereby increasing the overall level of the device.
도 2A 에 도시된 본 발명에 의한 레이아웃에서는, 비트라인이 소자의 활성영역(Active)과 따로 그려져 있으나, 실제로는 비트라인이 소자 분리 영역 형성시에 같이 형성되어 따로 비트라인 형성 공정이 없고, 또한 비트라인 콘택은 콘택 플러그로 대신되므로 공정 단순화가 이루어져 있다.In the layout according to the present invention shown in Fig. 2A, the bit lines are drawn separately from the active region of the device, but in reality, the bit lines are formed together at the time of forming the device isolation region so that there is no separate bit line forming process. Bitline contacts are replaced by contact plugs, which simplifies the process.
따라서 상기한 본 발명의 반도체 소자 제조공정에서는 종래의 기술에 비해, 콘택 패드, 비트라인 콘택, 비트라인 등 3번의 리도그라피 공정이 생략됨을 알 수 있으며, 또한, 비트라인 및 콘택 패드 형성시까지 한 번의 층간 절연막이 사용되고 있어, 소자의 전체적인 단차가 낮아지는 장점도 있다.Accordingly, it can be seen that in the semiconductor device manufacturing process of the present invention, three lithography processes such as a contact pad, a bit line contact, and a bit line are omitted in comparison with the conventional technology. Since the interlayer insulating film is used, there is also an advantage that the overall step of the device is lowered.
한편, 도 2CA 내지 도 2EA 및 도 2EB 는 상기 도 2C 내지 도 2E 의 각각 다른 실시예를 도시한 단면도이다.Meanwhile, FIGS. 2CA to 2EA and 2EB are cross-sectional views illustrating different embodiments of FIGS. 2C to 2E.
예컨데, 도 2CA를 참조하면, 상기 도 2C 와 비교해 볼 때 절연막(24)과 다결정 실리콘(33)을 형성하기 이전에 얇은 질화막(17)을 형성하여 제 2E 도의 공정에서 산화를 진행할 때 소자 분리 영역의 측면이 산화되는 것을 방지하도록 한다.For example, referring to FIG. 2CA, in comparison with FIG. 2C, when the thin nitride layer 17 is formed before the insulating layer 24 and the polycrystalline silicon 33 are formed, oxidation is performed in the process of FIG. 2E. To prevent the side of the oxidized.
또한, 도 2EA 와 도 2EB를 참조하면, 연마공정 이후에 비트라인 도전막(32)을 추가 식각하고, 그 상부에 다시 절연막(28)을 형성한다. 연마공정을 진행한 후 절연막(18,19)을 제거하여 비트라인 상부에 절연막을 형성하고, 이후 게이트 절연막(21)을 형성한다.In addition, referring to FIGS. 2EA and 2EB, the bit line conductive layer 32 is additionally etched after the polishing process, and an insulating layer 28 is formed on the bit line conductive layer 32. After the polishing process, the insulating films 18 and 19 are removed to form an insulating film on the bit line, and then the gate insulating film 21 is formed.
이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 기억소자 제조방법은, 기존의 기술에 비해 콘택 형성 공정 단계에서의 공정 단계 및 난이도가 감소하면서도, 다른 공정 단계에서의 난이도를 증가시키지 않는 기술이므로, 고집적 기억소자에 사용될 경우, 공정 단계의 감소 및 공정의 난이도 감소에 의한 비용 감소 및 수율 향상 등의 경제적 이득이 있는 기술이다.As described above, the method of manufacturing a semiconductor memory device according to the present invention is a technology that does not increase the difficulty in other process steps while reducing the process step and difficulty in the contact forming process step, compared to the existing technology. When used in a memory device, it is a technology that has economic benefits, such as cost reduction and yield improvement due to the reduction of the process step and the difficulty of the process.
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US7781285B2 (en) | 2005-10-10 | 2010-08-24 | Samsung Electronics Co., Ltd. | Semiconductor device having vertical transistor and method of fabricating the same |
KR101129919B1 (en) * | 2010-04-15 | 2012-03-23 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming the same |
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US7781285B2 (en) | 2005-10-10 | 2010-08-24 | Samsung Electronics Co., Ltd. | Semiconductor device having vertical transistor and method of fabricating the same |
US8174065B2 (en) | 2005-10-10 | 2012-05-08 | Samsung Electronics Co., Ltd. | Semiconductor device having vertical transistor and method of fabricating the same |
KR101129919B1 (en) * | 2010-04-15 | 2012-03-23 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming the same |
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