KR20000027275A - Flash memory cell and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A flash memory cell and a method for manufacturing the same are provided to store a multi-bit data according to the number of control gate by using a characteristic of continuously varied time. CONSTITUTION: A flash memory cell comprises a floating gate(130), a control gate(140,150),a source area(110), and a drain area(120). The flash memory cell further comprises two more control gates to store a multi-bit data. A method for manufacturing the same comprises the steps of: forming a tunnel oxidation layer(125) and a floating gate; forming a first dielectric layer(135) on an upper portion of the floating gate; forming a first control gate(140) on an upper portion of the first dielectric layer; forming a second dielectric layer(145) on an upper portion of the first control gate; forming a second control gate(150) on an upper portion of the second dielectric layer; and forming a source area and a drain area on an exposed portion of the substrate.

Description

Flash memory cell and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory cell and a method of manufacturing the same, and more particularly, to a flash memory cell capable of storing data in various states according to the number of control gates and a method of manufacturing the same.

In general, an electrically erasable programmable read only memory (EEPROM) device having an electrically programmed and erase function is in increasing demand due to its inherent advantages. Since the flash Y pyrom device can store and read binary information, i.e., 0 or 1 in one cell, there are 256 (= 2 ⁸ ) information amounts that can be displayed in 1 byte (8 cells). do. However, if one cell can store binary information, i.e. 0, 1, 2 or 3, then the amount of information in one byte is 65536 (= 4 ⁸ ), which is 256 times larger than a cell that can store binary information. It can store a large amount of information. Therefore, it is possible to implement a memory device having a capacity of 1 Giga or more.

However, a drawback of the flash Y pyrom device which can store only binary information is that its manufacturing cost per unit cell is high. In order to overcome this, high integration of cells is essential, and each manufacturer is making a lot of efforts to achieve this. In addition, since the structure of the flash Y-pyrom device is relatively complicated compared to DRAM, there are many difficulties in high integration. Recently, Intel announced 32 / 64M, which was created by storing 2 bits in one cell, and multi-bit cells have become a subject of intense research and development among manufacturers.

As part of this, much effort has recently been made to increase the density of flash memory cells. Most of that effort is skewed towards controlling the time spent on programs. Next, an embodiment of a conventional flash memory cell will be described with reference to the first (a) and the second (b).

FIG. 1 (a) is a cross-sectional view schematically illustrating an embodiment of a conventional flash memory cell, and FIG. 1 (b) shows a threshold voltage of a cell with a change in time in a conventional flash memory cell. This is a graph for explaining the changing process.

Referring to FIG. 1A, a floating gate 30 and a control gate 40 are sequentially stacked on a semiconductor substrate 1 on which sources and drains 10 and 20 are formed. A tunnel oxide film 25 is formed between the semiconductor substrate 1 and the floating gate 30, and a dielectric film 35 is formed between the floating gate 30 and the control gate 40. Sources and drains 10 and 20 are formed in selected regions of the semiconductor substrate 1 on which the gate electrodes are formed.

The program operation of the flash memory cell thus formed is as follows.

After the hot carrier is injected into the floating gate 30, the injected hot carrier is discharged toward the drain 20. At this time, the amount of hot carriers remaining in the floating gate 30 is adjusted by adjusting the time at which the hot carriers are extracted, and the amount of hot carriers remaining in the floating gate 30 according to a change in time for allowing the hot carriers to be extracted. The amount of hot carrier is adjusted, whereby the threshold voltage Vt of the cell is changed as shown in FIG. 1 (b) to store various bits of information such as 0, 1, 2, 3 in the memory cell. . Therefore, a flash memory cell capable of storing multi-bit data using a memory cell having such a structure is implemented.

Conventional flash memory cells must control the extraction time of hot carriers in order to retain a certain amount of hot carriers in the floating gate. However, it is difficult to accurately store the information when using a conventional method because it is difficult to precisely control the continuously changing time.

Therefore, since the present invention can store multi-bit data according to the number of control gates, it is possible to store accurate information regardless of time characteristics, and to increase the efficiency of area according to the number of control gates. It is an object of the present invention to provide a memory cell and a method of manufacturing the same.

Flash memory cell according to the present invention for achieving the above object in the flash memory cell consisting of a floating gate, a control gate, a source and a drain on a semiconductor substrate, to implement the memory cell for multi-bit data storage, the control At least two gates are formed.

A method of manufacturing a flash memory cell according to the present invention for achieving the above object is to form a field oxide film on a semiconductor substrate to define an active region, and then sequentially form a tunnel oxide film and a polysilicon layer for floating gate on the entire structure. step; Forming a polysilicon pattern for a floating gate through an etching process using a first mask; Sequentially forming a first dielectric film, a polysilicon layer for a first control gate, a second dielectric layer, a polysilicon layer for a second control gate, and a mask oxide film on the entire structure of the floating gate polysilicon pattern; Forming a second control gate through a first etching process using a second mask; The second dielectric layer, the polysilicon layer for the first control gate, the first dielectric layer, the polysilicon pattern for the floating gate, and the tunnel oxide layer are sequentially self-etched through an etching process using the second mask. Forming a first control gate and a floating gate; And forming a source and a drain in the exposed portion of the semiconductor substrate.

Another method of manufacturing a flash memory cell according to the present invention for achieving the above object comprises the steps of forming a tunnel oxide film and a floating gate on a semiconductor substrate; Forming a first dielectric layer on the floating gate; Forming a first control gate on the first dielectric layer; Forming a second dielectric layer on the first control gate; Forming a second control gate on the second dielectric layer; And forming a source and a drain in the exposed portion of the semiconductor substrate.

1 (a) is a cross-sectional view schematically illustrating one embodiment of a conventional flash memory cell.

1B is a graph illustrating a process of changing a threshold voltage of a cell according to a change in time in a conventional flash memory cell.

Figure 2 (a) is a cross-sectional view for explaining an embodiment of a flash memory cell according to the present invention.

2 (b) and 2 (c) are cross-sectional views shown for explaining the program operation of one embodiment of a flash memory cell according to the present invention;

<Description of Signs of Major Parts of Drawings>

1 and 100: semiconductor substrate 10 and 110: source

20 and 120: drain 25 and 125: tunnel oxide film

30 and 130: floating gates 35, 135 and 145: dielectric film

40, 140, and 150: control gate 155: mask oxide film

(Example)

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 (a) is a cross-sectional view illustrating an embodiment of a flash memory cell according to the present invention, and FIGS. 2 (b) and 2 (c) illustrate a program operation of an embodiment of the flash memory cell according to the present invention. It is sectional drawing shown to illustrate.

The floating gate 130, the first control gate 140, and the second control gate 150 are sequentially stacked on the semiconductor substrate 100. A tunnel oxide layer 125 is formed between the semiconductor substrate 100 and the floating gate 130, between the floating gate 130 and the first control gate 140, and the first and second control gates 140. And the first and second dielectric films 135 and 145 are formed between the first and second dielectric layers 150 and 150. Source and drain 10 and 20 are formed in a selected region of the substrate on which the gate electrode is formed.

A method of manufacturing a flash memory cell configured as described above is as follows.

After forming a field oxide film (not shown) on the semiconductor substrate 100 to define an active region, the tunnel oxide film 125 and the polysilicon layer 130 for floating gate are sequentially formed on the entire structure. A portion of the neighboring field oxide layer overlaps each other, and a linear first mask layer (not shown) is formed on the floating gate polysilicon layer 130 to be parallel to the field oxide layer. The floating gate polysilicon layer 130 and the tunnel oxide layer 125 are sequentially etched through an etching process using the first mask layer. As a result, a linear floating polysilicon pattern 130 is formed to partially overlap the field oxide layer. The first dielectric layer 135, the first control gate polysilicon layer 140, the second dielectric layer 145, and the second control gate polysilicon are formed on the entire structure of the floating gate polysilicon pattern 130. The layer 150 and the mask oxide film 155 are sequentially formed. A linear second mask layer (not shown) is formed on the mask oxide layer 155 in a direction intersecting with the floating gate polysilicon pattern 130 and the field oxide layer. The mask oxide layer 155 and the polysilicon layer 150 for the second control gate 150 are etched through the etching process using the second mask layer to form the second control gate 150. At this time, a transistor (not shown) of a peripheral circuit is formed at the same time. The second dielectric layer 145, the polysilicon layer 140 for the first control gate 140, the first dielectric layer 135, the polysilicon pattern 130 for the floating gate and the tunnel through an etching process using the second mask layer. The oxide film 125 is sequentially self-etched. As a result, the first control gate 140 and the floating gate 130 are formed. Here, the difference between the threshold voltages may be adjusted by the electrical thicknesses of the first and second dielectric layers 135 and 145. After the source and drain regions 110 and 120 are formed in the exposed portions of the semiconductor substrate 100 through an impurity ion implantation process, a flash memory cell for storing multi-bit data is performed by performing planarization and metallization processes. Complete

The flash memory cell formed as described above may store data of various states according to the number of the control gates. For example, when the control gate is composed of two, the flash memory cell may store data of three states such as 0, 1, and 2. have.

Then, in order to explain the program operation of the flash memory cell configured as described above, after injecting a hot carrier into the floating gate 130, it is necessary to extract as many hot carriers as necessary, which is illustrated in FIGS. 2 (b) and 2 (c). Referring to the following.

Referring to FIG. 2B, a bias condition for injecting hot carriers into the floating gate 130 is based on a state in which 0 V is applied to the source 110 and a voltage greater than 0 V is applied to the drain 120. The voltage greater than the voltage applied to the drain 120 is applied to the first control gate 140.

Referring to FIG. 2C, a bias condition for extracting hot carriers from the floating gate 130 is that the first and second control gates 140 and 150 are applied to a drain 120 with a voltage greater than 0V. ), A voltage greater than 0V is applied.

As described above, when the voltage Vcg1 is applied to the first control gate 140 adjacent to the floating gate 130 by the capacitance ratio and when the voltage Vcg2 is applied to the second control gate 150, When the amount of hot carriers extracted from the floating gate 130 to the drain 120 is changed, a voltage applied to Vcg1 has a lower threshold voltage than a voltage applied to Vcg2. According to this principle, a memory device for storing multi-bit data may be implemented by using a memory cell in which data of various states is stored. At this time, the number of bits of data that can be stored is determined according to the number of control gates. The threshold voltage ratio per bit may be adjusted according to the capacitance ratio between each gate.

As described above, the present invention utilizes a characteristic of time that continuously changes, and thus it is possible to store multi-bit data according to the number of control gates, compared to the conventional method, which is difficult to store accurate information. Accurate information can be stored regardless, and the efficiency of the area can be doubled (2 ⁿ ) according to the number n of control gates.

Claims (4)

A flash memory cell comprising a floating gate, a control gate, a source, and a drain in a semiconductor substrate, And at least two control gates for implementing a multi-bit data storage memory cell. Forming a field oxide film on the semiconductor substrate to define an active region, and then sequentially forming a tunnel oxide film and a polysilicon layer for floating gate on the entire structure; Forming a polysilicon pattern for a floating gate through an etching process using a first mask; Sequentially forming a first dielectric film, a polysilicon layer for a first control gate, a second dielectric layer, a polysilicon layer for a second control gate, and a mask oxide film on the entire structure of the floating gate polysilicon pattern; Forming a second control gate through a first etching process using a second mask; The second dielectric layer, the polysilicon layer for the first control gate, the first dielectric layer, the polysilicon pattern for the floating gate, and the tunnel oxide layer are sequentially self-etched through an etching process using the second mask. Forming a first control gate and a floating gate; And Forming a source and a drain in the exposed portion of the semiconductor substrate. The method of claim 2, And at least two control gates including the first and second control gates. Forming a tunnel oxide film and a floating gate on the semiconductor substrate; Forming a first dielectric layer on the floating gate; Forming a first control gate on the first dielectric layer; Forming a second dielectric layer on the first control gate; Forming a second control gate on the second dielectric layer; And Forming a source and a drain in the exposed portion of the semiconductor substrate.