KR20000026173A - Column repair circuit - Google Patents

Abstract

PURPOSE: A column repair circuit is provided to decrease a chip size and perform a stable chip operation by simplifying a column repair circuit composition of a memory device into which a graphic function is inserted. CONSTITUTION: A first fuse box unit(30) outputs a repair column address signal(RYA012) with a certain level according to a fuse program. A second fuse box unit(40) outputs a column address signal(BKYA) with a certain level according to the fuse program. A decoding unit(50) receives the repair column address signal(RYA012) of the first fuse box unit(30) and the column address signal(BKYA) of the second fuse box unit(40), decodes the received repair column address signal(RYA012) and the received column address signal(BKYA), and outputs a redundancy column decoder enable signal(RCEb) with a certain level.

Description

Column repair circuit

The present invention relates to a column repair circuit, and more particularly, to a column repair circuit employed in a graphics memory device to perform a column repair operation.

Memory devices and DRAMs designed for graphics such as Synchronous Graphics RAM (SGRAM), Window RAM (WRAM), Video RAM (VRAM), etc., which are equipped with a conventional block write function. If any one of a large number of fine cells constituting a DRAM) or a synchronous DRAM (SDRAM) occurs, the memory device may not function properly. Therefore, in this case, a repair method is adopted in which a yield rate is increased by replacing defective cells by using spare memory cells installed in the memory elements in advance.

In particular, in the case of such a repair method, for example, a 16 mega DRAM, a spare row and a column are pre-installed for every 256K cell array so that a failure occurs and a defective memory cell is stored in row / column units. In this case, a method of replacing a spare memory cell (that is, a redundant cell) is mainly used.

1 is a configuration diagram of a column repair circuit used in a conventional synchronous graphics RAM, and receives a column address signal YA012 <7: 0> from the outside and repairs the column address signal RYAijk by an internal fuse programming operation. A second fuse that receives the first fuse box unit 10 and a column address signal YA345 <7: 0> from the outside, and outputs a repair column address signal RYAijk by an internal fuse programming operation. A third fuse box unit 14 which receives the box unit 12 and the column address signal YA67 <3: 0> from the outside and outputs the repair column address signal RYAij by an internal fuse programming operation; The output unit 16 which decodes the output signals of the first to third fuse box units 10 to 14 and outputs a redundancy column decoder enable signal RCEb of a predetermined level, and a repair internal fuse are programmed. Results to the output 16 Repair consists of a master fuse box (18) for the ball.

As shown in FIG. 2, the first fuse box unit 10 outputs a predetermined level of signals 0b, 0; 1b, 1; 2b, and 2 according to a fuse program state allocated to each address. 21, 22, 23, and a decoding section 25 that decodes the signals from the fuse boxes 21, 22, 23, and outputs a defective column address signal as a repair column address signal RYAijk. .

The second fuse box part 12 also has the same configuration as the first fuse box part 10, and the third fuse box part 14 includes the first and second fuse box parts 10 and 12. However, the difference is that the first and second fuse box units 10 and 12 have three fuses and eight NAND gates and NMOS devices in the decoding unit 25, respectively. On the other hand, as shown in FIG. 3, the third fuse box unit 14 has two fuses and four NAND gates and four NMOS devices in the decoding unit 25.

According to the column repair circuit used in the conventional synchronous graphics RAM configured as described above, the outputs RYAijk and RYAij of the respective fuse box parts 10 to 14 are outputted according to whether or not the fuses allocated to each address are programmed. The output RCEb of the output unit 16 is determined by the signal of the repair master fuse 18. For example, in FIG. 3, if a fuse in the fuse box 21 is programmed (ie, disconnected) and the fuse box 22 is left as it is, the node 0b and the node 1 go high, and the node 0b, The signal of 1) is NAND-processed at the NAND gate ND3 in the decoding section 25, and makes the level of the node G43 high. As a result, the NMOS transistor T3 is turned on to output the column address signal YAij <2> as the repair column address signal RYAijk. The signal of each of the fuse box parts 10, 12, and 14 thus output is input to an input terminal of the NAND gate NG of the output part 16, and a signal according to the fuse program result of the repair master fuse box 18 (repair When the fuse is blown, the high level signal is input to the input terminal of the NAND gate NG. Therefore, the output unit 16 outputs a low level redundancy column decoder enable signal RCEb to output a redundancy column decoder (not shown). Omit).

In the conventional column repair circuit operating as described above, since the concept of decoding using eight fuses, an inverter, and a NAND gate is used to construct one column repair circuit, the circuits are complicatedly combined to increase the chip area. There is a problem that results.

Accordingly, an object of the present invention is to provide a column repair circuit that can reduce the chip area by simplifying the circuit configuration.

In order to achieve the above object, a column repair circuit according to a preferred embodiment of the present invention includes a first fuse box means for outputting a repair column address signal according to whether a fuse program is provided;

A second fuse box means for outputting a column address signal according to whether the fuse is programmed;

Decoding means for decoding the signals from the first and second fuse box means and outputting a redundancy column decoder enable signal,

The first fuse box means has a MOS device installed between its output terminal and the ground terminal and switched on / off by a power up signal, and a latch provided between the output terminal and the ground terminal to bring the output level to a predetermined level. And a plurality of switching transistors having an initialization unit for initializing, a plurality of drain transistors connected to a plurality of column address signal terminals, a gate connected to a plurality of fuse box output terminals, and a common source connected to the output terminals. And a signal output section for outputting a corresponding column address signal as a repair column address signal.

1 is a configuration diagram of a conventional column repair circuit,

FIG. 2 illustrates an internal circuit of the first fuse box unit illustrated in FIG. 1;

3 is a diagram illustrating an internal circuit of the third fuse box unit illustrated in FIG. 1;

4 is a column repair circuit diagram according to an embodiment of the present invention.

<Description of the reference numerals for the main parts of the drawings>

10: first fuse box unit 12: second fuse box unit

14: third fuse box unit 16: output unit

18: Repair master fuse box 21, 22, 23: fuse box

25 decoding unit 30 first fuse box means

40: second fuse box means 50: decoding means

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a column repair circuit diagram according to an embodiment of the present invention. The embodiment of the present invention may include a first fuse box means 30 for outputting a repair column address signal RYA012 having a predetermined level according to whether a fuse is programmed, and a fuse. A second fuse box means 40 for outputting a column address signal BKYA of a predetermined level according to whether or not a program is present, and a signal RYA012 and the second fuse box means 40 of the first fuse box means 30. And decoding means 50 for receiving and decoding the signal BKYA and outputting a redundancy column decoder enable signal RCEb of a predetermined level.

The first fuse box means 30 is provided between an output terminal K1 and a ground terminal thereof, and is NMOS transistor N11 and on / off-switched by a power-up signal PWRUPb and the output terminal K1 and a ground terminal. An initialization unit 32 having a latch provided between the inverter I11 and the NMOS transistor N12 to initialize the level of the output terminal K1 to a predetermined level (for example, a low level), and a column address signal. Each drain is connected to each of the input terminals of YA012 <7: 0>, a gate is connected to the output terminals G0 to G7 of the plurality of fuse boxes 34a to 34h, and a source is common to the output terminals G0 to G7. A plurality of switching transistors NT0 to NT7 (NMOS transistors) connected to each other and corresponding column address signals according to whether the fuses f10 to f17 in the fuse boxes 34a to 34h are programmed are repaired to the column address signals RYA012. And a signal output section 34 for outputting.

The second fuse box means 40 is installed between a power supply voltage terminal and its output terminal K2 and is switched by a control signal YPCGb to make the output terminal K2 a predetermined level, and the A latch consisting of an inverter I12 and a PMOS transistor P12 holding the potential of the output terminal K2, and a drain are commonly connected to the output terminal K2 via fuses f18 to f21, and the gate is connected to a column address signal ( YA67 <3: 0>) are respectively connected to the input terminal and the source is connected to a plurality of NMOS transistors T0 to T3 and the output terminal K2, and the drains are commonly connected via the fuses f22 to f29. The gate is connected to the input terminal of the column address signal YA345 <7: 0>, respectively, and the source is composed of a plurality of NMOS transistors Q0 to Q7 connected to the ground terminal.

The decoding means 50 is composed of two input NAND gates ND11.

The high voltage Vpp shown in the drawing is a power supply Vdd + 2Vt having a potential that is about twice as high as the transistor threshold potential Vt of the power supply voltage Vdd of the chip, and the power-up signal PWRUPb is applied to the memory chip. It is a signal that detects that power is applied and maintains a logic high state at first, and then turns to logic low when the power supply voltage rises to a certain level. The control signal (YPCGb) is input every time a column access signal (read or write) command is input. It has a low pulse every clock cycle. The column address signals YA012 <7: 0> are eight signal bundles generated by precoding the addresses A0, A1, and A2 input during column access, corresponding to the input state of the addresses A0, A1, and A2. One signal YA012 has a high pulse. The column address signals YA345 <7: 0> are eight signal bundles generated by pre-decoding the addresses A3, A4, and A5 input during column access, and correspond to the input states of the addresses A3, A4, and A5. One signal YA345 has a high pulse. The column address signal YA67 <3: 0> is a bundle of four signals generated by pre-decoding the addresses A6 and A7 input during column access, and corresponds to one signal corresponding to the input state of the addresses A6 and A7. YA67) has a high pulse.

Next, the operation of the column repair circuit according to the embodiment of the present invention configured as described above will be described.

When the power up signal PWRUPb is in a high state, as the NMOS transistor N11 of the initialization unit 32 of the first fuse box means 30 is turned on, the output terminal K1 is discharged to the ground voltage terminal Vss. It has a low level. When the output terminal K1 becomes low level, the NMOS transistor N12 is turned on by the inverter I11, so that the output terminal K1 continues to maintain the low level. When a command for activating a bank (or a row selection command or a row active command) is input, the control signal YPCGb outputs a low pulse every clock period, and the low pulse of the control signal YPCGb is output. As a result, the PMOS transistor P11 in the second fuse box means 40 is turned on to bring the output terminal K2 to a high level, and then the control signal YPCGb remains high to turn off the PMOS transistor P11. Even though the output stage K2 is maintained at the high level by the inverter I12 and the PMOS transistor P12.

If all of the memory elements are operating normally, the fuses f10 to f17 of the first fuse box means are left unchanged. Therefore, the signals of the output terminals G0 to G7 of the inverters IP0 to IP7 all have low values. Even if all of the NMOS transistors NT0 to NT7 are turned off and the column address signals YA012 <7: 0> are input with high pulses, the output terminal K1 keeps the low value in the precharge state. Further, the fuses f18 to f29 in the second fuse box means 40, to which the column address signals YA67 <3: 0> and YA345 <7: 0> are input, are also not blown and remain intact to the control signal YPCGb. As a result, the NMOS transistors T0 to T3 and Q0 to Q7 connected to the fuses f18 to f29 are turned on to discharge the output terminal K2 at the high level. Accordingly, since all low values are input to the input terminal of the NAND gate ND11 constituting the decoding means 50, the output redundancy column decoder enable signal RCEb remains high, which is a redundant column decoder (not shown). ) Is prevented from being enabled.

In contrast, if a memory cell has a defective cell, the fuse corresponding to the defective cell is programmed (disconnected). When the address of the defective cell is input, the fuse corresponding to the defective cell is cut off, so the output terminal K2 of the second fuse box means 40 remains high, and the column address signal YA012 <7: 0> One of the eight input NMOS transistors NT0 to NT7 is turned on so that the output terminal K1 of the first fuse box means 30 has a high pulse. In other words, for example, when the fuse f10 is disconnected, since the capacitor is at the input terminal of the inverter IP0 and the path to be charged is disconnected, it is latched low by the NMOS transistor NI0 connected to the ground voltage terminal. Accordingly, the output terminal G0 of the inverter IP0 has a high state, and the NMOS transistor NT0 is kept turned on so that the high level column address signal YA012 <0> has its NMOS transistor NT0. It is provided to the output terminal (K1) through. Therefore, the output terminals K1 and K2 both have high values, so that the output signal RCEb of the NAND gate ND11 has a low pulse, and the output signal RCEb of the low pulse has a redundancy column decoder (not shown). Enable).

An embodiment of the present invention constructed and operated as described above is mainly employed in a synchronous graphics RAM (SGRAM) having a block write function, which writes data by performing eight columns at a time by a write command. It can process 8 times as much data as normal write operation. In a normal write operation, one of the eight column address signals (YA012 <7: 0>) has a high pulse, so one corresponding column is enabled. However, when a block write command is input, the column address signal (YA012 <7: 0>) is enabled. All eight have high pulses, enabling eight columns. Since the embodiment of the present invention is applied to the synchronous graphics RAM having the block write function, the above-described operation is applied as it is. When any one of the eight columns enabled at the time of block write accesses the defective cell, the redundancy column is activated and repaired by the same method of disconnecting the fuse corresponding to the column address for accessing the defective cell.

According to the present invention as described above, by simplifying the column repair circuit configuration of the memory device with a built-in graphics function, it is possible to reduce the chip area and perform stable chip operation.

On the other hand, the present invention is not limited only to the above-described embodiments, but may be modified and modified without departing from the scope of the present invention.

Claims (3)

First fuse box means for outputting a repair column address signal according to whether the fuse is programmed; A second fuse box means for outputting a column address signal according to whether the fuse is programmed; Decoding means for decoding the signals from the first and second fuse box means and outputting a redundancy column decoder enable signal, The first fuse box means has a MOS device installed between its output terminal and the ground terminal and switched on / off by a power up signal, and a latch provided between the output terminal and the ground terminal to bring the output level to a predetermined level. And a plurality of switching transistors having an initialization unit for initializing, a plurality of drain transistors connected to a plurality of column address signal terminals, a gate connected to a plurality of fuse box output terminals, and a common source connected to the output terminals. And a signal output section for outputting a corresponding column address signal as a repair column address signal. The method of claim 1, And the initialization unit initially maintains the level of the output terminal at a ground voltage level. The method of claim 1, And said plurality of switching transistors are NMOS transistors.