KR20000026171A - Test method for semiconductor memory device and control unit thereof - Google Patents

Abstract

PURPOSE: A parallel test method for a semiconductor memory device and a control unit thereof are provided to decrease test time of memory product. CONSTITUTION: In a parallel test control unit of a semiconductor memory device, a parallel test control part(36) receives and mixes a CAS(Column Address Strobe) signal come from a CAS buffer(10), a RAS(Row Address Strobe) signal come from a RAS buffer(12), and a WE(Write Enable) signal come from a WE buffer(14) for perceiving WCBR condition. Also, when a parallel test mode starts, the control part(36) write data at all memory cells in a memory cell array(26) by offering a dynamic signal(WPTD1,WPTD2) to a bit-line sense amp(32) and decides pass or fault of the memory cells by reading the data of all the cells in sequence. At the same time, the control part(36) feeds control signal(WPTC) to an address buffer(16) and a row free decoder(18) for making the buffer(16) and the decoder(18) disable condition.

Description

Parallel test method of semiconductor memory device and its control device

The present invention relates to a parallel test method for a semiconductor memory device and a control device thereof, and more particularly, to a parallel test method and a control method of a semiconductor memory device configured to determine whether a defect is detected in all cells by a parallel test after fabrication of the memory device. Relates to a device.

As is well known, during the mass production or research and development of a semiconductor memory device such as DRAM, etc., a predetermined test process is performed. This test process detects defects in manufacturing process such as wafer process process or assembly process, removes defective products and selects only good products, and whether the function or performance of the manufactured semiconductor memory device is consistent with the design specification. Validation test procedures to verify.

Conventionally, when a semiconductor memory device is manufactured, a pass / fail is determined for all cells of the semiconductor memory device through a test process, and among the cells determined as defective, the repairable cell is repaired and the repair is impossible. The cell is discarded.

As the test process is performed after fabricating the semiconductor memory device as described above, the parallel test mode is generally adopted. As a result, many parallel test processes are used to determine the pass / fail of all cells while writing / reading data into the cells by 32 bits. In the conventional parallel test, as shown in FIG. 1, the cas test signal / CAS goes low before the ras signal / RAS, and the parallel test signal (WE) is enabled while the write enable signal / WE is enabled. The parallel test mode starts as the PT) becomes enabled (“high” level). If the write enable signal / WE is enabled again after the parallel test mode is started, the write cycle 1-1 and the read cycle 1-2 are performed between the subsequent write enable signals. Iteratively tests the cell of every bit.

When testing a 32-bit cell by such a parallel test operation, cycles 1 through 1 and 1 through 2 as shown in FIG. 1 are required, and 2,000,000 (64 M in the case of a 64 mega DRAM). Since a cycle of 32 bits (bits / 32 bits) x 2 (write, read) is required, a large amount of time is required when testing a large amount of finished products.

Accordingly, an object of the present invention is to provide a parallel test method for a semiconductor memory device and a control apparatus for reducing the test time for all cells of the semiconductor memory device.

In order to achieve the above object, a parallel test method of a semiconductor memory device according to an exemplary embodiment of the present invention may block data from all memory cells in a memory cell array by blocking input paths of row and column addresses when entering a parallel test mode. And a step of determining whether the memory cell is defective while sequentially reading data of all the memory cells after the writing.

In addition, a parallel test control apparatus for a semiconductor memory device according to an embodiment of the present invention includes a cas buffer for outputting a cas signal, a las buffer for outputting a las signal, a write enable buffer for outputting a write enable signal, A decoder which decodes an address from an address buffer, and checks the entry into the parallel test mode by combining the cas signal, the ras signal and the write enable signal, and writes data to all the memory cells in the memory cell array upon entering the parallel test mode. Parallel test control means for determining whether or not the memory cell is defective while writing the data and sequentially reading the data of all the memory cells.

1 is a timing diagram illustrating a parallel test method of a conventional semiconductor memory device;

2 is a block diagram of a parallel test control apparatus for a semiconductor memory device according to an embodiment of the present invention;

3 is an internal circuit diagram of the row decoder shown in FIG.

4 is a structural diagram of a bit line driver applied to an embodiment of the present invention;

FIG. 5 is a timing diagram illustrating parallel test operation timing at the time of high data write / read in a critical name of a parallel test method of a semiconductor memory device according to an exemplary embodiment of the present invention; FIG.

FIG. 6 is a timing diagram illustrating a parallel test operation during low data write / read in the parallel test method of a semiconductor memory device according to an exemplary embodiment of the present invention.

<Description of the reference numerals for the main parts of the drawings>

10: cas buffer 12: las buffer

14: Write enable buffer 16: Address buffer

18: Roo predecoder 20: Column predecoder

22: Roo Decoder 24: Column Decoder

26 memory cell array 28 data input buffer

30: input / output gate 32: bit line sense amplifier

34: data output buffer 36: parallel test control

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a parallel test control apparatus for a semiconductor memory device according to an exemplary embodiment of the present invention, wherein a cas buffer 10 (/ CAS buffer) receives an external cas signal (CAS: Column Address Strobe) and uses an internal CMOS. Converts to a level CAS signal (/ CAS) and provides it to the data input buffer 28 and the parallel test control unit 36. The Lars buffer 12 (/ RAS buffer) provides an external Ras signal (RAS: Row Address Strobe). The input signal is converted into an internal ras signal (/ RAS) having a large driving force and provided to the low predecoder 18 and the parallel test control unit 36. The write enable buffer 14 (/ WE buffer) is externally enabled. The signal WE is received and converted into an internal write enable signal / WE and provided to the data input buffer 28.

The address buffer 16 receives an external address (TTL level address; column address and row address), converts it into an internally usable address (CMOS level address; column address and row address), and outputs the result. The row predecoder 18 receives a row address from the address buffer 16 and transcodes the row address to the row decoder 22, and a column predecoder 20 supplies the address buffer 16. The column address is input to the column decoder 24 by pre-decoding.

The row decoder 22 receives a row address from the row predecoder 18, decodes it, and applies a result to a word line driver (not shown) to drive a corresponding word line in the memory cell array 26. The column decoder 24 receives and decodes the column address from the column predecoder 20 and drives the corresponding bit line in the memory cell array 26 by the result.

The data input buffer 28 receives data D from the outside through the input / output gate 30 in the data input mode by signals from the cas buffer 10 and the write enable buffer 14. 32, and the bit line sense amplifier 32 amplifies the bit line by the drive signals WPTD1 and WPTD2 from the parallel test control unit 36 to be described later and inputs the data through the input / output gate 30. It not only writes data from the input buffer 28 to all the cells in the memory cell array 26, but also provides data of all the cells to the data output buffer 34 through the input / output gate 30, and the data output buffer. Reference numeral 34 sequentially outputs data of all cells in the memory cell array 26 by an output enable signal (OEB) from a main controller (not shown).

The parallel test control unit 36 includes a cas signal (/ CAS) from the cas buffer 10, a ras signal (/ RAS) from the las buffer 12, and a write enable signal from the write enable buffer 14. (/ WE) is input and combined to sense the WCBR situation and provide driving signals WPTD1 and WPTD2 to the bit line sense amplifier 32 upon entry to the parallel test mode (PT → " H ") and the memory cell. Data is written to all the memory cells in the array 26, and the data of all the memory cells is read sequentially to determine the pass / defect of the memory cells. When the parallel test mode is started, the parallel test controller 36 provides a control signal WPTC to disable the operations of the address buffer 16 and the row decoder 18. In the case of the WCBR situation, the CAS signal (/ CAS) and the write enable signal (/ WE) are enabled before the Lars signal (/ RAS), and then the WCBR situation is entered from the time when the Lars signal (/ RAS) is enabled. Once you enter this WCBR situation, the WCBR situation will continue until you exit to CBR or RAS only.

Fig. 3 is an internal circuit diagram of the row decoder 22 employed in the embodiment of the present invention, in which the word line W / L is pulled up by the row address signal (X-dec. Signal) from the row predecoder 18. Figs. The word line W / L is connected to the pull-up element P1 (PMOS transistor) and the pull-up element P1 in series and by a row address signal (X-dec. Signal) from the row predecoder 18. NMOS device (NMOS transistor) which pulls down &lt; RTI ID = 0.0 &gt;) &lt; / RTI &gt; and a light cycle detection signal (WPTB) connected between the pull-down device N1 and the ground voltage terminal and formed in the WCBR situation. A PMOS device P2 connected to the word line W / L and providing a high voltage VPP to the word line W / L by a write cycle detection signal WPTB formed in a WCBR situation. ) And from the main controller (not shown) in the operation enable state of the row decoder 22. NMOS element N3 for driving the word line W / L by the control signal WLC applied at a low level and being disabled ("L") when the ras signal / RAS is enabled. do.

4 is a structural diagram of a bit line driver applied to an embodiment of the present invention, in which one end of a bit line BL is disposed at one end of the bit line pair BL and / BL intersecting the word line. The NMOS transistor N4, which is installed between the ground voltage terminals and switched by the drive signal WPTD1 from the parallel test control unit 36, is installed between the bit line BL and the power supply voltage terminal and is connected to the parallel test control unit 36. A PMOS transistor P3 switched by a drive signal WPTD2 from the circuit board), and at one end of the bit line bar / BL, between the bit line bar / BL and the ground voltage terminal. The NMOS transistor N5 switched by the drive signal / WPTD2 from the parallel test control unit 36 and the bit line bar (/ BL) and the power supply voltage terminal are installed and driven from the parallel test control unit 36. Switched by a signal (/ WPTD1) The PMOS transistor P4 is provided.

According to such a bit line driver structure, the NMOS transistors N4 and N5 and the PMOS transistors P3 and P4 are driven on / off by the driving signals WPTD1 and WPTD2 from the parallel test control unit 36 so as to perform bit line pairing. (BL, / BL) is driven to the power supply voltage level Vdd or the ground voltage level Vss.

Next, the operation of the parallel test control apparatus for the semiconductor memory device according to the exemplary embodiment of the present invention configured as described above will be described based on the operation timing diagrams of FIGS. 5 and 6.

First, a case of writing / reading high data will be described with reference to FIG. 5. The cas signal (/ CAS) from the cas buffer 10 and the ras signal (/ RAS) and the write in from the las buffer 12 are described. When the WCBR situation is caused by the combination of the write enable signal / WE from the enable buffer 14, and the signal PT indicating the entry into the parallel test mode becomes high, the parallel test control unit 36 performs an address buffer. The control signal WPTC is applied to the 16 and the row decoder 22 to make the operation disable state. That is, when the row address signal (X-dec. Signal; see FIG. 3) is at the low level and the word line boosting signal pxi is at the ground voltage Vss level, the PMOS device P2 is turned on in the parallel test mode. The high voltage VPP on the word line W / L is pulled out to the input terminal of the word line boosting signal pxi through the pull-up element P1. In other words, although the word buffer W / L should be turned on in the parallel test mode, when the address buffer 16 operates and the address is supplied to the row decoder 22, the pull-down element N1 turns on. Since the word line W / L is turned off, the operation of the address buffer 16 and the row decoder 22 is disabled in the parallel test mode.

On the other hand, a write cycle detection signal (WPTB) which is a signal for recognizing a cycle for performing a write operation on a cell is a signal in which a write enable signal (/ WE) is low in a WCBR situation) and the cas signal (/ CAS). As the parallel test control section 36 is generated by the combination of the enable signal / WE, the parallel test control section 36 sends the drive signals WPTD1 and WPTD2 to the bit line sense amplifier 32, and the bit line. The sense amplifier 32 receives the data D input to the data input buffer 28 through the input / output gate 30 and writes all the memory cells in the memory cell array 26. At this time, since the data D input to the data input buffer 28 is high level, high data is written to all the memory cells.

That is, the write cycle detection signal WPTB (low level signal) in the parallel test control unit 36 is applied to the row decoder 22 (see FIG. 3) to turn on only the PMOS device P2 to thereby turn on the word line W / L. ) Is enabled by applying a high voltage (VPP). In the high data write operation, since the driving signals WPTD1 and WPTD2 of the parallel test controller 36 are low, only the PMOS transistor P3 and the NMOS transistor N5 in FIG. 4 are turned on to turn on the bit line BL. Make it high level (Vdd) and make bitline bar (/ BL) low level (Vss). Accordingly, high data is simultaneously loaded in all memory cells.

Thereafter, when the 32 high data are read, the data output buffer 34 reads and compares 32 high data one by one as the operation is enabled at a predetermined time interval by the output enable signal (OEB). Pass, if different, will be determined as a failure.

On the contrary, with reference to FIG. 6, the case of writing / reading the raw data will be described. WCBR situation is based on the combination of the CAS signal / CAS, the ras signal / RAS, and the write enable signal / WE. When the parallel test mode is entered, the parallel test control unit 36 disables operations of the address buffer 16 and the row decoder 22. Meanwhile, as the write cycle detection signal WPTB is generated by the parallel test control unit 36 by the combination of the cas signal / CAS and the write enable signal / WE, the parallel test control unit 36 generates a drive signal. (WPTD1, WPTD2) are sent to the bit line sense amplifier 32, and the bit line sense amplifier 32 receives the data D input to the data input buffer 28 through the input / output gate 30 and the memory cell. Writes to all memory cells in array 26. At this time, since the data D input to the data input buffer 28 is at the low level, the low data is written to all the memory cells.

That is, since the word line W / L is enabled by the write cycle detection signal WPTB in the parallel test control unit 36 and the low data must be written, the drive signal in the parallel test control unit 36. (WPTD1, WPTD2) are made high and only the NMOS transistor N4 and PMOS transistor P4 in FIG. 4 are turned on by the high-level driving signals WPTD1 and WPTD2 to turn the bit line BL low. Make level (Vss) and make bitline bar (/ BL) high level (Vdd). As a result, row data is simultaneously loaded in all memory cells.

Thereafter, when the 32 low data are read, the data output buffer 34 reads and compares the 32 low data one by one as the operation is enabled at a predetermined time interval by the output enable signal (OEB). Pass, if different, will be determined as a failure.

According to the present invention as described above, the test time is drastically reduced by reducing the number of cycles written to all memory cells of 64 megabits by 32 bits in one cycle.

On the other hand, the present invention is not limited only to the above-described embodiments, but may be modified and modified without departing from the scope of the present invention.

Claims (7)

In a parallel test method of a semiconductor memory device for testing all the memory cells in the memory cell array, Writing data to all of the memory cells by blocking input paths of row and column addresses as the parallel test mode is entered; And sequentially reading data of all the memory cells after the writing, and determining whether or not the memory cells are defective. The method of claim 1, And writing data to all of the memory cells is performed in an enable section of a write cycle detection signal. The method of claim 2, And the write cycle detection signal is enabled in a WCBR situation and disabled when the write enable signal is disabled. A cas buffer that outputs a cas signal; A lath buffer for outputting a lath signal, A write enable buffer for outputting a write enable signal; A decoder for decoding the address from the address buffer, The entry into the parallel test mode is checked by the combination of the cas signal, the ras signal, and the write enable signal. When the parallel test mode is entered, data is written to all the memory cells in the memory cell array, and the data of all the memory cells is written. And parallel test control means for determining whether a memory cell is defective while being sequentially read. The method of claim 4, wherein And the parallel test control means controls the address buffer and the decoder to be disabled in the parallel test mode. The method of claim 4, wherein And said parallel test control means controls to write data to all memory cells in an enable period of the write cycle detection signal generated by the combination of the cas signal, the ras signal and the write enable signal. Parallel test controls. The method of claim 6, And the write cycle detection signal is enabled in a WCBR situation and disabled when the write enable signal is disabled.