KR20000025633A - Method for forming contact of semiconductor device - Google Patents

Abstract

PURPOSE: A method is provided to solve the problem of a resistance increase of the source/drain region and to reduce a junction leakage current by forming a TiSi2 of a low resistance through a thermal annealing process. CONSTITUTION: A device isolation layer(12), a gate insulation layer(13), a gate electrode(14),a gate electrode spacer(15), and a source/drain region are formed on a semiconductor substrate(11). The source/drain region(17) are activated by carrying out a thermal annealing process. The gate electrode(14) and the source/drain region(17) are amorphized by injecting germanium ions. Ionized titanium(18) is deposited. Silicide is formed by carry out a thermal annealing process, to thereby reduce a junction leakage current and to maximize an operation speed of a device.

Description

Contact formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact of a word line and an active region of a semiconductor device.

In general, polysilicon doped with electrodes of word lines has been used in semiconductor devices. However, due to the high specific resistance of polysilicon, a technology using a double layer of tungsten silicide (WSix) and polycrystalline silicon has been developed, thereby lowering the resistivity to some extent. However, the specific resistance of the tungsten silicide thin film is still about 100 μΩcm, and thus the specific resistance of the tungsten silicide thin film is limited in reducing the resistance of the word line and the contact for the next generation device development. Therefore, research is being conducted to reduce the resistance of the word line as much as possible by replacing the tungsten silicide with a titanium silicide thin film having a specific resistance of about 13-20 μΩcm. In addition, titanium silicide has been applied to logic devices by enabling self-aligned silicide (salicide) in the word line of polycrystalline silicon and the source / drain region of doped single crystal silicon.

However, as the design rule of the device becomes smaller than 0.25 µm, the phase transformation temperature to C54 TiSi2 having a low resistance of the titanium silicide thin film formed on the word line and the source / drain is increased (900 ° C). In addition, even at such a high temperature, some TiSi2 remains as C49 TiSi2 without being transformed into the C54 phase, thereby making it difficult to secure a sufficiently low resistance value. Recently, in order to solve this problem, Si and As are ion-implanted in the gate and source / drain regions before and after Ti deposition to pre-amorphize polycrystalline silicon or source / drain regions to change the phase to C54. Research is underway to provide nucleation sites to form low-resistance TiSi2 at narrow temperatures, even at relatively low temperatures (750-850 ° C). However, Si acts as a source of leakage current by forming a wide layer of defect layers on the substrate during amorphous phase, while As has the effect of counterdoping in the active region of the PMOS, so that the source / drain sheet There was a problem of increasing resistance and contact resistance.

The present invention devised to solve the above-described problems, the present invention is to minimize the resistance in the contact occurs when forming a contact line and a self-aligned silicide contact using TiSi ₂ in the polysilicon word line and the source / drain region having a narrow line width and In order to lower the phase change temperature, it is an object of the present invention to provide a method for forming a contact of a semiconductor device for depositing germanium (Ge) ions and ionized titanium on a silicon surface and forming a low resistance TiSi ₂ contact through a heat treatment process. .

In an embodiment, a contact forming method of a semiconductor device may include forming an isolation layer, a gate insulating film, a gate electrode, a gate electrode spacer, and a source / drain region on a semiconductor substrate; Performing a thermal process to activate the source / drain regions; Performing germanium ion implantation to amorphousize the gate electrode and the source / drain region; Depositing ionized titanium; And forming a silicide by performing a heat treatment process.

In another embodiment, a method of forming a contact for a semiconductor device may include forming an isolation layer, a gate insulating film, a gate electrode, a gate electrode spacer, and a source / drain region on a semiconductor substrate; Performing a thermal process to activate the source / drain regions; Performing germanium ion implantation to amorphousize the gate electrode and the source / drain region; Depositing an interlayer insulating film over the entire structure; Forming a contact hole in a predetermined portion; Cleaning the contact hole; Depositing ionized titanium; And forming a silicide by performing a heat treatment process.

1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device contact according to an embodiment of the present invention.

2 is a process cross-sectional view of a method of forming a semiconductor device contact according to another embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

11: Substrate 12: Device Separator

13: gate insulating film 14: gate electrode

15: Spacer 16: Mask

17: source / drain region 18: titanium film

19: Ge 20: TiSi ₂

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, as shown in FIG. 1A, an isolation layer 12 is formed on a semiconductor substrate 11 by using a field oxidation (FOX) or shallow trench isolation (STI) technique, and a gate dielectric ( 13) is deposited to a thickness of about 10-200Å. As the gate insulating film, a silicon oxide film, a silicon nitride film, a stacked structure of a silicon oxide film and a silicon nitride film, or a tantalum oxide film (Ta2O5) can be used. After the doped polysilicon is deposited to a thickness of about 100-2000 microns, the gate electrode 14 is formed by patterning the polysilicon using a wordline mask, and the spacer 15 is formed on the sidewall of the gate electrode 14. To form. At this time, the deposition of polycrystalline silicon using As, AsH3, Sb in the case of N-type, B, BF2, Ga, In in the case of P-type, in-situ by ion implantation and chemical vapor deposition (in -situ).

Next, as shown in FIG. 1B, ion implantation is performed using the mask 16 for forming the active region to form the source / drain 17 and perform a thermal process for activation. In this case, when the source / drain region is an N + layer, As, AsH3, P, PH3, Sb, and the like are used. In the case of the P + layer, B, BF2, Ga, and In are used. And, the thermal process for activation may be carried out at a temperature of about 850-1100 ℃, using a conventional furnace (furnace) or using an RTA reactor (reactor). When using a conventional reactor, a ramp up rate of 5-100 ° C./min is appropriate, and in the case of an RTA reactor, a ramp up rate of 20-150 ° C./min is appropriate.

Next, as shown in FIG. 1C, blanket implantation is performed using GE. In this case, a germanium (Ge) pre-amorphization process may be performed to amorphous the word line and the active region of the polycrystalline silicon, and Ge may be GeF4 or GeH4 gas, and a solid source may be used. Elemental Ge pellets are used by evaporation. In this case, the dosage of 8E13-4E15 and energy of 5-50 keV are used.

As shown in FIG. 1D, the ionized titanium 18 is simultaneously deposited on the word line (gate electrode) and the active region (source / drain) to form a self-aligned silicide (salicide). The TiSi2 film 19 on C49 is formed by deposition and rapid thermal annealing (RTA). At this time, the ionized Ti is deposited to a thickness of about 50-750 kPa by the sputtering method using a Ti target, wherein the substrate temperature is suitably 20-550 ℃. In addition, the power for sputtering is 500W to 4kW, an ionizer is provided between the target and the substrate for Ti ionization, and an ionizer is applied to the ionizer to facilitate ionization. The RF bias power at this time is 100-4000W, the voltage is 50-200V is appropriate. Prior to depositing Ti, the native oxide film is preferably removed using HF-based BOE (Buffered Oxide Etchant) or diluted HF. RTA process may be carried out over 2-3 orders, the first RTA temperature is 600-730 ℃, the heat treatment atmosphere may be used N2, NH3, Ar, He or a combination thereof, the flow rate is 1 -5 SLPM (standard liter per minute), ramp-up rate is 20-150 ℃ / min. Next, a second RTA process may be performed at a temperature of 700-750 ° C.

Next, when unreacted Ti / TiN is removed, a structure as shown in Fig. 1E is obtained, and then a series of RTA treatments are performed to form a TiSi 2 film 20 having a C54 phase. do. At this time, unreacted Ti / TiN is removed by using NH 4 OH: H 2 O 2: DI (Deionized water) at a ratio of 1: 1: 3-10, and TiN reacted with Ti or N at a portion not in contact with Si is All can be eliminated using selective etching. In this case, in order to form a low-resistance TiSi2 thin film, after the selective etching process, the RTA process may be performed at a temperature of about 700-900 ° C.

The contact forming method of the present invention can be applied to a wiring process including contact embedding of word lines, bit lines, and sources / drains in a peripheral region of a memory device or a CMOS of an MML device. At this time, as shown in FIG. 2, after the insulating film 22 is deposited after FIG. 1C, a deep contact hole is formed, contact cleaning is performed, ionized Ti deposition is completed, and a low temperature heat treatment (750-800). TiSi2 (23) having a C54 phase is formed through (C). Thereafter, a metal diffusion film (TiN) is deposited by a conventional process, and then a conventional metallization process such as tungsten plugging and A1 wiring may be performed. Further, in another embodiment of the present invention, a self-aligned silicide process may be performed only in the source / drain region except for the word line. In this case, a mask oxide film may be deposited on the word line.

According to the present invention as described above, the following advantages can be obtained through the pre-amorphization process through ion implantation of Ge and the deposition process of ionized titanium.

First, Ge is a material with tetravalent outermost electrons, which is neutral in the active region of the Si PMOS device at the time of ion implantation, resulting in the source / effect of anti-doping brought about by the pre-amorphization method using As. The problem of increasing the resistance of the drain region can be solved.

Second, since the thickness of the damaged layer between the amorphous layer and the substrate formed during ion implantation is thinner than that of Si and As, Ge may reduce junction leakage current.

Third, a thin TiSix amorphous layer is formed on the substrate by the self-bias effect during the deposition of ionized titanium, and thus has a low activation energy when silicide is formed, thereby forming a TiSi2 film having low resistance even in a low temperature heat treatment process. Can be. In addition, by applying a bias between the ionized Ti particles and the substrate, it is possible to control the depth of the amorphous layer, and to obtain a good bottom coverage even in the application of deep contact.

Therefore, since the sheet resistance, contact resistance, parasitic resistance, etc. of the source / drain or word line of the semiconductor device can be reduced, there is an effect of maximizing the operation speed of the device and securing a reliable process technology.

Claims (8)

In the contact formation method of a semiconductor element, Forming a device isolation film, a gate insulating film, a gate electrode, a gate electrode spacer, a source / drain region on a semiconductor substrate; Performing a thermal process to activate the source / drain regions; Performing germanium ion implantation to amorphousize the gate electrode and the source / drain region; Depositing ionized titanium; And Performing a heat treatment process to form silicide Contact forming method of a semiconductor device comprising a. The method of claim 1, GeF4 or GeH4 gas is used as the source of germanium, and the elemental germanium pellet is evaporated and used as a solid source. Method for forming a contact of a semiconductor device. The method according to claim 1 or 2, The germanium ion implantation is performed using an ion implantation amount of 8E13-4E15 and an ion implantation energy of 5-50 keV. Method for forming a contact of a semiconductor device. The method of claim 1, The step of depositing the ionized titanium, Ti target under the process conditions of 20-550 ℃ substrate temperature, 500W to 4kW power, 100-4000W ionizer RF bias power, 50-200V ionizer RF bias voltage Characterized by the sputtering method using Method for forming a contact of a semiconductor device. The method of claim 4, wherein The titanium is deposited to a thickness of about 50-750Å Method for forming a contact of a semiconductor device. The method of claim 1, Before depositing the titanium, further comprising removing the native oxide film using a BOE or diluted HF solution. Method for forming a contact of a semiconductor device. The method of claim 1, Forming the silicide by performing the heat treatment process is characterized in that carried out using a rapid heat treatment process Method for forming a contact of a semiconductor device. In the contact formation method of a semiconductor element, Forming a device isolation film, a gate insulating film, a gate electrode, a gate electrode spacer, a source / drain region on a semiconductor substrate; Performing a thermal process to activate the source / drain regions; Performing germanium ion implantation to amorphousize the gate electrode and the source / drain region; Depositing an interlayer insulating film over the entire structure; Forming a contact hole in a predetermined portion; Cleaning the contact hole; Depositing ionized titanium; And Performing a heat treatment process to form silicide Contact forming method of a semiconductor device comprising a.