KR20000024754A - Method for manufacturing semiconductor device using metal salicide - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device using metal salicide is provided to form a salicide to a DRAM cell region, ensure a mis-alignment margin, and apply SAC(self-alignment contact) process. CONSTITUTION: A method for manufacturing a semiconductor device forms a gate electrode(106) on a semiconductor substrate of a cell area and peripheral area. A first conductive layer and a first material layer are sequentially deposited. A second material layer is formed on the semiconductor substrate(100) and the gate electrode. A first interlayer insulation layer is formed on the semiconductor substrate. The first interlayer insulation layer and the second material layer are evenly etched until the first material layer is exposed. A first material layer on the first conductive layer is removed by a wet-type etching process. A metal salicide layer(110,114) is formed on the first conductive layer. A third material layer having an etching selection ratio with the first interlayer insulation layer is formed on the semiconductor substrate, and a thicker thickness than that of the second material layer by 1.5 times. A third material layer of a gate electrode's both sides is etched so as to be parallel with the third material layer. A second interlayer insulation layer is formed on the semiconductor substrate. The second and first interlayer insulation layer are sequentially etched until the third and second material layers are exposed by using a contact hole forming mask, thereby a self-alignment contact hole(120) is formed.

Description

METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING METAL SALICIDE

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a metal salicide.

Recently, the development of embedded DRAM (EMBEDDED DRAM) (MDL), which combines a DRAM cell array and a logic circuit into one chip, is being actively performed. In this case, a metal salicide formation process is essential to improve the speed of the logic portion.

The salicide formation process of the DRAM cell array portion has a problem that the doping concentration of the source / drain region is low and becomes very difficult due to deterioration of the refresh function after the salicide formation. However, in order to improve the data access time of DRAM, the resistance of the word line (gate electrode in the cell region) must be lowered. For this purpose, the salicidation process of the polysilicon film, which is a conductive film for forming the gate electrode, is performed. It is essential. In addition, the salicide process should be applied to improve the speed of development of next generation high performance DRAM.

In order to solve the above problems, the following process is performed.

First, a polysilicon film and a gate mask are sequentially stacked on a semiconductor substrate in a cell region and a peripheral region. Subsequently, the gate electrode is formed by sequentially etching the gate mask and the polysilicon film until the surface of the semiconductor substrate is exposed using the gate electrode forming mask.

Next, an insulating film spacer is formed on both sidewalls of the gate electrode by etching the entire surface of the silicon nitride film on the semiconductor substrate including the gate electrode by an etch back process. Then, a MOS transistor is formed by implanting impurity ions into the semiconductor substrate on both sides of the insulating film spacer.

A thin interlayer insulating film is deposited on the entire surface of the semiconductor substrate. Subsequently, the source / drain region in which the salicide is to be formed is exposed by etching the interlayer insulating layer in the peripheral region using the photoresist layer pattern, and the surface of the polysilicon layer is removed by etching the interlayer insulating layer and the mask nitride layer in the DRAM cell array. Exposed. After forming one of the Co film and the Ti film along the structures formed on the semiconductor substrate and performing a salsa sidization process, a salicide film is formed in the DRAM cell region by removing the unreacted metal film to form a salicide. Can be.

However, as the semiconductor memory device is highly integrated, the width of the gate electrode is reduced, and as a result, the misalignment margin is also reduced during the etching process of etching the gate mask to expose the polysilicon film of the cell region. It is difficult to apply during the manufacturing process.

In addition, after forming the salicide by performing the above process, it is difficult to apply a self-aligned contact (SAC) process to a subsequent DRAM cell array portion. Specifically, since the polysilicon film is exposed by removing the gate mask, a salicide is formed, so that the salicide film becomes an upper layer of the gate electrode. This means that it is difficult to apply a so-called SAC process that requires a hard mask having a selectivity with the interlayer insulating film such as a silicon nitride film on the gate electrode.

As a result, the conventional metal salicide formation method described above has a problem that it is difficult to apply in a highly integrated DRAM cell which essentially uses SAC.

The present invention has been proposed to solve the above-mentioned problems, using a metal salicide that can secure misalignment margin while applying a metal salicide to a cell region, and can apply a subsequent self-aligned contact (SAC) process. Its purpose is to provide a method for manufacturing a semiconductor device.

1A to 1F are flowcharts sequentially illustrating processes of a method of manufacturing a semiconductor device using a metal salicide according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100 semiconductor substrate 102 device isolation region

106: gate electrode 110, 114: salicide film

112, 118: interlayer insulating film 105, 116: gate mask

120: long-term alignment contact hole 122: contact plug

(Configuration)

According to the present invention for achieving the above object, in the method of manufacturing a semiconductor device using a metal salicide, a gate electrode in which a first conductive film and a first material film are sequentially stacked on a semiconductor substrate in a cell region and a peripheral region is formed. Making a step; Forming a second material layer on the semiconductor substrate including the gate electrode; Forming a first interlayer insulating film on the entire surface of the semiconductor substrate; Etching the first interlayer insulating film and the second material film evenly until the surface of the first material film is exposed; Removing the first material film on the first conductive film by a wet etching process; Forming a metal salicide film on the first conductive film; Forming a third material film having an etch selectivity with the first interlayer insulating film on an entire surface of the semiconductor substrate, wherein the third material film has a thickness of about 1.5 times or more than the thickness of the second material film; Etching the third material film on both sides of the gate electrode to be parallel to the third material film on the gate electrode; Forming a second interlayer insulating film on the entire surface of the semiconductor substrate; Forming a self-aligned contact hole by sequentially etching the second and first interlayer insulating films until the surfaces of the third and second material films are exposed using a contact hole forming mask.

In a preferred embodiment of the method, the method may further include forming a metal salicide film on a semiconductor substrate on both sides of the gate electrode in a peripheral region before forming the first interlayer insulating film.

In a preferred embodiment of the method, after forming the self-aligned contact hole, forming an insulating film spacer on the sidewall of the gate electrode by etching the third and second material film in the self-aligned contact hole; The method may further include forming a contact plug by filling the contact hole with a second conductive layer.

(Action)

1C and 1E, in a method of manufacturing a semiconductor device using a novel metal salicide according to an embodiment of the present invention, a first conductive film and a first material film are sequentially formed on a semiconductor substrate in a cell region and a peripheral region. A second material layer is formed on the semiconductor substrate including the stacked gate electrodes. After the first interlayer insulating film is formed on the entire surface of the semiconductor substrate, the first interlayer insulating film and the second material film are etched flat until the surface of the first material film is exposed. Subsequently, the first material film on the first conductive film is removed by a wet etching process, and a metal salicide film is formed on the first conductive film. Next, a third material film having an etch selectivity with the first interlayer insulating film is formed on the entire surface of the semiconductor substrate, and is formed to have a thickness of about 1.5 times or more than the thickness of the second material film. The self-aligned contact hole is formed by sequentially etching the second and first interlayer insulating films until the surfaces of the third and second material films are exposed using the contact hole forming mask. In this method of manufacturing a semiconductor device using a metal salicide, misalignment margin can be secured by removing the gate mask by a strip process rather than a photo process, and a mask having an interlayer insulating film and an etching selectivity after forming a salicide layer is formed. By forming, a subsequent SAC process can be applied.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1A to 1F.

1A to 1F are flowcharts sequentially illustrating processes of a method of manufacturing a semiconductor device using a metal salicide according to an embodiment of the present invention.

Referring to FIG. 1A, a method of fabricating a semiconductor device using a metal salicide of the present invention, first, device isolation region 102 for defining an active region and an inactive region in a semiconductor substrate 100 having a cell region and a peripheral region. Is formed. The device isolation region 102 is specifically formed of shallow trench isolation (STI).

Subsequently, a well region is formed by implanting impurity ions into the semiconductor substrate 100, and a threshold voltage of the transistor is controlled. Thereafter, a polysilicon film 104 and a gate mask 105 are sequentially formed on the semiconductor substrate 100 with a gate oxide film (not shown) interposed therebetween. Subsequently, the gate mask 106 is formed by sequentially etching the gate mask 105 and the polysilicon film 104 using a gate electrode forming mask.

The silicon nitride film 108 is formed on the semiconductor substrate 100 including the gate electrode 106 within a thickness range of 30 nm to 70 nm. Next, after the peripheral region except for the cell region is opened using a mask (not shown), the insulating layer spacer 108a is formed on both sidewalls of the gate electrode 106 formed in the peripheral region by etching the entire surface by an etch back process. ) Is formed as shown in the drawing.

In FIG. 1B, after removing the mask, source / drain regions are formed by implanting impurity ions into the semiconductor substrate 100. Next, after depositing a metal film along the structures formed on the semiconductor substrate 100, the salicide layer 110 is formed by performing a salicidation process. Subsequently, the unreacted metal is removed. The metal film is any one of a Co film and a Ti film.

The salicide film forming process of forming a salicide film after removing a gate mask after forming a gate electrode is a process performed when the metal film used is one of the Co film and the Ti film.

In this case, the salicide layer 110 is a layer formed to improve the speed of the device, and as described above, the source / drain region of the cell region has a low doping concentration and is refreshed after formation of the salicide layer. It is not formed by exposing the substrate to the silicon nitride film because the function is deteriorated, but is formed in the source / drain region of the peripheral region.

Then, an interlayer insulating film 112 is formed on the entire surface of the semiconductor substrate 100 as an oxide film. Subsequently, the interlayer insulating layer 112 and the silicon nitride layer 108 in the cell region are etched flat by a chemical mechanical polishing (CMP) process until the surface of the gate mask 105 is exposed. In this case, the oxide film and the silicon nitride film 108 which are the interlayer insulating film 112 do not have an etching selectivity.

Referring to FIG. 1C, the surface of the polysilicon film 104 is exposed by performing a phosphate strip (H ₃ PO ₄ strip) process to remove the gate mask 105. That is, the gate mask 105 on the polysilicon film 104 can be removed without performing a photo process, thereby ensuring a misalignment margin. At this time, some thicknesses of the silicon nitride film 108 on both sides of the gate mask 105 are also etched.

Next, a salicide film forming process for improving data access time of a DRAM is performed by reducing the resistance of the gate electrode on the polysilicon film 104. Specifically, after depositing a metal film along the structures formed on the semiconductor substrate 100, by performing a salsaside process, the metal film reacts with the polysilicon film 104 of the gate electrode 106 to metal salicide A film 114 is formed. Subsequently, the metal film not reacted with the polysilicon film 104 is removed. The metal film is any one of a Co film and a Ti film, and is deposited in a thickness range of 5 nm to 20 nm.

In FIG. 1D, a silicon nitride film 116 is deposited on the entire surface of the semiconductor substrate 100 by a chemical vapor deposition (CVD) process. The silicon nitride film 116 is deposited about 1.5 times thicker than the thickness of the silicon nitride film 108 deposited in FIG. 1A.

Subsequently, the silicon nitride film 116 except for the silicon nitride film 116 deposited on the gate electrode 106 is removed by a CMP process. Then, a second interlayer insulating film 118 is formed on the entire surface of the semiconductor substrate 100. Thereafter, the contact forming process is performed in a damascene process. Specifically, the self-aligned contact holes are sequentially etched by sequentially etching the first and second interlayer insulating films 112 and 118 until the surfaces of the silicon nitride films 108 and 116 in the cell region are exposed using a contact hole forming mask. 120 is formed.

The etching process for forming the self-aligned contact hole 120 is performed by a typical SAC process in which the oxide and silicon nitride layers, which are the interlayer insulating films 112 and 118, have different etching selectivity. Therefore, even when the contact hole forming mask is misaligned during the etching for forming the self-aligned contact hole 120, even when the contact hole 120 is formed, as shown in FIG. The side film 114 is not exposed. That is, misalignment margin can be secured.

Next, an insulating layer spacer is formed on the sidewall of the gate electrode 106 by etching the silicon nitride layers 108 and 116 in the self-aligned contact hole 120 by an etch back process until the surface of the semiconductor substrate 100 is exposed. do. In this case, the thickness B of the silicon nitride film 116 formed on the gate electrode is greater than the thickness A of the silicon nitride film 108 formed on the semiconductor substrate 100 on both sides of the gate electrode 106. It is formed about 1.5 times thicker to prevent exposure of the silicide layer 114 during etching for forming the insulating layer spacer. Therefore, the SAC process may be applied to the highly integrated DRAM cell due to the mask layer 116 on the salicide layer 114.

After filling the self-aligned contact hole 120 with a polysilicon film, the contact plug 122 is electrically connected to the semiconductor substrate 100 by forming a flat etching, as shown in FIG. 1F. Subsequently, subsequent processes such as bit lines, storage nodes, and metal wiring processes are performed (not shown in the figure).

The present invention solves the problem that the misalignment margin is reduced during the gate mask etching process for forming a salicide layer, and that the SAC process cannot be applied after the salicide layer is formed. In this case, the misalignment margin can be secured, and a subsequent SAC process can be applied by forming a mask having an etch selectivity with an interlayer insulating film after forming a salicide film.

Claims (7)

Forming a gate electrode in which a first conductive film and a first material film are sequentially stacked on a semiconductor substrate in a cell region and a peripheral region; Forming a second material layer on the semiconductor substrate including the gate electrode; Forming a first interlayer insulating film on the entire surface of the semiconductor substrate; Etching the first interlayer insulating film and the second material film evenly until the surface of the first material film is exposed; Removing the first material film on the first conductive film by a wet etching process; Forming a metal salicide film on the first conductive film; Forming a third material film having an etch selectivity with the first interlayer insulating film on an entire surface of the semiconductor substrate, wherein the third material film has a thickness of about 1.5 times or more than the thickness of the second material film; Etching the third material film on both sides of the gate electrode to be parallel to the third material film on the gate electrode; Forming a second interlayer insulating film on the entire surface of the semiconductor substrate; Using a metal salicide, including forming a self-aligned contact hole by sequentially etching the second and first interlayer insulating films until the surfaces of the third and second material films are exposed using a contact hole forming mask. The manufacturing method of a semiconductor device. The method of claim 1, Forming a metal salicide film on a semiconductor substrate on both sides of the gate electrode in a peripheral region before forming the first interlayer insulating film. The method of claim 1, After forming the self-aligned contact hole, etching the third and second material layers in the self-aligned contact hole to form an insulating film spacer on the sidewall of the gate electrode; And forming a contact plug by filling the contact hole with a second conductive layer. The method of claim 1, The first and second conductive films are polysilicon films, and the first, second and third material films are silicon nitride films. The method of claim 1, The wet etching process is a method of manufacturing a semiconductor device using a metal salicide is performed with a phosphoric acid solution. The method of claim 1, The metal salicide film is a semiconductor device manufacturing method using a metal salicide, which is one of a Co film and a Ti film. The method of claim 1, The third material film is a semiconductor device manufacturing method using a metal salicide is deposited by a chemical vapor deposition (CVD) process.