KR20000022281A - Methods and apparatuses for clamping and declamping a semiconductor wafer in a wafer processing system - Google Patents

Abstract

PURPOSE: An apparatus is provided for the improved method clamping and declamping a semiconductor wafer in the processing chamber of a wafer processing system, and for clamping a wafer to an electrostatic chuck having a substantially resistive dielectric layer disposed thereon. CONSTITUTION: The apparatus relates to the production of semiconductor device. The method includes the step of providing a build up voltage having a first polarity to a pole of the electrostatic chuck to cause a potential difference to build up between a first region of the substantially resistive dielectric layer and a second region of the wafer that overlies at least a portion of the first region. The potential difference gives rise to a clamping force to clamp the wafer to the electrostatic chuck. The method further includes the step of terminating the build up voltage when the clamping force substantially reaches a predefined level. There is further included the step of providing a holding voltage to the pole of the electrostatic chuck to substantially maintain the clamping force at the predefined level. The holding voltage has the first polarity and a magnitude that is lower than a magnitude of the build up voltage.

Description

A method and apparatus for clamping and declamping semiconductor wafers in a wafer processing system.

The use of electrostatic chucks in semiconductor wafer processing systems is known. For illustrative purposes, FIG. 1 illustrates a plasma processing system 100 by way of example: etching, oxidation, anodization, chemical vapor deposition (CVD), and semiconductors. It represents a semiconductor wafer processing system that can be used for other processes related to wafer fabrication. Although the plasma processing system 100 by way of example has been described in detail herein to facilitate understanding of the advantages of the present invention, the present invention itself is a particular type of wafer processing apparatus. It should be noted that the present invention is not limited to, but can be applied to use in any type of known wafer processing system, such as deposition, oxidation, anodic oxidation, (dry etching and plasma etching, reactive ion etching (RIE). ), Including magnetically enhanced reactive ion etching (MERIE), electron cyclotron resonance (ECR), etc.), and the like, and the like.

As described, in general, the plasma processing system 100 includes a plasma processing chamber 102, a first radio frequency power supply 104. Second radio frequency power supply 106, and the like. In the plasma processing chamber 102, a shower head 110, an electrostatic chuck 112, and the like may be installed. In general, the shower head 110 is used to distribute source etchant gas into the plasma region 103 of the plasma processing chamber 102, the shower head 110 being quartz and It can be made of the same non-conductive material.

When a voltage is applied to one or both of the radio frequency power supplies 104, 106, the plasma is created in the plasma region 103 outside of the source corrosive gas. Wafer 108 is mounted on top of the electrostatic chuck 112 that is processed by the plasma. The electrostatic chuck 112 may be made of a suitable conductive material, such as an aluminum alloy, and the electrostatic chuck 112 may have a number of configurations, including monopolar and bipolar configurations. At the top surface of the electrostatic chuck 112, generally a dielectric layer 116 may be installed. Between the electrostatic chuck 112 and the wafer 108 or the like, a heat transfer gas such as helium may be supplied under pressure to the wafer / chuck interface through the port 109. To facilitate the control of wafer temperature during processing, the heat transfer gas acts as a heat transfer medium between the wafer 108 and the electrostatic chuck 112 and the like.

As the term is used herein, when an electrostatic chuck has only one pole, it is said that the electrostatic chuck has a monopolar configuration. In another aspect, a bipolar configuration has two poles. In the example of FIG. 1, a toroidal pole is inserted into the base pole and electrostatically insulated from the base pole, ie, a donut and As a bipolar chuck with a donut-and-base configuration, the electrostatic chuck 112 is represented. Other bipolar chuck configurations also exist, including a third electrode that is floating, grounded, or insulated. As an example, FIG. 2 shows a variation known as an interdigitated configuration, or a comb configuration, such as a comb. Looks like weaves

Electrostatic force is induced by the DC power supply 114 for the purpose of clamping the wafer 108 securely to the electrostatic chuck 112 during processing. In the bipolar chuck 112 according to the example of FIG. 1, the poles 115A, 115B and the like are biased with a direct current potential having opposite polarity. As an example, the pole 115A is biased positively, and the pole 115B is biased negatively, or vice versa. The potential difference between the top surface of the pole and the area above the wafer top surface that corresponds to the top surface of the wafer is made by the direct current potential at each electrostatic pole. This creates an electrostatic force to receive the wafer into the electrostatic chuck.

In the prior art, any dielectric layer 116 may be formed of a substantially resistive dielectric material. When biasing the electrostatic chuck poles associated with the dielectric layer with direct current potential, this substantially resistive dielectric layer exhibits the Johnson-Rahbeck effect. In general, the electrostatic clamping effect requires a force to be prepared across the interface between the chuck surface and the wafer clamped to the chuck. If a monopolar chuck is used, the electric field can be applied between only one electrode, through an insulating dielectric layer and an interface gap to the wafer. In such a system, the charging circuit can be completed through plasma.

In monopolar configurations, charge is generally added and removed when plasma is present. In addition, as in the usual case, there is a difference in the plasma between the surfaces of the plasma facing and the like. If a bias occurs, the bias can act to change the clamping force so that it changes to increase or decrease the electric field in the gap. For the purpose of reducing this effect, it is common to offset the clamping potential applied to maintain the electric field at the required level.

Bipolar chucks are constructed by having chuck electrode regions at two electrodes in such a way that different potentials can be applied without the presence of plasma. It is preferred to make the wafer slightly conductive so that the induction charge can be re-distributed between the two poles. In addition, in order to equalize the electric field applied by the poles, the two poles can be equal in area, ie in a balanced configuration. However, the electric field applied by the poles of the bipolar chuck configuration can also be changed and exist in the d.c. The bias can cause the balance to break. In this case, for example, the electrostatic force applied by one pole may be greater than the force applied by the other pole of the bipolar chuck. As a result, bias cancellation is also required in bipolar chuck configurations.

Johnson-Rahbeck chucks can have either a monopolar or bipolar configuration and are generally constructed using semi-conductive lasers instead of conventional high resistive dielectrics. In conventional high resistive dielectrics, the potential is divided across the dielectric layer and the interface gaps, etc., so that only a portion of the potential appears at the surface of the chuck, and therefore the electric field can be reduced below the substantially maximum possible value. Since the clamping force is generally scaled to the square of the electric field, the clamping force can also be reduced.

When the potential is charged across the Johnson-Rahbeck dielectric layer, current flows. In a chuck system, it is possible for the charge to be transferred to the dielectric-wafer interface. As a result, the electric field and the clamping force are increased as a function of time. In general, the increase occurs at a time constant proportional to the dielectric resistance and the capacitance from the wafer to the chuck, and the increase charges. The treatment takes into account the susceptibility of the Johnson-Rahbeck chuck to wafer sticking as well as the high clamping force of the Johnson-Rahbeck chuck.

Wafer sticking occurs when extra charge is left on the surface of the chuck dielectric or on the wafer surface resulting in undesired electric fields, clamping forces, and the like. Not offset d.c. This situation occurs because of the bias, the charge accumulated on the surface of the chuck, the wafer, or the like due to excess local field, or any of the above, which is caused by field emission tunneling across the interface gap. field emmision tunneling). In general, with the same time constant that charges, charge gradually leaks out of the Johnson-Rahbeck chuck. However, if the charge moves from the Johnson-Rahbeck chuck to the back of the dielectric coated wafer, it is very difficult to remove the resulting excess charge. This cause of wafer sticking is further exacerbated by spatial imbalances, whereby one region sticks to another and unwinds, or vice versa.

3 illustrates wafer 108 and electrostatic chuck 112 of FIG. 1 in more detail, including poles 115A and 115B, dielectric layer 116 and the like. In the example of FIG. 3, the substantially resistive dielectric material of dielectric layer 116 has a resistive element, illustrated by a resistor 310 of FIG. 3.

For simplicity of discussion, for the purpose of clamping the wafer 108 to the top surface of the wafer, the pole 115A is positively biased and the pole 115B. ) Is negatively biased. When biased this way, for each region in the dielectric layer 116 lying on top of the pole at the time constant, the electrostatic potential difference begins to be prepared, which can be up to several minutes. have. The bottom surface region 305 of the wafer 108 lying on the positively biased pole 115A is negatively charged. Similarly, the bottom surface area 307 of the wafer 108 lying on the negatively biased pole 115B is positively charged. As described above, for the purpose of clamping a wafer to an electrostatic chuck, the electrostatic potential difference utilizes electrostatic forces on the wafer.

However, with respect to time, the poles are moved by moving across the substantially resistive dielectric layer 116 (as represented by the symbol by the resistor 310) toward the top surface of the dielectric layer 116. In this case, the electrical charge is redistributed. By way of example, a positively charged pole is formed for the purpose of forming a positively biased region 312 at the top surface of the dielectric layer 116. At 115A, the positive charge will move upward through the resistive dielectric layer 116. Similarly, a negatively charged pole 115B for the purpose of forming a negatively biased region 314 at the top surface of the dielectric layer 116. The negative charge at will move upward through the resistive dielectric layer 116.

3, the regions 305/312, 307/314 and the like act as capacitor plates across the gap 306 (gap). As the electrical charge continues to move upward through the resistive dielectric layer 116, the potential difference across the capacitor plate (potential difference) continues to be made. If the applied clamping voltage remains constant for the duration of the process, the potential difference between the capacitor plates such as, for example, the regions 305/312, 307/314, etc., may be made to an excessively high level. have. This excess high level result is a high field in the gap, which promotes charge transfer between the chuck and the wafer, thereby providing an effective clamping force between the chuck and the wafer. Decrease).

In addition, when the process is complete, the presence of a plurality of electrical charges on the top surface of the dielectric layer increases the amount of time required to remove the electrical charge satisfactorily in the electrostatic chuck. For the purpose of declamping the wafer at the chuck, removal of charge is necessary to remove the electrostatic forces between the wafer and the chuck. Longer declamping times are the result of the time constants required for the electrical charge leaking across the dielectric layer. Longer delamping times result in a lower throughput of the plasma processing system, i.e. the number of wafers that can be processed by a given plasma processing system per unit time. ) Means less.

In the following, the declamping time is used for the purpose of preventing the excessive setting of the potential difference between the pole of the chuck and the wafer region lying on each of them, and for improving the throughput of the wafer processing system. There is a need for an improved method and apparatus for reducing.

The present invention relates to the manufacture of semiconductor devices. More specifically, in a processing chamber of a semiconductor wafer processing system, an electrostatic chuck electrostatically clamps and declamps a semiconductor wafer. It relates to improved methods and apparatus for decapping.

1 shows a plasma processing system by way of example, representing a wafer processing system that can be applied in the use of the wafer clamping technique obtained with the invention. Is doing;

FIG. 2 shows a bipolar cjuck configuration known as an interdigitated configuration;

FIG. 3 shows the wafer and electrostatic chuck in more detail in FIG. 1;

4 is a flow chart illustrating the steps of clamping and declamping a wafer in an electrostatic chuck in accordance with one embodiment of the present invention;

5 is an anode of a chuck in accordance with one embodiment of the present invention; c. Shows a plot of potential input versus time; And

6 is a control circuit suitable for supplying a build-up voltage, a holding voltage, a declamping voltage, and the like, in accordance with one embodiment of the present invention. A plasma processing system having a circuit will be described.

* Reference Number Description

100: plasma processing system

103: plasma region

108: wafer

110: shower head

112: electrostatic chuck

115A, 115B: Pole

116: dielectric layer

305 and 307: bottom surface area of the wafer

306: gap

310: resistor

312 positively biased region

314: negatively biased region

In one embodiment, the present invention is directed to a control system for controlling a direct current power supply, wherein a substantially resistive device is provided for clamping a wafer to an electrostatic chuck. A direct current voltage is supplied to the pole of the electrostatic chuck with a dielectric layer. A control circuit electrically coupled to the DC power supply is controlled so that the DC power supply outputs a build-up voltage having a first polarity during the build-up period. system) is included. By the build-up voltage, a potential difference is made between the first region of the substantially resistive dielectric layer and the second region of the wafer over at least a portion of such region. The potential difference causes a clamping force that clamps the wafer to the electrostatic chuck. When the clamping force substantially reaches the predefined level, the build-up period ends.

A control circuit electrically coupled to the DC power supply such that the DC power supply outputs a holding voltage during a holding period that substantially maintains the clamping force at a predefined level, The control system includes. The holding voltage has a magnitude smaller than the magnitude of the first polarity and the build-up voltage.

A control system electrically coupled to the DC power supply such that the DC power supply outputs a declamping voltage during a declamping period that substantially eliminates the clamping force. (control system), wherein the declamping voltage has a polarity opposite to the first polarity.

In another embodiment, the present invention is directed to a method of clamping a wafer to an electrostatic chuck having a substantially resistive dielectric layer mounted on an electrostatic chuck. A build having a first polarity at the pole of the electrostatic chuck causing a potential difference between the first region of the substantially resistive dielectric layer and the second region of the wafer over at least a portion of the region, etc. -up) supplying a voltage, said method comprising. The potential difference causes a clamping force that clamps the wafer with an electrostatic chuck.

The method further includes the step of ending the build-up voltage when the clamping force substantially reaches a predefined level. The method further includes supplying a holding voltage to the pole of the electrostatic chuck so as to substantially maintain the clamping force at a predefined level. The holding voltage has a magnitude smaller than the magnitude of the first polarity and the build-up voltage.

The above and other advantages of the present invention will become apparent as the various details of the drawings are studied as the following detailed description is read.

The present invention is directed to the purpose of preventing de-clamping time to prevent over-setting of the potential difference between the poles of the chuck and the wafer region overlying each other and to improve throughput of the wafer processing system. It is described here. In the following description, various specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known steps have not been described for the purpose of not unnecessarily obscuring the present invention.

According to one feature of the invention, two separate clamping d.c. The wafer is clamped to an electrostatic chuck during the processing period using voltage—build-up voltage, holding voltage—and so forth. The build-up voltage is initially applied to the electrostatic pole that clamps the wafer to the chuck. To facilitate the rapid movement of electrical charge across the dielectric layer, the build-up voltage prefers a relatively large amount of time, depending on the potential difference across the dielectric layer. It has a time constant. There is an advantage in that the clamping of the wafer to an electrostatic chuck is satisfactory, i.e. minimizing the large amount of build-up voltage required to supply the wafer with suitable cooling.

Once it is determined to reach a suitable clamping force, the build-up voltage prefers to be changed to a holding voltage. Supports a wafer that is suitably clamped to the electrostatic chuck, i.e. the wafer may be de-clamped without exceeding the electrostatic potential difference between the wafer and the chuck, or during processing. Sustaining with adequate cooling, preferring to have a sufficient holding voltage. In one embodiment, there is an advantage that the holding voltage is maintained at the minimum required level so as to minimize the amount of charge stored in the chuck.

According to another feature of the invention, a sufficient amount of electrostatic charge is removed from the electrostatic chuck by minimizing declamping time, i.e. allowing the wafer to be removed from the electrostatic chuck. By minimizing the time required to do this, the throughput of the plasma processing system is improved. In one embodiment, a declamping voltage of opposite polarity and relatively large magnitude with respect to the build-up voltage is supplied to the electrostatic chuck during the declamping period. The large magnitude of the declamping voltage facilitates rapid reverse movement of the electrical charge across the dielectric layer and allows the electrical charge to be quickly removed from the chuck. In this manner, there is an advantage of minimizing declamping time to improve throughput of the wafer processing system.

For purposes of discussing the present invention in more detail, FIG. 4 shows a flow chart illustrating the steps of clamping and declamping a wafer in an electrostatic chuck in accordance with one embodiment of the present invention. In the following discussion, a bipolar chuck is used. However, the present technology also applies to monopolar chucks, which have a single pole, and therefore a single build-up voltage, a single holding voltage, and a single declamping. ) Only the voltage level is required.

In step 402, the wafer is prepared for processing in a conventional pre-processing step. For example, the pre-treatment step may include placing the wafer into a chamber for processing, accurately positioning the wafer on an electrostatic chuck, and the like.

In step 404, the build-up voltage is supplied to the chuck as a square wave pulse. 1, the above build-up voltage can be supplied while using a suitable analog control circuit, digital control circuit, or the like in the DC power supply 114. Large build-up voltages are preferred to create the electrostatic clamping force required between the wafer and the chuck if possible in the shortest possible time. The build-up voltage is preferred to have a magnitude greater than that required to maintain the clamping force at the required level. The build-up voltage is preferably large so as not to cause excess voltage damage. The amount of electrostatic clamping force required varies, depending on the construction, processing, and wafer type, wafer cooling conditions, etc. of the dielectric layer. However, the build-up voltage should not have an excessively large magnitude that can cause undesirable charge transfer, and as a result can be short between the wafer and the chuck. In addition, the magnitude of the build-up voltage is preferred to remain below the standoff voltage, which causes damage to the dielectric layer above this threshold voltage.

It should be understood that when the chuck is bipolar, this build-up voltage is applied to the chuck pole with the opposite polarity. In addition, the build-up voltages of the various poles are not required to have the same magnitude. In fact, in some cases, d.c. Careful obliqueness of the magnitude of the supplied build-up voltage taking into account the bias is an advantage, ie even supplying electrostatic clamping force between the various regions of the wafer and the chuck. This is d.c. This is an illustration of the Bayer offset technique.

Regardless of this exact magnitude, it is preferred to supply the build-up voltage to the pole of the chuck until the required clamping force is reached. According to one aspect of the invention, the magnitude of the build-up voltage and the corresponding build-up time for the particular processing environment, etc., can be confirmed through a combination of calculated estimates and empirical observations. Can be. For example, the maximum clamping force, i.e., the maximum voltage that the power supply can produce until reaching the appropriate wafer cooling, and the maximum voltage that does not damage the wafer or chuck surface, or the like. The build-up time can be ascertained by feeding the chuck pole at a low voltage or at a predefined voltage.

When the required clamping force is reached, the holding voltage is then supplied to the pole of the chuck in step 406. It is preferred that the holding voltage has a high magnitude sufficient to maintain the electrostatic clamping force required between the wafer and the chuck. Due to the magnitude of the holding voltage, it is preferred that the potential difference between the poles of the chuck and the wafer regions placed above each other should not be so large as to damage the wafer or chuck. The holding voltage is preferably supplied to the pole of the chuck for the remainder of the process.

The magnitude of the holding voltage can be confirmed empirically. Optimal application of the clamping voltage results in a constant and suitable clamping force. Methods of ascertaining the required magnitude of a suitable holding voltage include monitoring the flow rate of heat exchange gases such as helium at the chuck / wafer interface. An excessively high flow rate may indicate that a large amount of heat exchange gas exits the chuck / wafer interface, resulting in inadequate wafer cooling or inadequate holding force between the wafer and the chuck. And by increasing the amount of the electrostatic clamping force, i.e., increasing the magnitude of the holding voltage. Instead, temperature probes can be used to monitor or predict the temperature of the wafer itself. Too high a wafer temperature reading can be corrected by improving the thermal movement between the wafer and the chuck, ie to increase the magnitude of the electrostatic clamping force that occurs simultaneously with the holding voltage.

When the process is finished, the electrostatic clamping force is preferably removed substantially to remove the wafer from the electrostatic chuck. In step 408, the clamping force is removed by applying a declamping voltage to the pole of the chuck. For a given chuck pole, the declamping voltage prefers to have a polarity opposite to that of the build-up voltage. In one embodiment, the declamping voltage for a given pole is substantially the same (but opposite in polarity) to the build-up voltage. However, the magnitude of the declamping voltage for a given pole may be larger or smaller than the magnitude of the build-up voltage. It is possible to supply a declamping voltage having a magnitude greater than twice the holding voltage. The magnitude of the declamping voltage must be high to facilitate the quick removal of electrostatic forces at the poles of the chuck.

Regardless of this exact size, it is preferred to supply a declamping voltage to the poles of the chuck until the wafer is removed satisfactorily from the chuck. According to one aspect of the invention, the magnitude of the build-up voltage and the corresponding declamping time for the particular processing environment are empirically determined in the following examples. By way of example, a "pop-off" test can be performed in which various declamping voltages are supplied to the poles, and thermal transfer gas causes the wafer to fall off the chuck. Measurement of the time taken is obtained. The declamping time can be set to substantially coincide with the pop-off time, pop-off by approximately 2 seconds by a predefined time to confirm that sufficient charge has been removed from the chuck. It may exceed the pop-off time. Declamping voltages and times, etc. may vary from system to system, from wafer to wafer, and even from process to process (eg due to different chuck designs, wafer sizes, thermal transfer gas pressures, or otherwise). Note that this can vary. When the potential difference across the gap between the wafer and the dielectric layer approaches zero, the declamping time period ends.

In one embodiment, the declamping time is noticeably shorter than the build-up time, where the declamping voltage substantially matches the magnitude of the build-up voltage of opposite polarity. It's as short as 33% when it's size. The result of a high potential difference across the dielectric layer during the declamping period has the advantage of a shorter declamping time, which results in a faster transfer of electrical charge on the top surface of the dielectric layer.

In step 410, the wafer is in a virtually known post processing step. The finished wafer is then cut in a die, which can be made into an IC chip. The resulting IC, for example IC chip 150 of FIG. 1, may then be incorporated in commercial and consumer electronic devices, including, for example, a digital computer.

5 is an anode of a chuck in accordance with one embodiment of the present invention; c. Represents a plot of potential input versus time. For simplicity of discussion, it may be the mirror image of FIG. 5, which does not include a similar plot for the cathode of the chuck. In the above embodiment, a 200 mm wafer is installed on top of a bipolar chuck having electrodes in the same area, manufactured by Fujitsu of Japan. Wafers and chucks are placed in a transformer coupled plasma plasma etch system, available from Lam Research Corporation in Fremont, California. However, as described above, the present invention disclosed herein applies to certain wafer processing systems, where plasma is applied or enhanced in etching, deposition, oxidation, anodic oxidation, and the like.

As shown in FIG. 5, a build-up voltage of 2500 volts is applied between poles during the build-up period T1. The build-up voltage is applied substantially as a square wave pulse in one embodiment. The generation of square wave pulses that create a build-up voltage is conventional, and R.C. It can be implemented in an op-amp comparator in combination with the circuit. The build-up period T1 for 16 seconds is experimentally determined to be suitable for the particular etching process. The voltage may vary for different wafers, systems, processes described above, and the like.

Once a suitable electrostatic clamping force is reached, the build-up voltage is changed by the holding voltage, which is about 500 volts in this embodiment. As with the polarity of the build-up voltage, but with a lower magnitude, note that the holding voltage has the same polarity. The holding voltage is preferably supplied for substantially the entire processing period, represented by T2 in FIG. 4. The duration of the holding time T2 varies depending on the needs of the particular treatment. However, this minimum voltage is preferred, as the minimum required voltage reduces charge transfer across the interface gap and reduces voltage stress in the chuck dielectric.

Once the process is finished, the declamping voltage is then supplied. In the example of FIG. 5, the declamping voltage is of opposite polarity to the build-up voltage but has the same magnitude as the build-up voltage of about 2500 volts. In one embodiment, the declamping voltage is also applied as a square wave pulse. The relatively high magnitude of the declamping voltage makes it possible to quickly remove electrostatic charge from the chuck for the purpose of reducing declamping time and for improving the throughput of the plasma processing system. Has Particular attention should be paid to the fact that the declamping voltage may have a magnitude greater or less than the magnitude of the build-up voltage. In this experiment, the declamping time is about 10 seconds. In comparison, prior art methods may require up to 40 seconds to declamp the wafer in the chuck.

6 is a control circuit suitable for supplying a build-up voltage, a holding voltage, a declamping voltage, and the like, in accordance with one embodiment of the present invention. A plasma processing system having a circuit will be described. At the pole of the chuck d.c. DC power supply 114, which supplies a voltage, is coupled to control system 600 via line 602. In the configuration, the radio frequency filter circuit 608 using the conventional one has a d.c. in the radio frequency energy experienced by the chuck during the plasma processing. For the purpose of protecting the power supply 114, the electrostatic chuck 112 and d.c. Coupling between the power supply 114 and the like.

In control system 608, control circuit 610 is supplied, d.c. The output voltage of the power supply 114 as well as its duration and the like are controlled. The control circuit 610 establishes the build-up voltage and the period T1, the holding voltage and the period T2, the declamping voltage and the period T3 (as shown in FIG. 5).

The bias cancellation circuit 612 can be provided, which is d.c. induced in the wafer 108 by the plasma during processing. Consider bias. Induced d.c. as described above on a wafer. D.c. to consider bias For the purpose of properly adjusting the output of the power supply 114, the bias canceling circuit 612 is provided with the control circuit 610 and d.c. It may be electrically coupled between the power supply 114 and the like. By way of example, for the purpose of making the potential difference substantially constant at the pole by considering the induced wafer bias, the bias canceling circuit is d.c. It can be used in connection with a power supply. However, d.c. If the power supply is a floating power supply, the bias cancellation circuit may not be necessary.

The establishment of the build-up voltage and the period T1, the holding voltage and the period T2, and the declamping voltage and the period T3 can be performed by the digital processing device, for example, programmable. It should be noted that there are circuits, microprocessors, or computers. Via line 616, control circuit 610 and d.c. Suitable signals may be supplied by the digital processing device 614 such that it is possible to produce at least the voltages described above during the period during which the power supply 114 or the like is required.

As can be seen from the future, the present invention has the advantage of using a high voltage to quickly obtain the clamping force and the like occurring simultaneously with the required clamping field. Once the required clamping force is reached, the invention has the advantage of reducing the holding potential of sustaining the electric field at the minimum level required, thereby minimizing excess charge transfer across the interface gap. In this way, wafer sticking is substantially reduced.

In addition, the persistence of the electric field at the minimum level required results in the amount of charge stored in the known and re-producing chuck. As a result, the stored charge can be removed in a calculated manner to minimize the extra clamping force. In addition, the present invention has the advantage of using a high voltage (with the opposite polarity) to remove stored charges, thereby minimizing de-lamping time as well as extra sticking time for the purpose of improving wafer throughput. have.

Although the present invention has been described with respect to some preferred embodiments, there are variations, substitutions, coincidences, and the like, which are within the scope of the invention. It should be particularly noted that there are many variations in implementing the method, apparatus and the like of the present invention. Therefore, it is intended that the following appended claims be interpreted, including variations, substitutions, congruences, etc., within the spirit and scope of the present invention.

Claims (26)

A direct current to the pole of the electrostatic chuck having a substantially resistive dielectric layer installed on the electrostatic chuck for the purpose of clamping the wafer to the electrostatic chuck. A direct current power supply provides a direct voltage A control circuit electrically coupled to the DC power supply such that the DC power supply produces an output of the DC voltage; Having a first polarity during a build-up period, causing a potential difference made between a first region of the substantially resistive dielectric layer and a second region of the wafer over at least a portion of the region, and the like. Build-up voltage-the potential difference causes a clamping force to clamp the wafer to the electrostatic chuck, and the build-up cycle causes the clamping force to reach a substantially predefined level When it ends-; A holding voltage during a holding period that substantially maintains the clamping force at the predefined level—the holding voltage is greater than the magnitude of the first polarity and the build-up voltage. Have a small size, etc.-; A declamping voltage during a declamping period that substantially eliminates the clamping force, the declamping voltage having a polarity opposite to the first polarity; And a control system for controlling a DC power supply. The method of claim 1, wherein between the wafer and the chuck, a clamping force is representative of an electrostatic force sufficient to stabilize thermal transfer at a predefined level during processing. A control system for controlling a DC power supply. 2. The control system of claim 1, wherein the magnitude of said declamping voltage substantially coincides with said magnitude of said build-up voltage. The control system of claim 1, wherein the electrostatic chuck is a bipolar electrostatic chuck. 5. The DC power supply control of claim 4, further comprising a bias compensation circuit coupled to the control circuit that regulates the DC voltage in response to a DC induced bias in the wafer. Control system. 2. The method of claim 1, wherein at least one of the build-up voltage, the holding voltage, the declamping voltage, and the like, is responsive to a signal from a digital processing device coupled to the control circuit. A control system for controlling a DC power supply, characterized in that it is generated. 7. The method of claim 6, wherein at least one of the build-up period, the holding period, the declamping period, and the like is generated in response to a signal from the digital processing apparatus. Control system to control DC power supply. The control system of claim 1, wherein the control circuit is representative of an analog control circuit. 2. The control system of claim 1, wherein the declamping period ends when the potential difference approaches zero volts. 2. The control system of claim 1, wherein the build-up voltage level is supplied by a substantially square wave pulse. A first polarity at the pole of the electrostatic chuck so as to cause a potential difference made between the first region of the substantially resistive dielectric layer and the second region of the wafer over at least a portion of such region; Supplying a build-up voltage having the potential difference causing a clamping force to clamp the wafer to the electrostatic chuck; Terminating the step of supplying the build-up voltage when the clamping force reaches a substantially predefined level; Supplying a holding voltage to the electrostatic chuck to substantially sustain the clamping force at the predefined level, the holding voltage having the first polarity and the build-up Has a magnitude less than the magnitude of the voltage; A method of clamping a wafer to an electrostatic chuck having a substantially resistive dielectric layer installed on the electrostatic chuck. 12. The method of claim 11, further comprising supplying a declamping voltage to the pole of the electrostatic chuck to substantially remove the clamping force, the declamping voltage being the first. A method of clamping a wafer to an electrostatic chuck having a substantially resistive dielectric layer installed on the electrostatic chuck, characterized by having a polarity opposite to the polarity. . 13. The substantially resistive dielectric layer of claim 12, wherein the magnitude of the declamping voltage substantially matches the magnitude of the build-up voltage. A method of clamping a wafer to an electrostatic chuck with a dielectric layer. 13. The method of claim 12, wherein at least one of the build-up voltage, the holding voltage, the declamping voltage, and the like, is responsive to a signal from a digital processing device coupled to the control circuit. A method of clamping a wafer to an electrostatic chuck having a substantially resistive dielectric layer installed on the electrostatic chuck. The method of claim 12, wherein at least one of the build-up voltage, the holding voltage, the declamping voltage, and the like is generated in response to a signal from an analog circuit coupled to the control circuit. A method for clamping a wafer to an electrostatic chuck having a substantially resistive dielectric layer installed on the electrostatic chuck. 13. The method of claim 12, further comprising adjusting at least one of the build-up voltage, the holding voltage, the declamping voltage, and the like in response to a direct current induced bias in the wafer. And further comprising: clamping the wafer to an electrostatic chuck having a substantially resistive dielectric layer installed on the electrostatic chuck. 12. The method of claim 11, wherein between the wafer and the chuck, the clamping force is representative of an electrostatic force sufficient to facilitate stabilization of thermal transfer at a predefined level during processing. A method of clamping a wafer to an electrostatic chuck having a substantially resistive dielectric layer installed on the electrostatic chuck. 12. The wafer of claim 11, wherein the electrostatic chuck is a bipolar electrostatic chuck, the wafer having an electrostatic chuck having a substantially resistive dielectric layer installed on the electrostatic chuck. How to clamp the 12. The substantially resistive dielectric layer of claim 11, further comprising the step of terminating the step of supplying the declamping voltage when the potential difference is 0 volts. A method of clamping a wafer to an electrostatic chuck having a dielectric layer. 12. The electrostatic chuck of claim 11, wherein the build-up voltage is supplied as a substantially square wave pulse. A method of clamping a wafer to an electrostatic chuck. To the poles of the electrostatic chuck having a substantially resistive dielectric layer installed on the electrostatic chuck to effect the clamping of a wafer on the electrostatic chuck. The direct current power supply supplies the voltage Means coupled to said direct current power supply for generating a first control signal, in response to said first control signal, over a first region of said substantially resistive dielectric layer and at least a portion of said region; The DC power supply supplies a build-up voltage having a first polarity to the pole of the electrostatic chuck, which causes a potential difference made between the second regions of the wafer and the like, and the potential difference is Generate a clamping force to clamp the wafer to the electrostatic chuck; Means coupled to the direct current power supply for generating a second control signal—in response to the second control signal, when the clamping force reaches the predefined level, the build-up The DC power supply is terminated; Means coupled to the direct current power supply for generating a third control signal, the pole of the electrostatic chuck substantially sustaining the clamping force at the predefined level in response to the third control signal (Iii) the DC power supply supplies a holding voltage, the holding voltage has a magnitude smaller than the magnitude of the first polarity and the build-up voltage, and the like; An apparatus for controlling a DC power supply, comprising: and the like. 22. The apparatus of claim 21, comprising means coupled to the direct current power supply for generating a fourth control signal, wherein the electrostatic discharge substantially eliminates the clamping force in response to the fourth control signal. The DC power supply supplies a holding voltage to the pole of the chuck, and the declamping voltage has a polarity opposite to the first polarity. Device. 23. The apparatus of claim 22, wherein the magnitude of the declamping voltage substantially matches the magnitude of the build-up voltage. 23. The method of claim 22, wherein at least one of adjusting the build-up voltage, the holding voltage, the declamping voltage, and the like, in response to a direct current induced bias in the wafer, Apparatus for controlling a DC power supply, characterized in that it further comprises a means coupled to the DC power supply. Supplying a holding voltage to the pole of the electrostatic chuck that clamps the wafer to the electrostatic chuck substantially at a clamping force between the wafer and the electrostatic chuck at a predefined level. Step-said holding voltage has a first polarity; Supplying a declamping voltage to the pole of the electrostatic chuck that substantially removes the clamping force, wherein the declamping voltage has a polarity opposite to the first polarity, The clamping voltage has a magnitude greater than the magnitude of the holding voltage; And clamping the wafer to an electrostatic chuck having a substantially resistive dielectric layer installed on the electrostatic chuck. 27. The substantially resistive dielectric layer of claim 25, wherein the magnitude of the declamping voltage is greater than twice the magnitude of the holding voltage. clamping the wafer to an electrostatic chuck having a dielectric layer.