KR20000021737A - Stage for manufacturing semiconductor wafer - Google Patents
Stage for manufacturing semiconductor wafer Download PDFInfo
- Publication number
- KR20000021737A KR20000021737A KR1019980040986A KR19980040986A KR20000021737A KR 20000021737 A KR20000021737 A KR 20000021737A KR 1019980040986 A KR1019980040986 A KR 1019980040986A KR 19980040986 A KR19980040986 A KR 19980040986A KR 20000021737 A KR20000021737 A KR 20000021737A
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- Prior art keywords
- wafer
- stage
- gas
- semiconductor wafer
- manufacturing
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/682—Mask-wafer alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
본 발명은 반도체 제조용 스테이지에 관한 것으로, 특히, 마스크를 이용하여 반도체웨이퍼에 노광공정을 진행 시에 정렬도를 개선시킬 수 있는 웨이퍼 스테이지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stage for manufacturing a semiconductor, and more particularly, to a wafer stage capable of improving the degree of alignment during an exposure process on a semiconductor wafer using a mask.
도 1은 종래의 통상적인 반도체웨이퍼 제조용 노광장치를 도시한 도면이고, 도 2는 종래의 통상적인 반도체웨이퍼에 마스크를 통한 노광공정이 진행되는 것을 보인 도면이다.1 is a view showing a conventional exposure apparatus for manufacturing a conventional semiconductor wafer, Figure 2 is a view showing that the exposure process through a mask to a conventional conventional semiconductor wafer.
종래의 통상적인 반도체웨이퍼 제조용 스테이지는 도 1과 같이, 상면에 웨이퍼 안착부위가 형성되어 있다.In a conventional semiconductor wafer manufacturing stage, a wafer seating portion is formed on an upper surface as shown in FIG. 1.
웨이퍼(102)가 종래의 스테이지(100) 상의 안착부위에 안착되면, 웨이퍼와 마스크(104)를 정렬시킨다. 이 후, X선 등의 광원을 조사하여 마스크의 패턴을 웨이퍼 상에 전사시킨다.When the wafer 102 is seated on the seating site on the conventional stage 100, the wafer and the mask 104 are aligned. Thereafter, a light source such as X-rays is irradiated to transfer the pattern of the mask onto the wafer.
이 때, 노광공정에 필요한 적정온도를 가해주어야 한다.At this time, the proper temperature required for the exposure process should be applied.
등배에 의한 마스크 제작 기준과 렌즈를 이용하여 특수한 광학계의 조건하에서 공정 중 발생되어지는 웨이퍼의 열적인 변수들에 의해서 웨이퍼가 변성된다.The wafer is modified by thermal parameters of the wafer generated during the process under a special optical system condition using a mask manufacturing standard and a lens by an equal magnification.
웨이퍼가 변성되어 있을 경우 마스크를 물리적으로 변형을 시키어 정렬도를 맞출 수 있으나 실제 마스크는 박막 형태의 멤브레인 상태로 구성되어 있기 때문에 쉽게 마스크의 파손을 예상할 수 있으며 실제로 빈번한 취급 상의 파손을 야기시킨다.If the wafer is deformed, the mask may be physically deformed to align the alignment, but since the actual mask is composed of a membrane in the form of a thin film, the mask may be easily damaged and may cause frequent handling damage.
이처럼, 본 발명의 스테이지는 웨이퍼 위치별로 보상하기 위한 열적인 제어능력이 떨어지는 문제점을 가지고 있다.As such, the stage of the present invention has a problem that the thermal control ability to compensate for each wafer position is poor.
상기의 문제점을 해결하고자, 본 발명의 목적은 노광 공정 진행 시 발생되는 웨이퍼의 열을 제어하기가 용이한 반도체웨이퍼용 스테이지를 제공하려는 것이다.In order to solve the above problems, it is an object of the present invention to provide a stage for a semiconductor wafer that is easy to control the heat of the wafer generated during the exposure process.
상기 목적을 달성하고자, 본 발명의 반도체웨이퍼 제조용 스테이지는 표면에 형성된 다 수개의 홀과, 다 수개의 홀과 각각 연결되어 냉각가스가 유입되는 가지관 형상인 가스라인과, 가스라인으로의 각각의 냉각가스 유입을 제어하기 위한 콘트롤러가 형성된 것이 특징이다.In order to achieve the above object, the stage for manufacturing a semiconductor wafer of the present invention is a plurality of holes formed on the surface, the gas line is a branch pipe shape connected to each of the plurality of holes and the cooling gas flows, and each of the gas line It is characterized by a controller for controlling the inlet of the cooling gas.
도 1은 종래의 통상적인 반도체웨이퍼 제조용 스테이지를 도시한 평면도이고,1 is a plan view showing a conventional stage for manufacturing a conventional semiconductor wafer,
도 2는 종래의 반도체웨이퍼 제조용 스테이지를 이용하여 반도체웨이퍼에 마스크를 통한 노광공정이 진행되는 것을 보인 도면이다.FIG. 2 is a view illustrating an exposure process through a mask performed on a semiconductor wafer using a stage for manufacturing a conventional semiconductor wafer.
도 3은 본 발명의 반도체웨이퍼 제조용 스테이지를 도시한 평면도이고,3 is a plan view showing a stage for manufacturing a semiconductor wafer of the present invention,
도 2는 본 발명의 반도체웨이퍼 제조용 스테이지를 이용하여 반도체웨이퍼에 마스크를 통한 노광공정이 진행되는 것을 보인 도면이다.FIG. 2 is a view illustrating an exposure process through a mask on a semiconductor wafer using a stage for manufacturing a semiconductor wafer of the present invention.
*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100, 200. 스테이지 102, 202. 웨이퍼100, 200. Stage 102, 202. Wafer
104, 204. 마스크104, 204.Mask
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 3은 본 발명의 반도체웨이퍼 제조용 스테이지를 도시한 평면도이고, 도 2는 본 발명의 반도체웨이퍼 제조용 스테이지를 이용하여 반도체웨이퍼에 마스크를 통한 노광공정이 진행되는 것을 보인 도면이다.3 is a plan view illustrating a stage for manufacturing a semiconductor wafer of the present invention, Figure 2 is a view showing that the exposure process through a mask to the semiconductor wafer using the stage for manufacturing a semiconductor wafer of the present invention.
본 발명의 반도체웨이퍼 제조용 스테이지(200)는 도 3 및 도 4와 같이, 표면에 형성된 다 수개의 홀(210)과, 다 수개의 홀(210)과 각각 연결되어 냉각가스가 유입되는 가지관 형상의 가스라인(208)과, 가스라인(208)을 통해 각각의 냉각가스 유입을 제어하기 위한 콘트롤러(206)로 구성된다.3 and 4, the stage 200 for manufacturing a semiconductor wafer of the present invention is connected to a plurality of holes 210 and a plurality of holes 210 formed on a surface thereof, and a branch pipe shape into which cooling gas is introduced. And a controller 206 for controlling the inflow of each cooling gas through the gas line 208.
본 발명의 냉각가스로는 헬륨가스가 이용된다. 헬륨가스가 유입되는 가스라인(208)은 도면에서와 같이, 가지형으로 여러 개의 복수라인으로 형성된다.Helium gas is used as the cooling gas of the present invention. The gas line 208 into which helium gas is introduced is formed in a plurality of lines in a branched manner, as shown in the figure.
그리고, 가스라인(208)에는 각 라인 별로 헬륨가스 유입을 온/오프시킬 수 있는 스위칭 역할을 하는 콘트롤러(206)가 연결설치된다.In addition, the gas line 208 is connected to the controller 206 which serves to switch the helium gas flow on / off for each line.
만일, 노광 시 웨이퍼의 어느 특정 부위에 웨이퍼 변성에 의한 중첩도 상에 오정렬 정도가 커서 보상을 필요로 할 경우, 본 발명에서는 마스크의 패턴 레이아웃 전사시 발생될 수 있는 웨이퍼 변성 발생된 부위에 헬륨가스를 유입시킴으로써 웨이퍼 자체의 변성 성분을 보상할 수 있다.In the present invention, when the degree of misalignment on the overlapping degree due to wafer denaturation on a specific part of the wafer is large and needs compensation, in the present invention, helium gas may be formed on the part where wafer denaturation occurs that may occur when transferring the pattern layout of the mask. It is possible to compensate for the denatured component of the wafer itself by introducing.
즉, 가스라인(208)은 웨이퍼 변성 발생된 부위에 소정 가지관을 통해 선택적으로 헬륨가스를 유입되도록 콘트롤러(206)에 의해 제어된다. 유입된 헬륨가스는 웨이퍼 뒷면에 맞닿으면서 쿨링효과를 기대할 수 있다.That is, the gas line 208 is controlled by the controller 206 to selectively introduce helium gas into a portion where wafer denaturation has occurred through a predetermined branch pipe. The introduced helium gas can be expected to be cooled while contacting the back of the wafer.
경우에 따라서는 헬륨가스 대신에 열을 공급할 수 있는 히팅가스를 이용하여 국부적으로 웨이퍼를 히팅할 수도 있다. 따라서, 히팅과정을 통해 웨이퍼의 팽창을 기대할 수 있어 결국 웨이퍼의 정렬도 개선을 도모할 수 있다.In some cases, the wafer may be locally heated using a heating gas capable of supplying heat instead of helium gas. Therefore, the expansion of the wafer can be expected through the heating process, so that the alignment of the wafer can be improved.
상술한 바와 같이, 본 발명에서는 열공정에 의해서 발생된 웨이퍼 변성에 의한 정렬도 측면에서의 변수서의 변수를 최소화할 수 있다.As described above, in the present invention, it is possible to minimize the variables in the variable standing in terms of the degree of alignment due to wafer modification generated by the thermal process.
그리고, 웨이퍼 변성이 발생해서 정렬도 개선을 위해 보상이 필요할 경우, 물리적인 힘을 가하지 않음으로써 마스크의 파손을 극소화시킬 수 있다.In addition, when wafer denaturation occurs and compensation is required to improve alignment, the damage to the mask can be minimized by applying no physical force.
또한, 국부적으로 냉각가스 공급이 필요한 부분만을 보상할 수 있는 잇점이 있다.In addition, there is an advantage that can be compensated only for the portion that needs to supply the cooling gas locally.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980040986A KR20000021737A (en) | 1998-09-30 | 1998-09-30 | Stage for manufacturing semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980040986A KR20000021737A (en) | 1998-09-30 | 1998-09-30 | Stage for manufacturing semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000021737A true KR20000021737A (en) | 2000-04-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980040986A KR20000021737A (en) | 1998-09-30 | 1998-09-30 | Stage for manufacturing semiconductor wafer |
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| KR (1) | KR20000021737A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014064347A1 (en) | 2012-10-23 | 2014-05-01 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for forming a doped silicon ingot of uniform resistivity |
-
1998
- 1998-09-30 KR KR1019980040986A patent/KR20000021737A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014064347A1 (en) | 2012-10-23 | 2014-05-01 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for forming a doped silicon ingot of uniform resistivity |
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