KR20000020950A - Method for manufacturing lower electrode of capacitors - Google Patents
Method for manufacturing lower electrode of capacitors Download PDFInfo
- Publication number
- KR20000020950A KR20000020950A KR1019980039796A KR19980039796A KR20000020950A KR 20000020950 A KR20000020950 A KR 20000020950A KR 1019980039796 A KR1019980039796 A KR 1019980039796A KR 19980039796 A KR19980039796 A KR 19980039796A KR 20000020950 A KR20000020950 A KR 20000020950A
- Authority
- KR
- South Korea
- Prior art keywords
- hsg
- layer
- forming
- lower electrode
- silicon layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
Abstract
Description
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 커패시터 하부전극의 면적 증대를 위한 HSG(Hemi Spherical Grain)-Si 적용시 고농도 도핑된 실리콘막을 추가로 증착하여 도펀트 디플리션(dopant depletion)에 의한 커패시턴스의 감소와 HSG-Si형태에서 기인되는 전계집중에 의한 리키지(leakage)특성 열화를 개선시키기 위한 커패시터의 하부전극 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and in particular, a high concentration doped silicon film is further deposited when HSG (Hemi Spherical Grain) -Si is applied to increase the area of a capacitor lower electrode, thereby resulting in capacitance due to dopant depletion. The present invention relates to a method for fabricating a lower electrode of a capacitor for reducing the degradation and improving degradation of leakage characteristics due to electric field concentration resulting from the HSG-Si type.
일반적으로 소자의 집적도가 증가함에 따라 대용량의 커패시턴스를 요구하게 되는데, 한정된 면적내에서 보다 큰 커패시턴스를 확보하기 위한 노력이 계속되어 왔다.In general, as the integration degree of the device increases, a large capacitance is required, and efforts to secure a larger capacitance within a limited area have been continued.
그중에서도 커패시턴스를 증가시키기 위한 방안으로써, 하부전극의 구조를 스택형, 실린더형 형태로 제조하는가 하면, 하부전극의 표면을 울퉁불퉁하게 제조하여 전극의 표면적을 최대한 확보하기 위한 기술이 대두 되었다.Among them, as a method for increasing capacitance, a technique for manufacturing the structure of the lower electrode in the form of a stack or a cylindrical shape, or to produce the surface of the lower electrode unevenly, to secure the maximum surface area of the electrode has emerged.
상기의 하부전극의 표면을 울퉁불퉁하게 제조하는 방법중에서 비정질 실리콘의 실리콘 원자의 이동을 이용한 HSG-Si전극을 형성하는 방법이 있다.Among the methods of manufacturing the surface of the lower electrode unevenly, there is a method of forming the HSG-Si electrode using the movement of silicon atoms of amorphous silicon.
이하, 첨부된 도면을 참조하여 종래 기술에 따른 커패시터의 하부전극 제조방법을 설명하기로 한다.Hereinafter, a method of manufacturing a lower electrode of a capacitor according to the prior art will be described with reference to the accompanying drawings.
도 1에 도시된 바와 같이, 기판 또는 절연막상에 비정질 실리콘층을 증착한 후, SiH4나 Si2H6가스를 흘려 선택적으로 실리콘 씨드(seed)를 형성한 뒤 고온/고진공에서 열처리하므로써, 비정질 실리콘층의 실리콘 원자의 이동을 통한 반구형의 돌출부를 갖는 HSG-Si전극(11)을 형성한다.As shown in FIG. 1, after depositing an amorphous silicon layer on a substrate or an insulating film, by forming a silicon seed selectively by flowing a SiH 4 or Si 2 H 6 gas, the amorphous by heat treatment at high temperature / high vacuum, An HSG-Si electrode 11 having a hemispherical protrusion through movement of silicon atoms in the silicon layer is formed.
이때, 비정질 실리콘층의 도펀트를 일정 농도 이상 도핑하면, 비정질 실리콘층 형성시 도펀트에 의해 실리콘의 결정화 에너지 장벽이 낮아져 조기에 비정질 실리콘층이 결정화됨으로써, 실리콘 원자의 이동이 원활하지 않아 HSG-Si전극 형성시 밸드 디팩트(Bald defect)등이 나타나므로 비정질 실리콘층의 도펀트 농도를 낮게 제어할 필요가 있다.At this time, when the dopant of the amorphous silicon layer is doped at a predetermined concentration or higher, the barrier layer of crystallization energy of silicon is lowered by the dopant during the formation of the amorphous silicon layer, and the amorphous silicon layer is crystallized early, so that the movement of silicon atoms is not smooth, and thus the HSG-Si electrode It is necessary to control the dopant concentration of the amorphous silicon layer to be low due to the appearance of a ball defect (formation defects) during formation.
여기서, HSG-Si전극(11) 자체는 불순물이 도핑되지 않은 실리콘층으로 형성된다.Here, the HSG-Si electrode 11 itself is formed of a silicon layer which is not doped with impurities.
또한, HSG-Si전극(11)의 형태는 도 1에 도시된 바와 같이, 완전한 반구형이 아니라 반구형의 형태보다 더 큰 표면적을 갖는다.In addition, the shape of the HSG-Si electrode 11 has a larger surface area than that of the hemispherical shape instead of the full hemispherical shape, as shown in FIG.
그러나 상기와 같은 종래 커패시터의 하부전극 제조방법은 다음과 같은 문제점이 있었다.However, the method of manufacturing a lower electrode of the conventional capacitor as described above has the following problems.
HSG-Si전극을 커패시터의 하부전극으로 사용할 경우, 도펀트 디플리션에 의한 커패시턴스의 감소를 초래하고, HSG-Si의 형태가 협소한 골 형태의 부분(A부분)이 발생하므로 이 부분에서 전계집중 현상이 발생하여 리키지(leakage)특성이 심하게 열화되는 단점이 있었다.When the HSG-Si electrode is used as the lower electrode of the capacitor, the capacitance caused by dopant depletion is reduced, and the bone-shaped part (part A) having a narrow shape of HSG-Si is generated, so the electric field concentration in this part There was a disadvantage that the phenomenon occurred severely degraded (leakage) characteristics.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로서, HSG-Si전극 형성후, 고농도 도핑된 실리콘을 얇게 추가 증착함으로써, 커패시턴스 감소 및 전계집중 현상을 방지하고, 부피증가에 따른 전극 면적을 최대화하는데 적당한 커패시터의 하부전극 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above-mentioned problems of the prior art, by forming a thin addition of a high concentration of doped silicon after the formation of the HSG-Si electrode, to prevent capacitance reduction and field concentration phenomenon, the electrode area according to the increase in volume It is an object of the present invention to provide a method for fabricating a lower electrode of a capacitor suitable for maximizing the voltage.
도 1은 종래기술에 따른 커패시터 하부전극의 표면 확대단면도1 is an enlarged cross-sectional view of a surface of a capacitor lower electrode according to the prior art;
도 2는 본 발명에 따른 커패시터 하부전극의 표면 확대단면도2 is an enlarged cross-sectional view of a surface of a capacitor lower electrode according to the present invention;
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11 : HSG-Si 전극 12 : 실리콘층11: HSG-Si electrode 12: silicon layer
상기의 목적을 달성하기 위한 본 발명의 커패시터 하부전극 제조방법은 반도체 소자의 커패시터 하부전극을 형성함에 있어서, 게이트전극, 워드라인 및 데이터라인이 형성된 기판 또는 절연막상에 HSG-Si층을 형성하는 공정과, 상기 HSG-Si의 표면에 고농도 도핑된 실리콘층을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.In the method of manufacturing a capacitor lower electrode of the present invention for achieving the above object, a process of forming an HSG-Si layer on a substrate or an insulating film on which a gate electrode, a word line and a data line are formed, in forming a capacitor lower electrode of a semiconductor device. And forming a highly doped silicon layer on the surface of the HSG-Si.
이하, 본 발명의 커패시터 하부전극 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of manufacturing a capacitor lower electrode of the present invention will be described with reference to the accompanying drawings.
먼저, 도면에는 도시하지 않았지만, 기판상에 원하는 패턴대로 게이트 전극 및 워드라인을 형성한다.First, although not shown in the drawing, gate electrodes and word lines are formed on a substrate in a desired pattern.
이후, 콘택홀을 통해 기판의 불순물영역과 전기적으로 연결되도록 데이터 라인을 형성한 후, 노드 콘택홀을 형성한다.Thereafter, the data line is formed to be electrically connected to the impurity region of the substrate through the contact hole, and then the node contact hole is formed.
노드 콘택홀을 통해 기판과 연결되는 커패시터 하부전극을 형성하게 되는데 이와 같은 커패시터 하부전극을 형성함에 있어서, 도 2에 도시한 바와 같이, 기판 또는 절연막상에 비정질 실리콘층을 증착한 후, 실리콘을 소오스(source)로 하는 가스 즉, SiH4나 Si2H6가스를 흘려 선택적으로 실리콘 씨드(seed)를 형성한다.A capacitor lower electrode connected to the substrate is formed through the node contact hole. In forming the capacitor lower electrode, as shown in FIG. 2, after depositing an amorphous silicon layer on the substrate or the insulating layer, the silicon is sourced. A silicon seed is selectively formed by flowing a gas serving as a source, that is, SiH 4 or Si 2 H 6 gas.
이후, 고온/고진공에서 열처리하여 비정질 실리콘층의 실리콘 원자의 이동을 통한 반구형의 돌출부를 갖는 HSG-Si전극(11)을 형성한다.Thereafter, heat treatment is performed at high temperature / high vacuum to form an HSG-Si electrode 11 having a hemispherical protrusion through movement of silicon atoms in the amorphous silicon layer.
이때, 비정질 실리콘층의 도펀트를 일정 농도 이상 도핑하면, 비정질 실리콘층 형성시 도펀트에 의해 실리콘의 결정화 에너지 장벽이 낮아져 조기에 비정질 실리콘층이 결정화됨으로써, 실리콘 원자의 이동이 원활하지 않아 HSG-Si전극 형성시 밸드 디팩트(Bald defect)등이 나타나므로 비정질 실리콘층의 도펀트 농도를 낮게 제어할 필요가 있다.At this time, when the dopant of the amorphous silicon layer is doped at a predetermined concentration or higher, the barrier layer of crystallization energy of silicon is lowered by the dopant during the formation of the amorphous silicon layer, and the amorphous silicon layer is crystallized early, so that the movement of silicon atoms is not smooth, and thus the HSG-Si electrode It is necessary to control the dopant concentration of the amorphous silicon layer to be low due to the appearance of a ball defect (formation defects) during formation.
여기서, HSG-Si전극(11) 자체는 불순물이 도핑되지 않은 실리콘층으로 형성된다.Here, the HSG-Si electrode 11 itself is formed of a silicon layer which is not doped with impurities.
이후, 상기 HSG-Si전극(11)상에 고농도 도핑된 실리콘층(12)을 얇게 추가 증착한다.Subsequently, a thinly doped silicon layer 12 is further deposited on the HSG-Si electrode 11.
따라서, HSG-Si전극(11)의 표면에는 도펀트 디플리션이 없는 층을 만들 수 있고 상기 HSG-Si전극(11)의 본래 형태에서 발생된 골진 부분들이 라운딩(rounding)되므로써 HSG-Si전극(11)의 형태가 협소한 골 형태의 부분이 발생하지 않아 전체적으로 전극의 면적이 증가하게 된다.Therefore, the surface of the HSG-Si electrode 11 can be made without a dopant depletion layer and rounded rounded portions generated in the original shape of the HSG-Si electrode 11 can be formed by rounding the HSG-Si electrode 11 The narrow bone shape of 11) does not occur, resulting in an increase in the area of the electrode as a whole.
이상에서 상술한 바와 같이, 본 발명의 커패시터 하부전극 제조방법은 다음과 같은 효과가 있다.As described above, the capacitor lower electrode manufacturing method of the present invention has the following effects.
커패시터 하부전극용 HSG-Si를 형성한 후, 상기 HSG-Si표면에 고농도 도핑된 실리콘층을 형성함에 따라 전극 표면의 도펀트 디플리션에 의한 커패시턴스의 감소를 방지한다.After forming the HSG-Si for the capacitor lower electrode, by forming a highly doped silicon layer on the HSG-Si surface to prevent the reduction of capacitance due to dopant depletion of the electrode surface.
그리고 HSG-Si의 형태를 라운딩지게 하므로써 전계집중에 의한 리키지 특성의 열화를 개선시킴과 동시에 전극의 면적을 증가시키는 효과가 있다.In addition, by rounding the shape of HSG-Si, there is an effect of improving the deterioration of the leakage characteristics due to electric field concentration and increasing the area of the electrode.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980039796A KR20000020950A (en) | 1998-09-24 | 1998-09-24 | Method for manufacturing lower electrode of capacitors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980039796A KR20000020950A (en) | 1998-09-24 | 1998-09-24 | Method for manufacturing lower electrode of capacitors |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20000020950A true KR20000020950A (en) | 2000-04-15 |
Family
ID=19551859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019980039796A KR20000020950A (en) | 1998-09-24 | 1998-09-24 | Method for manufacturing lower electrode of capacitors |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20000020950A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100737304B1 (en) * | 1999-12-03 | 2007-07-09 | 에이에스엠 인터내셔널 엔.브이. | Conformal thin films over textured capacitor electrodes |
-
1998
- 1998-09-24 KR KR1019980039796A patent/KR20000020950A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100737304B1 (en) * | 1999-12-03 | 2007-07-09 | 에이에스엠 인터내셔널 엔.브이. | Conformal thin films over textured capacitor electrodes |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
RU2199168C2 (en) | Method for producing integrated-circuit capacitor having improved characteristics of electrode and insulating layers (alternatives) and capacitors produced by this method | |
KR100269287B1 (en) | A method for forming hemi-spherical grain | |
KR100224707B1 (en) | Method for manufacturing of semiconductor device capacitor | |
JPH11238857A (en) | Semiconductor device and its manufacture | |
US5943570A (en) | Methods of forming capacitor electrodes containing HSG semiconductor layers therein | |
US5960281A (en) | Methods of fabricating microelectronic electrode structures using hemispherical grained (HSG) silicon | |
KR100338848B1 (en) | Fabrication method of semiconductor device with hsg configuration | |
KR20000020950A (en) | Method for manufacturing lower electrode of capacitors | |
JP2000091532A (en) | Semiconductor device and manufacture of the semiconductor device | |
KR100350588B1 (en) | Hsg lower electrode structure, capacitor using the same, and the formation of the capacitor | |
KR100200298B1 (en) | Capacitor device fabrication method of semiconductor | |
KR100524685B1 (en) | Manufacturing Method of Dielectric Capacitor of Semiconductor Device | |
KR950011644B1 (en) | Method of fabricating a storage node of a capacitor | |
KR100328597B1 (en) | method for fabricating Capacitor of semiconductor device | |
US6194266B1 (en) | Method for forming a capacitor having selective hemispherical grained polysilicon | |
KR20000000566A (en) | Method for forming capacitor of semiconductor using hemispherical grain silicon layer | |
KR100329614B1 (en) | Capacitor Formation Method of Semiconductor Device | |
US6204121B1 (en) | Method for bottom electrode of capacitor | |
KR100384841B1 (en) | A method for forming capacitor in semiconductor device using hemispherical silicon grain | |
KR100319168B1 (en) | A method for fabricating a semiconductor device | |
JPH11145392A (en) | Semiconductor capacitance element and its manufacture | |
KR20010069054A (en) | method for fabricating capacitor of semiconductor device | |
KR970000975B1 (en) | Storage electrode manufacture method of capacitor | |
KR100268184B1 (en) | Method of manufacturing a sram cell of a semiconductor device | |
KR100451516B1 (en) | Method for manufactruing capacitor in semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
N231 | Notification of change of applicant | ||
WITN | Withdrawal due to no request for examination |