KR20000020223A - Laminated package of semiconductor chip - Google Patents

Laminated package of semiconductor chip Download PDF

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Publication number
KR20000020223A
KR20000020223A KR1019980038739A KR19980038739A KR20000020223A KR 20000020223 A KR20000020223 A KR 20000020223A KR 1019980038739 A KR1019980038739 A KR 1019980038739A KR 19980038739 A KR19980038739 A KR 19980038739A KR 20000020223 A KR20000020223 A KR 20000020223A
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South Korea
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semiconductor chip
pin
pins
package
semiconductor
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KR1019980038739A
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Korean (ko)
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KR100276213B1 (en
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강경석
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강경석
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Priority to KR19980038739A priority Critical patent/KR100276213B1/en
Priority to JP10374773A priority patent/JP3035534B2/en
Priority to US09/232,026 priority patent/US6242285B1/en
Publication of KR20000020223A publication Critical patent/KR20000020223A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers

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  • Engineering & Computer Science (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE: A laminated package of semiconductor chip is provided to effectively laminate a semiconductor chip. CONSTITUTION: A first semiconductor chip(50A) is connected to a laminating substrate by linking a plurality of pins. An auxiliary connecting substrate is disposed at lower portion of a second semiconductor chip(50B) to link the selected pins of the second semiconductor chip to a predetermined no connection pins. At least one and more the second semiconductor chip is laminated on upper portion of the first semiconductor chip by linking the predetermined pins of the second semiconductor chip to pins of the first semiconductor chip. The pin controlling the second semiconductor chip in operable state are electrically connected to a predetermined no connection pin not related to operation of the second semiconductor chip. Thereby, a plurality of the semiconductor chip is effectively laminated, so that a mounting area of the semiconductor chip is minimized.

Description

반도체칩의 적층패키지Semiconductor chip stack package

본 발명은 반도체칩을 적층한 적층패키지(package)에 관한 것으로, 해당 반도체칩의 동작상태를 제어하는 핀의 배선에 변화를 주기 위해, 배선기능을 갖는 PCB기판 등의 보조연결수단을 반도체칩에 추가시켜, 다수의 반도체칩을 적층하는 반도체칩의 적층패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stack package in which semiconductor chips are stacked, and in order to change the wiring of a pin for controlling the operation state of the semiconductor chip, auxiliary connecting means such as a PCB substrate having a wiring function is connected to the semiconductor chip. In addition, the present invention relates to a stack package of a semiconductor chip for stacking a plurality of semiconductor chips.

전자기기들이 소형화되고 또 휴대용제품을 선호하는 추세에 따라 이들 전자기기들을 구성하는 부품들이 경박단소화 되어 가고, 줄어든 실장공간에서 이러한 단위부품의 실장면적을 줄이는 것에 관심이 증폭되고 있으며, 그 중에서도 반도체칩의 실장효율을 향상시키기 위한 패키지 기술이 급속도로 발전하고 있다.As electronic devices are becoming smaller and portable products are preferred, components constituting these electronic devices are becoming smaller and thinner, and interest in reducing the mounting area of such unit parts in a reduced mounting space is amplified. Package technologies for improving chip mounting efficiency are rapidly developing.

이에 따라, 최근에는 실장효율을 배가시키기 위해 복수의 반도체칩을 적층하여 모듈화하는 적층패키지 기술이 실용화단계에 접어들고 있으며, 이러한 종래의 대표적인 적층기술을 도면을 참조하여 설명한다.Accordingly, in recent years, a stacking package technology for stacking and modularizing a plurality of semiconductor chips in order to double the mounting efficiency has been put into practical use, and this conventional stacking technology will be described with reference to the drawings.

도 1a 및 도 1b는 종래 반도체칩의 적층패키지를 설명하기 위한 사시도 및 단면도이다.1A and 1B are a perspective view and a cross-sectional view for describing a laminated package of a conventional semiconductor chip.

도시한 바와 같이, 종래에는 적층할 위치를 맞춘 후 두 개의 반도체칩(10A,10B)을 상부와 하부에 위치시키고, 헤더(header, 121∼127...,12)라고 부르는 별도의 도체선을 사용하여 각 반도체칩의 다수의 핀(11A,11B)을 연결하므로써 적층을 수행하였다. 그리고 125헤더와 같이, 경우에 따라서는 두 반도체칩(10A,10B)의 핀연결부위를 끊고, 적층된 반도체칩(10B)의 상부를 가로지르도록 하여 연결하기도 하였다.As shown in the drawing, conventionally, two semiconductor chips 10A and 10B are positioned at the top and the bottom after the stacking positions are aligned, and a separate conductor line called headers 121 to 127, 12 is formed. The stacking was performed by connecting a plurality of pins 11A and 11B of each semiconductor chip. In some cases, as in the 125 header, pin connection portions of the two semiconductor chips 10A and 10B are cut off and connected to cross the upper portions of the stacked semiconductor chips 10B.

하지만 위와 같은 종래의 적층패키지는, 다수의 헤더(header)를 이용해야 하는 번거로움이 있었으며, 반도체칩 핀의 피치(Pitch;핀간 간격)가 좁아짐에 따라 필요한 부분을 단락하거나 또는 다수의 각 핀에 대응시켜 헤더를 연결하는 것은 공정적인 측면에서도 많은 문제점을 야기시켰다.However, the conventional multilayer package as described above has been troublesome to use a plurality of headers, and as the pitch of the semiconductor chip pins is narrowed, a necessary portion is shorted or a plurality of pins are connected. Connecting headers in response has caused many problems in terms of fairness.

따라서 본 발명의 목적은 전술한 문제점을 해결할 수 있도록, 반도체칩의 핀모양을 변형시키고 특정 핀간을 연결하는 보조연결수단을 반도체칩 하부에 삽입시켜 적층하므로써, 반도체칩을 효율적으로 적층시킬 수 있는 반도체칩의 적층패키지를 제공함에 있다.Accordingly, an object of the present invention is to solve the above-described problems, by inserting the auxiliary connecting means for deforming the pin shape of the semiconductor chip and connecting the specific pin inserted under the semiconductor chip, the semiconductor chip can be efficiently stacked The present invention provides a stack package of chips.

도 1a 및 도 1b는 종래 반도체칩의 적층구조를 설명하기 위한 도면.1A and 1B are views for explaining a laminated structure of a conventional semiconductor chip.

도 2a 및 도 2b는 본 발명의 반도체칩의 적층패키지에 대한 사시도 및 단면도.2A and 2B are a perspective view and a cross-sectional view of a laminated package of a semiconductor chip of the present invention.

도 3a는 본 발명의 적층패키지에 이용되는 반도체칩의 배면 핀배열도.3A is a rear pin arrangement diagram of a semiconductor chip used in the laminated package of the present invention.

도 3b 및 도 3c는 적층패키지의 상부반도체칩에 삽입하는 보조연결기판의 배선에 대한 예시도.Figure 3b and Figure 3c is an illustration of the wiring of the auxiliary connecting substrate inserted into the upper semiconductor chip of the laminated package.

※ 도면의 주요부분에 대한 부호의 설명※ Explanation of code for main part of drawing

10A,10B : 반도체칩 11A,11B : 핀(pin)10A, 10B: Semiconductor chip 11A, 11B: pin

121∼127,...,12 : 헤더(header)121 to 127, 12, header

50A,50B : 반도체칩 501A,501B : 바디(body)50A, 50B: Semiconductor chip 501A, 501B: Body

52 : 보조연결기판 54 : 연결부52: auxiliary connection substrate 54: connection

01P∼27P,19PA,19PB: 핀(pin)01P ~ 27P, 19P A , 19P B : pin

이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체칩의 적층패키지는,The laminated package of the semiconductor chip according to the present invention for achieving the above object,

적층하기 위한 기판에 다수의 핀들을 연결하여 접합시킨 제1반도체칩; 및, 상기 제1반도체칩을 동작가능상태로 제어하는 선택핀의 위치에 해당하는 제2반도체칩의 선택핀을, 상기 제2반도체칩의 동작에 관련되지 않은 소정의 미연결핀들에 연결하기 위해 상기 제2반도체칩 하부에 삽입한 보조연결수단을 포함하며, 상기 제1도체칩의 상부에 위치시켜 상기 제2반도체칩의 소정의 핀을, 상기 제1반도체칩의 핀들에 연결하여 적층시킨 적어도 하나 이상의 제2반도체칩을 구비하고 있다.A first semiconductor chip connected to and bonded to a plurality of pins on a substrate for stacking; And connecting the selection pin of the second semiconductor chip corresponding to the position of the selection pin for controlling the first semiconductor chip to an operable state to predetermined unconnected pins not related to the operation of the second semiconductor chip. And an auxiliary connecting means inserted below the second semiconductor chip, the predetermined pins of the second semiconductor chip being positioned on the first semiconductor chip to be connected to and stacked on the pins of the first semiconductor chip. At least one second semiconductor chip is provided.

이하, 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 및 도 2b는 본 발명의 반도체칩의 적층패키지에 대한 사시도 및 단면도이다. 본 발명은 2개의 TSOP형 64M DRAM(64-Mega Synchronous Dynamic Random Access Memory) 반도체칩(50A,50B)을 이용하여 적층하는 것을 일실시예로 하여 설명한다.2A and 2B are a perspective view and a cross-sectional view of a laminated package of a semiconductor chip of the present invention. The present invention will be described by using two TSOP type 64M DRAM (64-Mega Synchronous Dynamic Random Access Memory) semiconductor chips 50A and 50B as one embodiment.

도 2a에 도시한 바와 같이, 본 발명에 따른 적층패키지는 PCB기판(인쇄회로기판, 미도시)에 최초로 접합시킨 반도체칩(50A)을 구비하고 있다. 그리고 이 상부에 적층하고자 하는 반도체칩(50B)을 위치시켜, 연결해야 하는 소정의 핀들(01P,02P, 03P,..., 단 19P는 미연결)을 연결시킨 층구조로 되어 있다.As shown in Fig. 2A, the laminated package according to the present invention includes a semiconductor chip 50A first bonded to a PCB substrate (printed circuit board, not shown). The semiconductor chip 50B to be stacked is placed on the upper portion of the semiconductor chip 50B, and predetermined pins 01P, 02P, 03P,..., But 19P are not connected.

본 발명의 반도체칩의 적층패키지에 이용되는 반도체칩(50A,50B)은 각 핀들의 기능이 동일하게 제작된 것이다. 하지만 반도체칩의 적층패키지를 완성 시킨후 정상적인 기능이 발휘되도록 하기 위해서, 본 발명의 예시에서는 반도체칩의 특정 핀(50B의 36P)의 기능에 변화를 주게 된다. 핀의 기능변화 등에 대해서는 뒤에서 자세히 설명한다.The semiconductor chips 50A and 50B used in the multilayer package of the semiconductor chip of the present invention are manufactured with the same function of each pin. However, in order to exhibit a normal function after completing the stacked package of the semiconductor chip, in the example of the present invention, the function of a specific pin (36P of the semiconductor chip) of the semiconductor chip is changed. The function change of the pins will be described later in detail.

이러한 변화를 주기 위해, 핀의 배선을 변화시킬 수 있는 보조연결수단의 하나인 PCB기판을 특정핀(pin)간이 연결되도록 배선하여 상부반도체칩(50B)의 바디(body; 501B)하부에 삽입하고, 이렇게 준비한 반도체칩(50B)을 하부의 반도체칩(50A) 상부에 위치시킨 후, 각각의 핀들사이에 전기적으로 잘 통하도록 솔더링(soldering)하여 적층하므로써 반도체칩의 적층패키지를 형성한다. 이렇게 하면, 도 2b에 도시한 바와 같이, 다수의 연결부(54)를 통해 상부 반도체칩(50B)의 19번핀(19PB)이 36번핀(36PB)에 연결되기 때문에 적층패키지의 특정단자(36P)의 기능에 변화를 주게 된다.To make this change, the PCB board, which is one of the auxiliary connecting means that can change the wiring of the pins, is wired so as to be connected between specific pins, and inserted under the body 501B of the upper semiconductor chip 50B. The semiconductor chip 50B thus prepared is positioned above the semiconductor chip 50A at the lower side, and then soldered and stacked so as to be electrically connected between the respective pins to form a stack package of the semiconductor chip. In this case, as shown in FIG. 2B, since the 19th pin 19P B of the upper semiconductor chip 50B is connected to the 36th pin 36P B through the plurality of connecting portions 54, the specific terminal 36P of the stacked package. ) Will change the function.

그리고, TSOP형 64M DRAM 반도체칩의 핀들은 최초 제작된 형태가 도 2a의 하부반도체칩(50A)의 핀들과 같은 형태(반사다리꼴같이 느슨한 `乙'자 형태)로 되어 있다. 따라서, 적층을 용이하게 하기 위해서는 이러한 형태의 핀구조를 상부반도체칩(50B)과 같이 `ㄱ'자 형태로 변형시키고 필요한 부분은 짧게 잘라(50B의 19P), 하부반도체칩의 해당 핀(50A의 19P)과 전기적으로 단락(open)되도록 해야 한다.In addition, the pins of the TSOP type 64M DRAM semiconductor chip have the same shape as the pins of the lower semiconductor chip 50A of FIG. 2A (loose '乙' shape). Therefore, in order to facilitate lamination, the fin structure of this shape is deformed into a shape of 'a' like the upper semiconductor chip 50B, and the necessary portion is cut short (19P of 50B), and the corresponding pin of the lower semiconductor chip (50A). 19P) should be electrically shorted.

도 3a는 본 발명의 적층패키지에 이용되는 반도체칩의 배면 핀배열을 도시한 것이고, 도 3b 및 도 3c는 적층하기 위한 상부반도체칩에 보조연결기판을 삽입되는 보조연결기판의 배선에 대한 예시도이다.3A illustrates a rear pin array of a semiconductor chip used in a multilayer package of the present invention, and FIGS. 3B and 3C are exemplary views of wiring of an auxiliary connector board in which an auxiliary connector board is inserted into an upper semiconductor chip for stacking. to be.

도시한 바와 같이, 본 발명의 적층패키지에 이용되는 64M SDRAM은 54개의 핀을 구비하고 있다. 54개 핀은 크게, 14개의 어드레스핀(A0∼A13), 4개의 데이터핀(DQ0∼DQ3), 반도체칩내부의 다이(die)와 연결되지 않은 15개의 NC핀(No Connection 핀), 그리고 반도체칩의 동작을 제어하기 위한 다수의 제어신호핀들로 구성되어 있다.As shown, the 64M SDRAM used in the laminated package of the present invention has 54 pins. The 54 pins are largely divided into 14 address pins (A0 to A13), 4 data pins (DQ0 to DQ3), 15 NC pins (No Connection pins) that are not connected to a die inside the semiconductor chip, and semiconductors. It consists of a number of control signal pins to control the operation of the chip.

본 발명에 따른 반도체칩의 적층패키지에서, 적층된 각각의 반도체칩(50A, 50B)을 동작할 수 있도록 선택하는 핀은, 19번의 CS(Chip Selection)핀이다. 즉 이 CS핀(19번)에 신호가 인가되어야, 반도체칩이 동작가능상태로 되는 것이다. 따라서, 도 2a 및 도 2b에 도시한 바와 같이 적층패키지의 두 반도체칩(50A,50B)을 각각 동작시키기 위해서는 두 반도체칩(50A,50B)의 CS핀의 위치를 서로 다르게 해야 한다.In the stacked package of the semiconductor chip according to the present invention, the pins selected to operate each of the stacked semiconductor chips 50A and 50B are No. 19 (Chip Selection) pins. In other words, when a signal is applied to the CS pin (19), the semiconductor chip becomes an operable state. Therefore, in order to operate the two semiconductor chips 50A and 50B of the stacked package as shown in FIGS. 2A and 2B, the CS pins of the two semiconductor chips 50A and 50B must be different from each other.

도 3b의 실시예에서는 CS핀의 위치를 변환시키기 위해, 상부에 적층하기 위한 반도체칩(50B)의 CS핀(19번)을, 다수의 NC핀들중의 하나인 36번 핀과 연결되도록 배선한 보조연결기판(52)을 상부반도체칩의 바디(body;501B)하부에 삽입한 것이다. 그리고 도 3c는 CS핀의 위치를 15번으로 변환시킨 일실시예를 도시한 것이다.In the embodiment of FIG. 3B, in order to change the position of the CS pin, the CS pin (19) of the semiconductor chip 50B to be stacked on top is wired so as to be connected to pin 36, which is one of the plurality of NC pins. The auxiliary connecting substrate 52 is inserted below the body 501B of the upper semiconductor chip. FIG. 3C illustrates an embodiment in which the position of the CS pin is converted to 15. FIG.

이렇게 변환시킨 도 3b 및 도 3c의 반도체칩은, 도 2a에 도시한 바와 같이 상부 반도체칩(50B)의 CS핀(19번)의 길이를 짧게 하여 적층시 전기적으로 단락시키므로써, 도 3b 및 도 3c의 반도체칩을 상부에 적층하는 경우 적층패키지의 36번단자 및 15번단자가 적층된 상부반도체칩(50B)을 동작가능상태로 제어하게 된다.The semiconductor chips of FIGS. 3B and 3C converted as described above are shortened by the length of the CS pin (No. 19) of the upper semiconductor chip 50B as shown in FIG. When the semiconductor chip of 3c is stacked on the top, the upper semiconductor chip 50B in which the terminals 36 and 15 of the stacked package are stacked is controlled to be in an operable state.

다수의 반도체칩을 적층시킨 반도체칩의 적층패키지를 형성할 경우에는, CS핀의 위치를 각각 서로 다른 위치로 변화시킨 반도체칩(도 3b 및 도 3c의 반도체칩)을 이용하여 적층하면 된다. 즉, 도 3a에 도시한 반도체칩을 PCB기판에 최초로 접합시키고, 그 상부에 도 3b 또는 도 3c의 반도체칩을 선택적으로 적층하면, 적층된 각각의 반도체칩을 동작가능상태로 하는 CS핀의 위치가 다르기 때문에, 적층된 반도체칩의 적층패키지를 원할하게 동작시킬 수 있다.In the case of forming a stack package of a semiconductor chip in which a plurality of semiconductor chips are stacked, the semiconductor chips (the semiconductor chips shown in FIGS. 3B and 3C) in which the positions of the CS pins are changed to different positions may be stacked. That is, when the semiconductor chip shown in Fig. 3A is first bonded to the PCB substrate and the semiconductor chips of Fig. 3B or 3C are selectively stacked on top of each other, the position of the CS pin for making each of the stacked semiconductor chips operable. Since is different, the stacked package of the stacked semiconductor chips can be smoothly operated.

전술한 바와 같이, CS핀은 해당 반도체칩을 동작가능상태로 만들어 주는 기능을 수행한다. 반도체칩은 해당 반도체칩만의 동작을 제어하는 제어 기능의 핀이전술한 CS핀 이외에도 다수 구비될 수도 있으며, 이 경우는 본 발명의 실시에서 설명한 개념에 근거하여 제어기능을 수행하는 핀들의 연결을 변화시키고 변화시킨 핀의 길이를 짧게 하여 적층하므로써, 다수의 반도체칩을 적층할 수 있다.As described above, the CS pin performs a function of making the semiconductor chip operable. The semiconductor chip may include a plurality of pins of the control function for controlling the operation of only the semiconductor chip, in addition to the aforementioned CS pin. In this case, connection of the pins for performing the control function based on the concept described in the embodiment of the present invention may be performed. A plurality of semiconductor chips can be stacked by shortening the changed and changed lengths of the pins.

상술한 바와 같이 본 발명은, 반도체칩의 특정 핀간을 연결하는 보조연결기판을 삽입하고, 적층할 반도체칩의 동작상태를 제어하는 선택핀의 길이를 짧게 변화시킨 후 적층하므로써, 반도체칩의 실장면적을 최소화하면서 다수의 반도체칩을 효율적으로 적층하는 효과를 제공한다.As described above, the present invention provides a mounting area of a semiconductor chip by inserting an auxiliary connecting substrate connecting specific pins of a semiconductor chip, and shortening the length of a selection pin for controlling an operation state of a semiconductor chip to be stacked. It provides an effect of efficiently stacking a plurality of semiconductor chips with a minimum.

Claims (6)

반도체칩을 적층시킨 구조에 있어서,In a structure in which semiconductor chips are laminated, 적층하기 위한 기판에 다수의 핀들을 연결하여 접합시킨 제1반도체칩; 및,A first semiconductor chip connected to and bonded to a plurality of pins on a substrate for stacking; And, 상기 제1반도체칩을 동작가능상태로 제어하는 선택핀의 위치에 해당하는 제2반도체칩의 선택핀을, 상기 제2반도체칩의 동작에 관련되지 않은 소정의 미연결핀들에 연결하기 위해 상기 제2반도체칩 하부에 삽입한 보조연결수단을 포함하며, 상기 제1도체칩의 상부에 위치시켜 상기 제2반도체칩의 소정의 핀을, 상기 제1반도체칩의 핀들에 연결하여 적층시킨 적어도 하나 이상의 제2반도체칩을 구비하는 것을 특징으로 하는 반도체칩의 적층패키지.The first pin for connecting the select pin of the second semiconductor chip corresponding to the position of the select pin for controlling the first semiconductor chip to be operable, to predetermined unconnected pins not related to the operation of the second semiconductor chip. At least one or more second connecting means inserted into the lower portion of the semiconductor chip, the predetermined pins of the second semiconductor chip connected to the pins of the first semiconductor chip by being positioned on the first semiconductor chip; A stack package of a semiconductor chip comprising a second semiconductor chip. 제 1항에 있어서, 상기 제1 및 제2 반도체칩은The method of claim 1, wherein the first and second semiconductor chips 상기 제1반도체칩을 동작가능상태로 제어하는 핀(pin) 및, 이에 해당하는 제2반도체칩의 핀은, 상기 제1 및 제2 반도체칩을 동작가능(enable)상태로 만들어 주는 반도체칩의 칩선택(CS;Chip Selection)핀인 것을 특징으로 하는 반도체칩의 적층패키지.A pin for controlling the first semiconductor chip to be in an operable state and a pin of the second semiconductor chip corresponding thereto are formed in the semiconductor chip for making the first and second semiconductor chips to be in an operable state. A stack package of a semiconductor chip, characterized in that it is a chip selection (CS) pin. 제 1항에 있어서, 상기 보조연결수단은The method of claim 1, wherein the auxiliary connecting means 상기 제2반도체칩의 동작에 관여되지 않는 소정의 미연결(NC;No Connection)핀에, 상기 제2반도체칩을 동작가능상태로 제어하는 핀을 전기적으로 연결하는 것을 특징으로 하는 반도체칩의 적층패키지.Stacking semiconductor chips electrically connected to a predetermined No Connection (NC) pin that is not involved in the operation of the second semiconductor chip, and a pin for controlling the second semiconductor chip to be operable. package. 제 1항에 있어서, 상기 제2반도체칩은The method of claim 1, wherein the second semiconductor chip 반도체칩의 적층을 용이하게 수행하기 위해, 상기 제1반도체칩의 상부에 적층되는 반도체칩의 핀들을 `ㄱ'자 형태로 변형하는 것을 특징으로 하는 반도체칩의 적층패키지.In order to facilitate stacking of the semiconductor chip, the semiconductor chip stack package characterized in that the pins of the semiconductor chip stacked on the upper portion of the first semiconductor chip is deformed in the form of a letter. 제 1항에 있어서, 상기 반도체칩의 적층패키지는The stack package of claim 1, wherein the stack package of the semiconductor chip is 상기 제1반도체칩을 동작가능상태로 제어하는 핀(pin)에 해당하는, 상기 제1반도체칩 상부에 적층되는 소정의 상부반도체칩의 핀의 길이를 짧게 변형하여, 상기 제1반도체칩의 해당 핀과 전기적으로 단락되도록 하는 것을 특징으로 하는 반도체칩의 적층패키지.The length of the pin of a predetermined upper semiconductor chip stacked on the first semiconductor chip, which corresponds to a pin for controlling the first semiconductor chip in an operable state, is shortened so that the corresponding of the first semiconductor chip can be changed. A laminated package of a semiconductor chip, characterized in that the pin and the electrical short. 제 1항에 있어서, 상기 반도체칩의 적층패키지는The stack package of claim 1, wherein the stack package of the semiconductor chip is 상기 제2반도체칩의 소정 핀에 전기적으로 연결하는 보조연결수단으로 PCB기판(인쇄회로기판)을 사용하는 것을 특징으로 하는 반도체칩의 적층패키지.Laminated package of a semiconductor chip, characterized in that a printed circuit board (PCB) is used as an auxiliary connection means for electrically connecting to a predetermined pin of the second semiconductor chip.
KR19980038739A 1998-07-23 1998-09-18 Piling-package of ic chips KR100276213B1 (en)

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JP10374773A JP3035534B2 (en) 1998-07-23 1998-12-28 Laminated package and method of laminating the same
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010086476A (en) * 2001-07-13 2001-09-13 신이술 Printed circuit board and package method of stacking semiconductor using therof
KR100376884B1 (en) * 2001-04-24 2003-03-19 주식회사 하이닉스반도체 Stack package
KR100677825B1 (en) * 2005-07-06 2007-02-02 (주)시스앤텍 Stacking flash memory chip and manufacturing method thereof
KR100766895B1 (en) * 2005-08-24 2007-10-15 삼성에스디아이 주식회사 Display apparatus

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Publication number Priority date Publication date Assignee Title
KR100418380B1 (en) * 2001-07-16 2004-02-11 주식회사 지아이씨하이테크 Method for heaping Semiconductor Package
KR20020035509A (en) * 2002-03-18 2002-05-11 주식회사 휴먼스텍 Stack package of semiconductor chip and method for fabricating the same
KR100460285B1 (en) * 2002-05-10 2004-12-08 차기본 A stack semiconductor package and it's manufacture method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100376884B1 (en) * 2001-04-24 2003-03-19 주식회사 하이닉스반도체 Stack package
KR20010086476A (en) * 2001-07-13 2001-09-13 신이술 Printed circuit board and package method of stacking semiconductor using therof
KR100677825B1 (en) * 2005-07-06 2007-02-02 (주)시스앤텍 Stacking flash memory chip and manufacturing method thereof
KR100766895B1 (en) * 2005-08-24 2007-10-15 삼성에스디아이 주식회사 Display apparatus

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