KR20000019790A - Module device in mpc860 processor - Google Patents

Abstract

PURPOSE: A module device in a MPC860 processor is provided to improve a reliability of a module by composing a MPC processor, a logic, memory, a glue logic as a module type. CONSTITUTION: A module device in a MPC860 processor comprises an Electrically Erasable Programmable ROM(EEPROM,100) for a booter, an address decoder(110), a MPC860 processor(120), a debugging port(130), a system memory(140), a glue logic(150), and an EEPROM for an information base memory(160). The address decoder decodes an address and a signal input and output to an outside. The MPC860 processor processes each protocol. The debugging port performs a download of a program by using only a processor module. The system memory stores an application program and each pa RAMeter. The glue logic generates a signal for controlling surrounding elements. The EEPROM for the information base memory stores a management information base for a network management system and sets an initial value of the processor.

Description

MP860 Processor Module Unit

The present invention relates to a module device of the MPC860 processor, and in particular, to implement the performance of the MPC860 processor in the case of mounting the MPC860 processor module, which is implemented to be used universally when the MPC860 processor is implemented in a plurality of boards, the required number of processor modules The present invention relates to an MPC860 processor module device that shortens the time taken to implement a processor module and improves reliability by implementing the remaining functions and developers implementing the remaining functions.

1 is a module implemented using three MPC860 processors in a conventional Integrated Services Digital Network (ISEA) PRI (Early Rate Interface) PRI (EEA) assembly, and has an ISDN PRI E1 interface of a remote access server (RAS). This is a functional block diagram of the board.

In the prior art, when a plurality of processors are implemented in one board as in the case of the module, that is, when two MPC860MHs and one MPC860EN, which are processors of a specific company, are implemented, the three processors are required for normal operation of the module. All should work normally. In addition, this module cannot be used if one processor does not operate normally.

Therefore, the problem of the prior art as described above is that all three processors have to operate normally, so that the development period is long, and the reliability of the module is also deteriorated at all times.

Therefore, the present invention was devised to solve the above problems, and the MPC860 processor and peripheral logic (Booter, memory, glue logic, etc.) to make the module type of general purpose of the motherboard It is an object of the present invention to provide an MPC860 processor module device that can be mounted and used according to a required quantity.

The above and other objects and novel features of the present invention will become more apparent from the following detailed description of the invention and the accompanying drawings.

1 is a functional block diagram of an ISDN PRI subscriber module implemented with a conventional multiprocessor according to the present invention.

2 is a functional block diagram of an entire ISDN PRI board using a processor module in accordance with the present invention.

3 is a processor module block diagram in accordance with the present invention.

Figure 4 is a table showing the input and output signals to the outside of the processor module according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: line connection part 20a, 20b: MPC860 processor module

30: memory unit 40: function processing unit

50: common processor unit 60: system bus connection unit

100: from EEPROM 110: address decoder

120: MPC860 processor 130: debug port

140: system memory 150: glue logic

160: EEPROM for configuration and management information base (MIB) memory

A preferred embodiment of the MPC860 processor module device according to the present invention, which was created to achieve the above object, is implemented with a conventional EEPROM and PLD for initialization, and an address decoder and main for decoding an address and a signal input and output from the outside. MPC860 processor that processes channels for cross-processor communication with the board, and various protocols such as PPP, MLPPP, V.120, HDLC, and frame relay, and is connected to the MPC860 processor. Debugging port to download and test program by itself, system memory (SRAM) to store application program and various parameters, glue logic to make signals necessary to control peripheral devices, and management information base for network management system A phrase that stores data and sets the initial value of the processor. EEPROM for sex and management information base memory.

The preferred embodiment of the ISDN PRI board device using the MPC processor module according to the present invention created to achieve the above object is composed of a transmission line interface device and a framer, depending on the role of the board ISDN PRI or frame relay, etc. Line connection that connects T1 or E1 with switch that has interface of, has protocol processing function to implement ISDN PRI board function, handles ISDN D channel signal processing, and handles V.120 and subscriber protocols such as PPP and MLPPP. MPC860 process module to perform, a function processing unit and a system bus connection unit for transmitting subscriber data and subscriber data, data status reporting and command transfer function to the upper control unit through the initialization function of the line connection unit and information exchange with the MPC860 processor module To control the function processing unit and the system bus connection unit. It includes a common processor with Ethernet connectivity and debug.

The ISDN PRI board according to the present invention has been invented for a remote access server (RAS) which is widely utilized for economical service provision and efficient and diverse service provision of Internet service providers (ISPs). It provides a primary rate interface (PRI) of an ISDN (Integrated Services Digital Network), and is a device having a function for simultaneously accommodating ISDN terminal subscribers and modem subscribers. That is, in order to serve both ISDN and non ISDN with one device, it has a structure that can connect to an Internet service provider using a packet bus which is a backbone.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, the peripheral logic (from, memory, glue logic, etc.), which is essential for versatility with the MPC860 processor, is constructed and made into a module type.

2 is an overall functional block diagram of an ISDN PRI board using a processor module. As shown in FIG. 2, the configuration of the present invention is a configuration in which the MPC860 processor module is used, and the function-specific roles are as follows.

The line connection unit 10 is a module serving as a T1 / E1 trunk composed of a transmission line interface unit (LIU) and a framer, and has an interface such as an ISDN PRI or a frame relay, depending on the role of the board. It can be connected to the exchange by E1 or T1. That is, in this connection, two internal time division multiplex (TDM) bus termination functions among the internal functions of the processor module can handle the E1 / T1 channel.

MPC860 process module (20a, 20b) is a module in which the function of the present invention is implemented, has the protocol processing function to handle ISDN D channel signal processing to implement the function of the ISDN PRI board, V.120 and PPP (Point-to It performs subscriber protocols such as -Point Protocol) and MLPPP (Multi-Link PPP). It also manages subscribers such as IP assignment, management, and deletion. In addition, it has a function of processing the data input from the function processing unit 40 and the system bus connection unit 60, etc. to be sent to the line connection unit or vice versa.

The function processing unit 40 and the system bus connection unit 60 perform subscriber data transfer functions with the server connection unit.

The common processor unit 50 performs data initialization and command transfer functions to the upper control unit through the initialization function of the line connection unit 10 and the information exchange with the MPC860 processor modules 20a and 20b. It controls the system bus connection 60 and has an Ethernet connection and debug function.

3 is a processor module block diagram in accordance with the present invention. Looking at each function of the processor module as follows.

The MPC860 processor 120 processes channels for interprocessor communication modules (IPC) and common protocols such as PPP, MLPPP, V.120, HDLC, and Frame Relay with a common processor of a main board on which the processor module is mounted. It can be implemented according to the type of protocol to be handled by the motherboard, such application program and various parameters can also be stored in the system memory 140 implemented as SDRAM (Synchronous DRAM) to implement. .

The upper 24 bits and 32 bits of data among 32 bits of the address 32 bits input and output from the MPC860 processor 120, CS * (Chip Select), IRQ * (Interrupt Request), WR * (Write), WE * (Write Enable), TA * ( Memory between processor module and main board by connecting signals such as Transfer Acknowledge (DMAREQ), DMAREQ (DMA Request), DMAACK (DMA Acknowledge), TDM Bus, 232c signals, various Reset, Master / Slave signals, etc. B. I / O devices and devices with specific functions can be adjusted and made accessible so that signals that are used universally can be made to meet the desired functions, and the necessary signals can be selected to implement the functions. can do.

SDRAM, the system memory 140, can be extended to a maximum storage size of 32 Mbytes, and the memory size can be variably adjusted as necessary, and has a function of storing an application program.

The conventional EEPROM 100 is for initialization, and an EEPROM (Electronically Erasable Programmable ROM) 160 for a configuration and management information base (MIB) memory is a network management system that can be written according to a user's implementation function. It is used to store management information base data for Network Management System (NMS) and to set the initial value of the processor.

The debugging port 130 allows a 232C serial port to be connected to a PC, allowing the program to be downloaded and tested with this module alone.

The address decoder 110 implemented as a programmable logic device (PLD) may decode the address and the CS *.

Glue logic 150 is a logic composed of a buffer, etc., while minimizing the size of the module, the function is implemented to have general purpose. This creates the signals needed to control the devices around the processor.

4 is a list of signals input and output through the connector in the processor module, so that only the signals input and output from the board to which the processor module is applied can be used.

While the invention is susceptible to various modifications and alternative forms, the disclosure thereof has been described with reference to specific embodiments only. It is to be understood, however, that the present invention is not limited to the specific forms referred to in the specification, but rather that the invention is intended to cover all modifications, equivalents, and substitutions within the spirit and scope of the invention as defined by the appended claims. It should be understood to include.

In the present application operating as described above, the effects obtained by the representative ones of the disclosed inventions will be briefly described as follows.

It is possible to reduce the development time and increase the reliability by easily implementing the multi-processor by applying the universal module, and to apply the various protocol requirements of the subscriber and the system by supplementing the program modification in the processor module without affecting the system. You can download the program and test it using your own serial port.

Claims (6)

Standard EEPROM for initialization; An address decoder implemented with a PLD and decoding an address and a signal input and output from the outside; An MPC860 processor that processes and performs channels for interprocessor communication with the main board and various protocols such as PPP, MLPPP, V.120, HDLC, and frame relay; A debugging port connected to the MPC860 processor and capable of connecting to a PC so as to download and test a program using only the processor module itself; System memory (SRAM) for storing application programs and various parameters; Glue logic for producing signals necessary to control peripheral devices; And An MPC860 processor module device comprising an EEPROM for configuration and management information base memory for storing management information base (MIB) data for a network management system and setting an initial value of the processor. The processor of claim 1, wherein the MPC860 processor connects a signal input and output to the outside through a connector of a processor module to adjust a memory, an I / O device, or a device performing a specific function between the processor module and the motherboard. MPC860 processor module apparatus for selecting and writing a required signal of the signals to enable. 2. The MPC860 processor module device of claim 1, wherein the system memory is expandable up to 32 Mbytes so that the memory size can be variably adjusted as needed. A line connection part composed of a transmission line interface device and a framer, and connected to an exchanger having an interface such as an ISDN PRI or a frame relay to T1 or E1 according to a role of a board; An MPC860 process module that has a protocol processing function to implement functions of an ISDN PRI board, is in charge of processing ISDN D channel signals, and performs subscriber protocols such as V.120 and PPP and MLPPP; A function processing unit and a system bus connection unit for transferring the server connection unit and subscriber data; And It performs data status reporting and command transfer function to the upper control unit through the initialization function of the line connection unit and the information exchange with the MPC860 processor module, controls the function processing unit and the system bus connection unit, and has an Ethernet connection and debug function. ISDN PRI board device using the MPC processor module, including a common processor unit. 5. The ISDN of claim 4, wherein the line connection unit has two time division multiple bus termination functions among internal functions of the processor module when connecting to the switch with E1 or T1, and processes an E1 / T1 channel. PRI board device. 5. The MPC860 processor module of claim 4, wherein the MPC860 processor module manages subscribers by providing, managing, and deleting an IP, and processes data inputted from the function processor and the system bus connection, and sends the data to the line connection. ISDN PRI board device using the MPC processor module, which also handles the opposite case.