KR20000018930U - Apparatus for detecting surface resistance of semiconductor wafer - Google Patents

Apparatus for detecting surface resistance of semiconductor wafer Download PDF

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Publication number
KR20000018930U
KR20000018930U KR2019990005217U KR19990005217U KR20000018930U KR 20000018930 U KR20000018930 U KR 20000018930U KR 2019990005217 U KR2019990005217 U KR 2019990005217U KR 19990005217 U KR19990005217 U KR 19990005217U KR 20000018930 U KR20000018930 U KR 20000018930U
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South Korea
Prior art keywords
wafer
surface resistance
semiconductor wafer
prober
seating portion
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KR2019990005217U
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Korean (ko)
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류종암
호원준
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김영환
현대반도체 주식회사
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Priority to KR2019990005217U priority Critical patent/KR20000018930U/en
Publication of KR20000018930U publication Critical patent/KR20000018930U/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2648Characterising semiconductor materials

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

본 고안은 반도체 웨이퍼의 표면저항측정장치에 관한 것으로, 본체(11)의 상면에 안착부(15)와 요입부(17)를 연속적으로 형성하고, 그 요입부(17)의 내측에는 프로버(16)를 이동가능하게 설치하며, 안착부(15)에는 웨이퍼(14)를 흡착하기 위한 수개의 버큠홀(18)을 형성하여서 구성되어, 웨이퍼(14)의 표면저항 측정시 런 웨이퍼(14)를 안착부(15)에 고정시킨 다음 프로버(16)로 런 웨이퍼(14)의 뒷면을 프로빙한 상태에서 표면저항을 측정할 수 있도록 하여, 종래와 같이 더미 웨이퍼를 별도로 준비하지 않는데 따른 비용절감의 효과가 있다.The present invention relates to a surface resistance measuring apparatus of a semiconductor wafer, and the seating portion 15 and the recessed portion 17 are continuously formed on the upper surface of the main body 11, and a prober (inside the recessed portion 17) is provided. 16 is movably provided, and the seating portion 15 is formed by forming several vent holes 18 for adsorbing the wafer 14, so that the wafer 14 when measuring the surface resistance of the wafer 14 is formed. Is fixed to the seating portion 15 and then the surface resistance can be measured while the back side of the run wafer 14 is probed with the prober 16, thereby reducing the cost of not separately preparing a dummy wafer as in the prior art. Has the effect of.

Description

반도체 웨이퍼의 표면저항측정장치{APPARATUS FOR DETECTING SURFACE RESISTANCE OF SEMICONDUCTOR WAFER}Surface resistance measuring apparatus for semiconductor wafers {APPARATUS FOR DETECTING SURFACE RESISTANCE OF SEMICONDUCTOR WAFER}

본 고안은 반도체 웨이퍼의 표면저항측정장치에 관한 것으로, 특히 런 웨이퍼의 뒷면 표면저항을 측정할 수 있도록 하여 더미 웨이퍼의 사용을 배제할 수 있도록 하는데 적합한 반도체 웨이퍼의 표면저항측정장치에 관한 것이다.The present invention relates to a surface resistance measuring apparatus of a semiconductor wafer, and more particularly, to a surface resistance measuring apparatus of a semiconductor wafer suitable for enabling the measurement of the surface resistance of the back surface of a run wafer so as to eliminate the use of a dummy wafer.

일반적으로 반도체 웨이퍼 제조공정중 폴리(POLY)로 막을 만들고 포클(PoCl3) 처리를 해서 P가 폴리막질로 들어가도록 하여 캐리어 역할을 하는 도체로 사용하도록 포클도핑하는 공정에서 도핑작업을 마친 웨이퍼들의 표면저항(RS)을 측정하게 되는데, 이와 같은 표면저항을 측정하는 표면저항측정장치가 도 1에 도시되어 있는 바, 이를 간단히 설명하면 다음과 같다.In general, during the semiconductor wafer manufacturing process, the surface of the wafers that have been doped in the process of forming a film from poly (POLY) and performing a fockle (PoCl 3 ) to allow P to enter the poly film to be used as a carrier acting as a carrier. The resistance (RS) is measured, and a surface resistance measuring apparatus for measuring such a surface resistance is shown in FIG. 1, which will be briefly described as follows.

도 1은 종래 반도체 웨이퍼의 표면저항측정장치를 보인 사시도로서, 도시된 바와 같이, 종래 표면저항측정장치는 웨이퍼(1)가 얹혀지는 본체(2)에 커버(3)가 개,폐가능토록 설치되어 있고, 그 커버(3)의 하측에는 웨이퍼(1)의 일정부분을 프로빙하기 위한 프로버(4)가 설치되어 있으며, 상기 본체(2)의 전면에는 저항값을 디스플레이하기 위한 디스플레이 윈도우(5)가 설치되어 있다.1 is a perspective view showing a surface resistance measuring apparatus of a conventional semiconductor wafer. As shown in the drawing, the conventional surface resistance measuring apparatus is installed so that the cover 3 can be opened and closed on the main body 2 on which the wafer 1 is placed. A prober 4 for probing a portion of the wafer 1 is provided below the cover 3, and a display window 5 for displaying a resistance value on the front of the main body 2. ) Is installed.

상기와 같이 구성되어 있는 종래 반도체 웨이퍼의 표면저항측정장치에서는 도핑작업을 마친 더미 웨이퍼(1)를 도 2와 같이 본체(2)의 상면에 올려놓고, 커버(3)를 본체(2) 측으로 닫아서 커버(3)의 하측에 설치되어 있는 프로버(4)의 탐침(4a)이 더미 웨이퍼(1)의 상면을 프로빙하도록 한다. 그와 같은 상태에서 표면저항값이 측정이 되고, 측정된 표면저항값은 디스플레이 윈도우(5)를 통하여 디스플레이된다.In the conventional semiconductor wafer surface resistance measuring device configured as described above, the dummy wafer 1 having been doped is placed on the upper surface of the main body 2 as shown in FIG. 2, and the cover 3 is closed to the main body 2 side. The probe 4a of the prober 4 provided under the cover 3 allows the top surface of the dummy wafer 1 to be probed. In such a state, the surface resistance value is measured, and the measured surface resistance value is displayed through the display window 5.

그러나, 상기와 같은 종래 반도체 웨이퍼의 표면저항측정장치는 웨이퍼(1)의 상면을 프로빙 하도록 되어 있어서, 실제사용하는 런 웨이퍼를 측정하는 경우에 양품으로 사용하는 것이 불가능하여 항상 별도의 더미 웨이퍼(1)를 제작하여 표면저항을 측정하게 되므로 그에 따른 비용절감에 한계가 있는 문제점이 있었다.However, the surface resistance measuring apparatus of the conventional semiconductor wafer as described above is to probe the upper surface of the wafer 1, so that it is impossible to use it as a good product when measuring the actual use wafer. ) To measure the surface resistance, there was a problem in that there is a limit in reducing the cost.

상기와 같은 문제점을 감안하여 안출한 본 고안의 목적은 런 웨이퍼의 뒷면 표면저항을 측정할 수 있도록 하여 더미 웨이퍼의 사용을 배제하는데 따른 비용을 절감할 수 있도록 하는데 적합한 반도체 웨이퍼의 표면저항측정장치를 제공함에 있다.The object of the present invention devised in view of the above problems is to provide a surface resistance measuring apparatus of a semiconductor wafer suitable for reducing the cost of eliminating the use of dummy wafers by measuring the surface resistance of the back surface of the run wafer. In providing.

도 1은 종래 반도체 웨이퍼의 표면저항측정장치의 구조를 보인 사시도.1 is a perspective view showing the structure of a surface resistance measuring apparatus of a conventional semiconductor wafer.

도 2는 종래 더미 웨이퍼의 표면저항을 측정하는 상태를 보인 종단면도.Figure 2 is a longitudinal sectional view showing a state of measuring the surface resistance of the conventional dummy wafer.

도 3은 본 고안 반도체 웨이퍼의 표면저항측정장치의 구조를 보인 사시도.Figure 3 is a perspective view showing the structure of the surface resistance measuring apparatus of the inventive semiconductor wafer.

도 4는 본 고안 반도체 웨이퍼의 표면저항측정장치에서 검사되는 상태를 보인 단면도.4 is a cross-sectional view showing a state of being inspected in the surface resistance measuring apparatus of the inventive semiconductor wafer.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

11 : 본체 14 : 런 웨이퍼11 body 14 run wafer

15 : 안착부 16 : 프로버15: seating portion 16: Prover

17 : 요입부17: recessed part

상기와 같은 본 고안의 목적을 달성하기 위하여 본체의 상면에 안착부와 요입부를 연속적으로 형성되어 있고, 그 요입부의 내측에 런 웨이퍼의 뒷면을 프로빙하기 위한 프로버가 이동가능하게 설치되어 있으며, 상기 안착부의 상면에는 안착부에 안착되는 런 웨이퍼를 진공흡착하기 위한 수개의 버큠홀이 형성되어 있는 것을 특징으로 하는 반도체 웨이퍼의 표면저항측정장치가 제공된다.In order to achieve the object of the present invention as described above, a seating portion and a recessed portion are continuously formed on the upper surface of the main body, and a prober for probing the back side of the run wafer is provided inside the recessed portion to be movable. An apparatus for measuring surface resistance of a semiconductor wafer is provided on an upper surface of a seating portion, in which a plurality of burr holes are formed for vacuum adsorption of a run wafer seated on the seating portion.

상기와 같이 구성되어 있는 본 고안 반도체 웨이퍼의 표면저항측정장치를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Referring to the embodiment of the accompanying drawings, the surface resistance measuring apparatus of the inventive semiconductor wafer configured as described above will be described in more detail as follows.

도 3은 본 고안 반도체 웨이퍼의 표면저항측정장치의 구조를 보인 사시도로서, 도시된 바와 같이, 본 고안 반도체 웨이퍼의 표면저항측정장치는 본체(11)의 후단부에는 커버(12)가 개,폐가능토록 설치되어 있고, 전면에는 디스플레이 윈도우(13)가 설치되어 있다.3 is a perspective view showing the structure of the surface resistance measuring apparatus of the semiconductor wafer of the present invention. As shown, the surface resistance measuring device of the semiconductor wafer of the present invention has a cover 12 open and closed at the rear end of the main body 11. It is installed so that it is possible, and the display window 13 is provided in the front surface.

그리고, 상기 본체(11)의 상면에는 런 웨이퍼(14)를 안착시키기 위한 안착부(15)와 프로버(16)가 위치되는 요입부(17)가 연속적으로 형성되어 있고, 그안착부(15)에는 등간격으로 수개의 버큠홀(18)이 형성되어 있다.In addition, a seating portion 15 for seating the run wafer 14 and a recessed portion 17 in which the prober 16 is positioned are continuously formed on the upper surface of the main body 11, and the seating portion 15 ), Several vent holes 18 are formed at equal intervals.

상기와 같이 구성되어 있는 본 고안 반도체 웨이퍼의 표면저항측정장치는 도핑공정을 마친 런 웨이퍼(14)를 본체(11)에 형성된 안착부(15)에 얹어 놓고, 안착부(15)에 형성된 버큠홀(18)에 버큠을 작동시켜서 웨이퍼(14)를 흡착고정한다.The surface resistance measuring apparatus of the inventive semiconductor wafer structured as described above is mounted on the seating portion 15 formed in the main body 11 after the doping process has been completed, and a burr hole formed in the seating portion 15. The wafer 14 is sucked and fixed by actuating the valve 18.

상기와 같은 상태에서 커버(12)를 닫고, 프로버(16)를 이동시켜서 측정하고자 하는 런 웨이퍼(14)의 뒷면 일정부분을 도 4와 같이 프로빙하며, 그와 같은 상태에서 표면저항을 측정하여 디스플레이 윈도우(13)를 통하여 디스플레이하고, 측정을 마친 런 웨이퍼(14)는 폐기하지 않고 후공정을 계속진행하게 된다.By closing the cover 12 in the above state, and moving the prober 16 to probe the back portion of the run wafer 14 to be measured as shown in Figure 4, by measuring the surface resistance in such a state The run wafer 14, which is displayed through the display window 13 and has completed the measurement, is continued without any waste.

이상에서 상세히 설명한 바와 같이, 본 고안 반도체 웨이퍼의 표면저항측정장치는 본체의 상면에 안착부와 요입부를 연속적으로 형성하고, 그 요입부의 내측에는 프로버를 이동가능하게 설치하며, 안착부에는 웨이퍼를 흡착하기 위한 수개의 버큠홀을 형성하여서 구성되어, 웨이퍼의 표면저항 측정시 런 웨이퍼를 안착부에 고정시킨 다음 프로버로 런 웨이퍼의 뒷면을 프로빙한 상태에서 표면저항을 측정할 수 있도록 하여, 종래와 같이 더미 웨이퍼를 별도로 준비하지 않는데 따른 비용절감의 효과가 있다.As described in detail above, the surface resistance measuring apparatus of the inventive semiconductor wafer continuously forms a seating portion and a recessed portion on the upper surface of the main body, and installs a prober inside the recessed portion so that the prober is movable. It is composed by forming several burr holes for adsorption, and fixing the run wafer to the seating part when measuring the surface resistance of the wafer, and then measuring the surface resistance while probing the back side of the run wafer with a prober. As described above, there is an effect of reducing the cost of not separately preparing a dummy wafer.

Claims (1)

본체의 상면에 안착부와 요입부를 연속적으로 형성되어 있고, 그 요입부의 내측에 런 웨이퍼의 뒷면을 프로빙하기 위한 프로버가 이동가능하게 설치되어 있으며, 상기 안착부의 상면에는 안착부에 안착되는 런 웨이퍼를 진공흡착하기 위한 수개의 버큠홀이 형성되어 있는 것을 특징으로 하는 반도체 웨이퍼의 표면저항측정장치.A seating portion and a recessed portion are continuously formed on the upper surface of the main body, and a prober for probing the rear surface of the run wafer is provided on the inner side of the recessed portion so as to be movable. Surface resistance measurement apparatus of a semiconductor wafer, characterized in that several vacuum holes for vacuum suction.
KR2019990005217U 1999-03-31 1999-03-31 Apparatus for detecting surface resistance of semiconductor wafer KR20000018930U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100940415B1 (en) * 2007-12-03 2010-02-02 주식회사 동부하이텍 On resistance test method for back-side-drain wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100940415B1 (en) * 2007-12-03 2010-02-02 주식회사 동부하이텍 On resistance test method for back-side-drain wafer

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