KR20000016513A - Method and apparatus for compiling one circuit in a sequence of circuits within a programmable gate array - Google Patents

Abstract

PURPOSE: Disclosed is a method and apparatus for compiling one circuit in a sequence of circuits within a programmable gate array. CONSTITUTION: A programmable gate array (70) including a plurality of logic gates can be programmed to constitute a series of configurations chosen to consist of a series of circuits. The series of circuits are chosen to accomplish a desired communication ability. Depending upon the circumstances of operation, the series of circuits can initially consist of a grouping of communications initialization circuits, then later a grouping of communications maintenance circuits, and still later a grouping of communications termination circuits.

Description

Method and apparatus for compiling one of the continuous circuits in a programmable gate array

Personal communication is at an unprecedented stage in performance. With the advent of improved personal communication services such as cellular phones and low earth orbit satellite services, these performance advances also benefit mobile users. Similarly when used in portable computers and other personal data communicators, advances in performance not only benefit voice communications, but also data communications.

The difficulty in expanding services is that a wide variety of different voice and data communication protocols have been proposed. This diversity is expected to increase globally and regionally. For example, each communication service has its own technical, regional and characteristic set. Technical parameters include frequency, modulation and protocols, among others. Local parameters are defined by specific places. The feature set refers to whether the service is voice, paging, data, or a combination thereof.

As a result, a given communication device becomes less useful when a user wishes to use it in an area using incompatible services. For example, when people who rely on mobile communications move during the day, they cannot enter or leave other coverage areas. So their communication needs will always change. In addition, even within a region, a given communication device becomes less useful as established performance is degraded by newer services. It is not desirable for an individual to have a different communication device for each communication service. In addition, few would like to know the details and characteristics of each of the available communication services. Most will want to have a smooth service that is simple to use, convenient and cost-effective.

Therefore, it is desirable to have one personal communication service device that is configured to be compatible with any communication service required. This is difficult with the prior art.

Detailed description of the invention

The present invention relates to a method and apparatus for communicating information, and more particularly, to a method and apparatus for changing a communication service.

1 is a schematic diagram of an interface structure according to an embodiment of the present invention;

2 is a schematic diagram of a physical structure according to an embodiment of the present invention;

3 is a block diagram according to one embodiment of the present invention when used as a terminal emulator;

4 is a block diagram according to one embodiment of the present invention when used as a facsimile transmitter / receiver emulator;

5 is a block diagram according to one embodiment of the present invention when used as a communication device emulator;

6 is a block diagram according to one embodiment of the present invention when used as a wireless local area network emulator;

7 is an operation block diagram of the present invention;

8 is an operational block diagram of the present invention in an embodiment incorporating several digital personal communication services;

9 is a flowchart of a call processing operation of the present invention;

10 is a timing diagram for the processing operation of a terrestrial outgoing call according to the present invention;

11 is a timing diagram for the processing operation of a mobile outgoing call according to the present invention;

12 is a schematic diagram of a functional structure according to an embodiment of the present invention;

13 is a schematic diagram of the functionality of the software in the present invention;

14 is a block diagram of the software architecture of the present invention;

15 is a table for the dynamic configuration mode of the present invention;

16 is a schematic diagram of a dynamic configuration mode of the present invention;

17 is a schematic diagram of a runtime reconfigurable architecture of the present invention;

18 is a schematic diagram of a symmetric array structure for use with the present invention;

19 is a schematic diagram of a bus network symmetry structure used in the present invention;

20 is a schematic diagram of a cell structure for use in the present invention;

21 is a flow chart for a standalone design environment of a field programmable gate array for use with the present invention;

22 is a flow chart of the design environment of a field programmable gate array for use with the present invention;

23 is a schematic diagram of an analog front end for use in the present invention; And

24 is a schematic diagram of digital hardware for use in the preferred embodiment of the present invention.

1 to 24 are schematic representations of preferred embodiments, which will be better understood by those skilled in the art when combined with the description of the embodiments below.

1 is a schematic diagram of an interface structure according to an embodiment of the present invention. The interface device 50 includes an interface 52 (such as a PCMCIA interface), a protocol 54, an intermediate frequency (IF) stage 56, and a connector 58 (such as an analog pigtail). The interface 52 receives and transmits signals between the interface device 50 and an external device (not shown), such as a computer having a PCMCIA slot. The protocol 54 interprets the signal from the interface 52 and transmits the interpretation to the IF stage 56. The protocol 54 also receives signals from the IF stage 56 and converts them into signals for transmission over the interface 52 according to the appropriate protocol. Connector 58 communicates signals with IF stage 56 for transmission to and from external communication services. The external communication service can be connected in a wired or wireless manner as known in the art.

2 is a schematic diagram of a physical structure according to an embodiment of the present invention. In FIG. 2, interface device 50 is a configurable device 70 (such as a field programmable gate array (FPGA) or other bulk gate device), a memory (such as flash random access memory (RAM)) 72, hard drive 74, and connector 58 are shown. The configurable device 70 is connected to an external device (not shown), such as a computer, and processes the signal for transmission to and from the memory 72. Hard drive 74 communicates with memory 74 and transmits signals to and from connector 58 for transmission to and from external communication services. The external communication service may be connected in a wired or wireless manner such as that known in the art.

3 is a block diagram according to an embodiment of the present invention when used as a terminal emulator. Terminal emulator device 90 includes an interface 52 coupled to configurable circuit 92, signal processing circuit 94, first memory 96, and second memory 98. The signal processing circuit 94 is in communication with the configurable circuit 92, the first memory 96, and the second memory 98. The signal processing circuit 94 also communicates with an external communication service. The external communication service may be connected by a wired or wireless manner known in the art.

Configurable circuit 92 is arranged to respond to signals from interface 52, signal processing circuit 94, flash memory 96, and RAM 98, such that interface 52 and signal processing circuit 94 Ensures proper transmission of communication signals between

4 is a block diagram according to one embodiment of the present invention when used as a facsimile transmitter / receiver emulator. The facsimile transmitter / receiver emulator 110 includes an interface 52 connected to the configurable circuit 92. The configurable circuit 92 is also connected to the first specific facsimile circuit 112, the flash memory 114, the RAM 116, the second special purpose facsimile circuit 118, and the signal conditioning circuit 120. The signal conditioning circuit 120 allows communication with a compatible device (not shown), such as a telephone or external speaker.

The configurable circuit 92 is arranged to respond to signals from the interface 52, the first and second specific purpose facsimile circuits 112 and 118, the flash memory 114, and the RAM 116, and thus the interface 52. ) And the facsimile signal between the signal conditioning circuit 120.

5 is a block diagram of one embodiment of the present invention when used as a communication device emulator. Communication device emulator 130 includes interface 52, configurable circuit 92, A / D converter 132, specific signal conditioning circuit 134, flash memory 136, RAM packet memory 138, and RAM. Memory 140. In general, communication device emulator 130 communicates via analog signals even though communication through digital signals is possible. The signal transmitted over interface 52 is received and processed by configurable circuit 92. Configurable circuit 92 is in communication with specific signal conditioning circuit 134, flash memory 136, RAM packet memory 138, and RAM memory 140. The A / D converter 132 communicates with the flash memory 135, the RAM packet memory 138, and the RAM memory 140. The particular signal conditioning circuit 134 is arranged to communicate with a compatible device (not shown), such as a computer or terminal.

The configurable circuit 92 is arranged to respond to signals from the interface 52, the specific signal conditioning circuit 134, the flash memory 136, the RAM packet memory 138, and the RAM memory 140, so that the interface ( 52) and a particular signal conditioning circuit 134 to properly transfer the facsimile signal.

6 is a block diagram of one embodiment of the present invention when used as a wireless local area network emulator. The wireless local area network (LAN) emulator 150 includes an interface 52, configurable circuits 92, address translation circuits 152, interface circuits 154, flash memory 156, and RAM 158. . Interface circuit 154 includes signal processing circuit 160 and second configurable circuit 162. Configurable circuit 92 is in communication with signal processing circuit 160, flash memory 156, and RAM 158. The address translation circuit 152 communicates with the signal processing circuit 160, the flash memory 156, and the RAM 158. The signal received by the signal processing circuit 160 from the configurable circuit 162 and the address translation circuit 152 is converted into a form for processing by the second configurable circuit 162, which is in accordance with known procedures. It may be formed if necessary. The processing result signal of the second configurable circuit 162 is transmitted to a wireless communication device, such as a baseband transceiver. Similarly, a signal from the wireless communication device is received by the second configurable circuit 162 and converted into a form compatible with the signal processing circuit 160. The signal processing circuit 160 then generates a signal for reception by the configurable circuit 92 and / or the address translation circuit 152 that processes the signal and sends it to the interface 52.

7 is a block diagram of the operation of the present invention, showing the functionality performed by the hardware described above.

8 is a block diagram of the operation of the present invention in an embodiment incorporating several digital personal communication services. Personal communicator 170 includes an antenna 172 coupled to RF power amplifier 174. Personal communicator 170 also includes an RF small signal circuit 176, a filter 178, and an IF stage 180. The RF small signal circuit 176 is coupled to the RF power amplifier 174. The signal generated by the small signal circuit 176 is sent to the filter 178, and then to the IF stage 180. As shown in FIG. 8, the function of this part of the personal communicator serves as a combined voice and RF A / D and D / A device as well as a homodyne RF transceiver.

The output of the IF stage 180 is transmitted to the voice A / D and D / A circuit 182. Circuit 182 performs appropriate analog-to-digital and digital-to-analog operations to send the results to the integrated baseband voice data and image circuitry 184. Circuit 184 includes a microcontroller 186, a modem equalizer 188, a channel coder 190, and a voice coder 192. The microcontroller 186 is connected to the circuit 182, and the signal generated by the microcontroller 186 is connected to the modem equalizer 188. The signal generated by the modem equalizer 188 is sent to a channel coder 190 which generates a signal that is sent to the voice coder 192. Circuit 184 converts the signal from circuit 182 into a form suitable for use with speaker 194 and multimedia terminal 196.

It will be appreciated by those skilled in the art that the signals from the speaker 194 and the multimedia terminal 196 may be converted by the personal communicator 170 in a form for transmission by the antenna 172 to a remote service or user.

9 is a flowchart of a call processing operation that can be understood by one skilled in the art of communication. After the DC power start task step (block 500), the next step is to initialize the communicator 170 by the dedicated channel scan task step (block 502). If no valid message is received, the task returns to the power initiated task step (block 500). On the other hand, if a valid message is received, the task proceeds to select a paging channel task step (block 504). If no valid message is received, the task returns to the power initiated task step (block 500). If registration is instructed, the task proceeds to an automatic registration task step (block 508). However, if a valid message is received at the paging channel selection task step (block 504), the task proceeds to an idle task step (block 508).

In the idle task step (block 506), there are several options. 1) If no valid message is received, 2) only if the rescan timer times out after 300 seconds, and 3) if a rescan message is received, the task proceeds to a power initiation task step (block 500). If registration is instructed, the task proceeds to an automatic registration task step (block 508). If initiation of a call is indicated, the task proceeds to an initial task step (block 510). If a command message is received, the task proceeds to a command response task step (block 512). If a page message is received and a page match occurs, the task proceeds to a paging response task step (block 514). If the expected event occurs, the task stays in an idle task step (block 506).

The auto-registration task step (block 508) includes an access channel scan. If initiation of a call is indicated, the task proceeds to an initial task step (block 510). Otherwise, the task proceeds to serving system determination task step (block 516) regardless of whether a valid message has been received.

If the task is in the initial task stage (block 510) and no valid message is received, the task proceeds to the serving system determination task stage (block 516). On the other hand, if a valid message is received, the task proceeds to the conversation task step (block 518).

Regardless of whether a valid message has been received, from command response task step (block 512), the task proceeds to serving system determination step (block 516). From the paging response task step (block 514), if no valid message is received, the task proceeds to the serving system determination task step (block 516). However, if a valid message is received, the task proceeds to a command waiting task step (block 520) (block 520).

There are four possible states to reach from the dialog task step (block 518). If the fade timer times out after 5 seconds, the task proceeds to a transmitter release task step (block 518). If a release command is received or the conversation ends by pressing the END key of the communicator 170, the task proceeds to a release task step (block 524). If a warning or maintain command is received, the task proceeds to the wait for response task step (block 526). If no command or action is received, the task returns to the dialog task step (block 518).

From the wait for response task step (block 526), the task returns to the chat task step (block 518) when a chat enable signal is received by pressing the SEND key of the communicator 170. If an end warning command is received, the task proceeds to a command waiting task step (block 520). If a release command is received, the task proceeds to a release task step (block 524). Finally, if the 5 second fade timer times out or the 64 second warning timer times out, the task proceeds to a transmitter release task step (block 522).

From the wait for command task step (block 520), the task proceeds to wait for response task step (block 526) when a warning or maintain command is received. However, if a release command is received, the task proceeds to a release task step (block 524). Finally, if the 65 second warning timer times out or the conversation ends by pressing the END key of communicator 170, the task proceeds to a transmitter release task step (block 522).

From the release task step (block 524), the task proceeds to a transmitter release task step (block 522), and from the transmitter release task step (block 522), the task proceeds to a serving system determination task step (block 516). From the serving system determination task step (block 516), the task goes to an initialization task step (block 502) if the serving system state is not set to NAM. On the other hand, if the serving system state is set to NAM, the task goes to the paging channel selection task step (block 504).

10 is a timing diagram for the processing operation of the ground-initiated call according to the present invention, and FIG. 11 is a timing diagram for the processing operation of the mobile-initiated call according to the present invention. It will be appreciated by those skilled in the art that these timing diagrams each graphically represent a sequence of transmission signals required to handle telephone calls initiated from terrestrial base stations and mobile users.

As shown in Fig. 10, in the case of a ground-initiated call, the system first transmits a signal (duration time 26 microseconds) from the base station to the mobile terminal using all signaling channels. At this time, the channel 0 is transmitted with a response indication. Next, using the appropriate local signaling channel, the mobile responds by sending a ready state indication to the base station. Following this, again using the local signaling channel, the appropriate base station sends a signal to the mobile, which is accompanied by a switch request to voice channel 12. Then, in voice channel 12, the mobile responds to the base station by instructing execution of the command. Using the voice channel, the base station sends a ring signal to the mobile, and in response the mobile sends an off-hook signal to the base station, where the voice channel is used.

In Figure 11, the case of a mobile-initiated call is shown. Using the mobile for the base station signaling channel, the mobile first sends its own address and request channel assignment command. Next, using the assigned channel, the base station signals to the mobile station, giving it its own channel assignment. The mobile device then signals the base station on the assigned channel, informing it of the channel assignment and requesting a dial tone. In response to the request, the base station sends a dial tone signal to the mobile, using the assigned channel.

12 is a schematic diagram of a functional structure according to an embodiment of the present invention. The communication device 200 includes an interface card 202 and an analog pigtail 204. The interface card 202 may be, for example, a PCMCIA type II card. Interface card 202 includes a PCMCIA connector 206 for connection to host system 208. The interface card 202 also includes a protocol engine 210, a dynamically programmable intermediate modulation stage 212 and a memory portion 214. The protocol engine 210 and the intermediate modulation stage 212 are connected to the PCMCIA connector 206. Memory unit 214, which may include a hard drive, static RAM, and flash RAM, communicates with protocol engine 210 and intermediate modulation stage 212.

The interface card 202 is connected to the analog pigtail 204, which serves to communicate information with various means for communicating with the user, such as antennas, modulators, demodulators and modems, microphones, speakers, and others. Provide other components to Personal communication device 200 preferably operates at a UHF (or higher) frequency, such as 800-900 MHz, acts as a joint paging receiver, a fax modem operates at baseband, and other communication devices are also known in the art. Known as known art.

13 is a schematic diagram of the software functionality of the present invention, illustrating the advantages provided by software running on a computer connected to an accessible network.

14 is a block diagram of the software architecture of the present invention. At the highest level, the software of the present invention facilitates communication with external communication services. This level of software communicates with software for communication within a personal communicator, including host level drivers, serial I / O operators, local area networks, and the like. At a low level, the personal communicator's software runs background applications, controls file systems, performs power management, and controls the I / O transport stack. Internal software also acts as an embedded digital signal manager and controls functions such as phone stacking, call management, call control, and more.

At a lower level, the software of the personal communicator drives the reconfiguration operation system used to control the reconstruction circuitry of the personal communicator.

15 is a table for the dynamic configuration mode of the present invention, Figure 16 is a schematic diagram of the dynamic configuration mode of the present invention. As shown in FIG. 16, the operation of the dynamic configuration mode activates a task stored in the configuration mode memory 220 and loads the task into a portion of the reconfigurable circuit 222. As the condition indicates, the task can be repositioned within the reconfigurable circuit 222 or can be adjusted to accommodate the changing condition.

17 is a schematic diagram of a runtime reconfigurable architecture of the present invention. Software from read-only memory 250 is used to boot the system when the system is activated. The system is booted by loading into configurable file work storage 252, which may be part of several memory devices included in the personal communicator. A group of system applications is also stored in system memory 254, which responds to signals from download control circuitry 256. The download control circuit 256 is connected to the interface 52. Interface 52 is in communication with configurable circuit 92. As schematically shown, configurable circuit 92 is loaded into a number of programs having several predetermined characteristics.

Under control of the signal from the download control 256, certain characteristics that are not already present in the configurable circuit 92 are loaded from the system memory 254 into the working storage 252, and from there into the configurable circuit 92. do. When the characteristic present in the configurable circuit 92 is no longer needed, the software providing the characteristic is removed from the configurable circuit 92 and the software providing the remaining characteristic is new software for providing a new predetermined characteristic. May move around on configurable circuit 92 before it is loaded into configurable circuit 92.

18 is a schematic diagram of a symmetric array structure used in the present invention, and FIG. 19 is a schematic diagram of a bus network symmetry structure used in the present invention.

FIG. 20 is a schematic diagram of the cell structure used in the present invention, particularly for the symmetric array structure shown in FIGS. 18 and 19. FIG. As will be appreciated, the cell structure includes processing elements, logic gates and timing circuits to achieve the desired result.

Figure 21 is a flow chart for a standalone design environment of a field programmable gate array used in the present invention. The flowchart shows an overview generation, represented by design entries, logic simplification and optimization, pre-layout timing and functional verification, and bitstream generation including certain software.

Figure 22 is a flow chart of the design environment of a field programmable gate array used in the present invention, as will be appreciated by those skilled in the art.

23 is a schematic diagram of an analog front end used in the present invention. The front end 300 includes an antenna 302 and a diplexer 304. The signal received by the antenna 302 and passed through the diplexer 304 passes through the bandpass filter 306 and the amplifier 308 to the mixer 310. Mixer 310 mixes the RF signal generated by amplifier 308 with the local oscillator signal generated by synthesizer 312 and driven by crystal 314. The signal output by the mixer 310 passes through the bandpass filter 318 to a user who may be an analog user or a digital user.

The signal generated by the microphone 120 is received by another mixer 322, which is also provided with an RF signal by the synthesizer 312. The output of the mixer 322 is passed through the bandpass filter 322 and the output of the mixer 322 is received by another mixer 322, which is also provided with an RF signal by the synthesizer 312. The output of mixer 322 passes through bandpass filter 324 to amplifier 326. The output of the amplifier 326 is input to a diplexer 304 which serves to transmit a signal to an antenna 302 for transmission as electromagnetic waves.

24 is a schematic diagram of digital hardware used in the preferred embodiment of the present invention. Device 350 includes an interface 52, first and second configurable circuits 352, 354. The first configurable circuit 352 is connected to the interface 52 and the second configurable circuit 354. The interface 52 is also connected to the second interface 354. Device 350 also includes third configurable circuit 356, fourth configurable circuit 358, microcontroller 360, RAM 362, and flash RAM 364. The first and second configurable circuits 352 are connected to the third configurable circuit 356, the microcontroller 360, the RAM 362, and the flash RAM 364. The fourth configurable circuit 358 is connected to the third configurable circuit 356 and the microcontroller 360. Under the control of the microcontroller 360, the first, second, third and fourth configurable circuits 352, 354, 356 and 358 are configured to achieve the desired functionality of the apparatus 350 according to the principles discussed above. . As described above, certain characteristics may be stored in the RAM 362 and the flash RAM 364.

Although the foregoing is a detailed description of preferred embodiments of the present invention, those skilled in the art will be able to make many modifications even within the scope of the disclosure. Therefore, it is intended that the scope of the invention be defined by the following claims.

Claims (15)

A method of compiling one of the continuous circuits in a plurality of programmable gate arrays (PGAs) having a plurality of logic gates, the method comprising: a) setting a first lower majority logic gate in the PGA, wherein the first lower majority logic gate consists of a logic gate that is not currently being used as part of an existing circuit in the continuous circuit; b) determining which of the existing circuits in the continuous circuit are decompileable circuits, each decompileable circuit including distinct lower multiple logic gates available in the PGA to other circuits in the continuous circuit; ; c) determining a second lower majority logic gate in the PGA, wherein the second lower majority logic gate is a logic gate taken from a set of logic gates defined by the first set of lower majority logic gates and a decoded gate in the PGA. A lower number of unused logic gates that are distinguished in the existing circuit determined as a compileable circuit; d) determining a third lower majority logic gate in a PGA that is a subset of the second lower majority gate, the third lower majority being connectable to form a circuit; And e) coupling a gate to compile a circuit in the third lower majority logic gate in the PGA. 2. The circuit of claim 1, wherein step b) includes determining which subset of the existing circuits can be decompiled and then recompiled to reconstruct the subset of the existing circuits. Creating a logic gate within the PGA that is available to the PGA. 2. The apparatus of claim 1, wherein the existing circuitry receives a corresponding set of input signals to produce a corresponding set of output signals, each of the input and output signals having a value at a given time. At least one of the output signals generated by one is an input signal to one of the other existing circuits, and f) storing at least one value of the input and output signals at the predetermined time to supply the signal having the stored value to the one And applying to the circuit. A method of compiling one of the continuous circuits in a programmable gate array (PGA) having multiple logic gates, the method comprising: a) determining which of the existing circuits in the continuous circuit are decompileable circuits, each decompileable circuit comprising a distinct lower majority logic gate available in the PGA available to other circuits in the continuous circuit; Each decompileable circuitry receives at least one corresponding input signal and generates at least one corresponding output signal in response to the at least one corresponding input signal, each of the input signal and the output signal being constant; Has a value at time; And b) storing a value of at least one of said input or output signal at said predetermined time. The method of claim 4, wherein c) decompiling at least one of the decompileable circuits; And d) applying a signal whose value is stored in step b) to one of said continuous circuits. A device for compiling one of the continuous circuits in a programmable gate array (PGA) having multiple logic gates A first electronic circuit for setting a first lower majority logic gate in the PGA, the first lower majority logic gate comprising a logic gate that is not currently being used as part of an existing circuit in the continuous circuit; A second electronic circuit that determines which of the existing circuitry in the continuous circuit is a decompileable circuit, each decompileable circuit including a distinct lower majority logic gate available in the PGA to other circuitry within the continuous circuit To; A third electronic circuit for determining a second lower majority logic gate in the PGA, wherein the second lower majority logic gate is a logic gate taken from a set of logic gates defined by a set set of the first lower majority logic gate and in the PGA; A lower number of unused logic gates distinguished from the existing circuitry determined as decompileable circuitry; A fourth electronic circuit that determines a third lower majority logic gate in a PGA that is a subset of the second lower majority gate, the third lower majority being connectable to form one circuit; And And a fifth electronic circuit connecting a gate to compile a circuit in the third lower multiple logic gate in the PGA. 7. The continuous circuit of claim 6, wherein the second electronic device comprises an electronic circuit that determines which subset of the existing circuit can be recompiled after being decompiled to reconstruct the subset of the existing circuit. And build a logic gate in the PGA that is available to other circuits. 7. The apparatus of claim 6, wherein the existing circuitry receives a corresponding set of input signals to generate a corresponding set of output signals, each of the input and output signals having a value at a given time. At least one of the output signals generated by one is an input signal to one of the other existing circuits, A memory circuit which stores a value of at least one of the input and output signals at the predetermined time; and And a sixth electronic circuit for applying the signal having the stored value to the one circuit. An apparatus for compiling one of the continuous circuits in a programmable gate array (PGA) having multiple logic gates, A first electronic circuit that determines which of the existing circuitry in the continuous circuit is a decompileable circuit, each decompileable circuitry comprising in the PGA a distinct lower majority logic gate available to other circuitry in the continuous circuit; Wherein each decompileable circuitry receives at least one corresponding input signal and generates at least one corresponding output signal in response to the at least one corresponding input signal, wherein each of the input signal and the output signal Has a value at a given time; And And a second electronic circuit for storing a value of at least one of the input or output signal at the predetermined time. The method of claim 9, A third electronic circuit to decompile at least one of the decompileable circuits; And And a fourth electronic circuit whose value is retrieved and applied to one of the continuous circuits by searching for the value of the signal stored by the second electronic circuit. A device for compiling one of the continuous circuits in a programmable gate array (PGA) having multiple logic gates First means for establishing a first lower majority logic gate in the PGA, the first lower majority logic gate comprising a logic gate that is not currently being used as part of an existing circuit in the continuous circuit; As a second means for determining which of said existing circuits in said continuous circuit are decompileable circuits, each decompileable circuit including distinct lower multiple logic gates available in said PGA to other circuits in said continuous circuit; ; Third means for determining a second lower majority logic gate in the PGA, wherein the second lower majority logic gate is a logic gate taken from a set of logic gates defined by the set of first lower majority logic gates and a decoded gate in the PGA. A lower number of unused logic gates that are distinguished in the existing circuit determined as a compileable circuit; Fourth means for determining a third lower majority logic gate in a PGA that is a subset of the second lower majority gate, the third lower majority being connectable to form a circuit; And And fifth means for connecting a gate to compile a circuit in the third lower multiple logic gate in the PGA. 12. The method of claim 11, wherein the second means includes an electronic circuit that determines which subset of the existing circuit can be recompiled after being decompiled and reconfigured the subset of the existing circuit. And build a logic gate in the PGA that is usable for another circuit. 12. The apparatus of claim 11, wherein the existing circuitry receives a corresponding set of input signals to produce a corresponding set of output signals, each of the input and output signals having a value at a given time. At least one of the output signals generated by one is an input signal to one of the other existing circuits, Memory means for storing a value of at least one of the input and output signals at the predetermined time; and And a sixth electronic means for applying the signal having the stored value to the one circuit. An apparatus for compiling one of the continuous circuits in a programmable gate array (PGA) having multiple logic gates, First means for determining which of said existing circuits in said continuous circuit are decompileable circuits, each decompileable circuit including a distinct lower majority logic gate available in a PGA available to other circuitry within said continuous circuit; Each decompileable circuitry receives at least one corresponding input signal and generates at least one corresponding output signal in response to the at least one corresponding input signal, each of the input signal and the output signal being constant; Has a value at time; And And second electronic means for storing at least one value of the input or output signal at the predetermined time. The method of claim 14, Third electronic means for decompiling at least one of the decompileable circuits; And And fourth electronic means for retrieving and applying the value of the signal stored in the second electronic means to one of the continuous circuits.