KR20000015352A - Circuit for adjusting an automatic gain in a will(wireless local loop) system - Google Patents

Abstract

PURPOSE: An AGC(Automatic Gain Control) circuit is provided to regularly adjust a gain of an IF(Intermediate Frequency) signal, to the rate of eight-bit on an IF board in a wireless local loop(WILL) system. CONSTITUTION: An AGC(Automatic Gain Control) circuit in a base station of a wireless local loop(WILL) system, amplifies and attenuates an IF(Intermediate Frequency) signal gain in the regular level, according to an inputted voltage control, so that the gain maintains the regular value, after filtering a required band of the IF signal, outputted rom a RF(Radio Frequency section) in the base station of the WILL. The AGC circuit removes noises of an I signal and a Q signal through an I,Q mixer, a low-pass filter, and an OP AMP(Operational Amplifier), and amplifies in the regular level. The amplified I signal and the Q signal is converted to eight-bit digital data, is temporarily latched, and is outputted to a channel card in the base station. The eight-bit digital data is address-inputted through a memory element called RPROM, operated according to a system clock. The stored eight-bit gain control data is outputted by being pre-calculated according to the inputted address, and the outputted gain control data is converted to an analog signal by integrating, and is outputted after adding up to the analog.

Description

Automatic Gain Control Circuit in Base Station of Wireless Subscriber Network System

The present invention relates to an IF (Intermediate Frequency) board in a base station of a wireless local loop (hereinafter, referred to as a "WLL") system, and to code division multiple access (hereinafter, referred to as "CDMA"). In the WLL system, a memory-based gain control circuit used in a base station of a mobile communication system employing the method is modified so that the gain of the IF signal can be constantly adjusted at an 8-bit sampling rate. It relates to an automatic gain control (hereinafter referred to as "AGC") circuit in the base station.

In general, the WLL system is a system that forms a link using a wireless system instead of a wired line from a telephone station to a subscriber terminal. It is expected to play an important role in building information infrastructure in the future.

Such a WLL system includes a radio station unit (hereinafter referred to as a "RIU") for constituting a radio link with a base station, a base station for forming a radio link with the RIU, wired to a telephone exchange, And a base station controller and a telephone exchange for controlling the base station.

On the other hand, in a CDMA mobile communication system such as a digital cellular system (hereinafter, referred to as a "DCS") or a personal communication system composed of a mobile station, a base station, a control station, and a switching station, the mobile station and a wireless station IF board that processes analog and digital signal to convert analog IF signal of RF part into digital signal between RF part and channel card in base station performing access control, the gain level of IF signal is adjusted A memory-based gain control circuit is used to obtain the demodulation output.

That is, the AGC circuit in the base station of the CDMA mobile communication system using the memory-based gain control circuit as shown in Fig. 1 is a band pass filter (1), voltage control amplifier (2), I mixer (3-1), Q mixer (3-2), low pass filter (4-1, 2), OP amplifiers (5-1, 2), A / D converters (6-1, 2), memory (7), D / A converters 8, consisting of an integrator 9, inputs 4 digitized I, Q signals through the A / D converters 6-1, 2 to the address of the memory 7, and stores 8 Outputs the gain control data of the bit, converts the output data into an analog signal through the D / A converter 8, passes through the integrator 9, and then outputs the voltage control amplifier 2 to the voltage control amplifier ( In 2), a constant value is maintained by amplifying or attenuating the gain of the IF signal passing through the band pass filter 1 according to the voltage control signal for gain control of the IF signal.

At this time, if the level of the analog signal before passing through the A / D converters 6-1 and 2 is too small, the upper bits of the I signal and the Q signal become zero.

In the AGC circuit as described above, data for controlling the voltage control amplifier 2 for each address is pre-calculated and stored in the memory 7. Therefore, the 8-bit digital data is stored by adding 4 bits of I signal and 4 bits of Q signal. With the address input of (7), the gain of the voltage control amplifier 2 can be adjusted according to the data value previously stored in the address.

However, the WLL system is designed for wide bandwidth in consideration of Integrated Service Digital Network (hereinafter, referred to as 'ISDN') service, so that the analog IF signal of the RF part of the base station is converted into an A / D digital signal of 8 bits or more. It needs to be designed to convert.

The present invention has been made in view of the above, and an object thereof is to change the memory-based gain control circuit used in a base station of a CDMA mobile communication system from an IF board in a base station of a WLL system to an IF signal at an 8-bit sampling rate. The purpose of the present invention is to provide an AGC circuit in a base station of a WLL system in which the WLL system can accommodate a wideband ISDN service by adjusting the gain of the constant.

1 is a block diagram of an automatic gain control circuit in a base station of a conventional CDMA mobile communication system;

2 is a block diagram of an automatic gain control circuit in a base station of a wireless subscriber network system according to the present invention;

3 is a view showing a memory table structure according to the present invention.

<Description of the symbols for the main parts of the drawings>

11 bandpass filter 12 voltage control amplifier

13-1: I mixer 13-2: Q mixer

14-1,2: Low pass filter 15-1,2: OP amplifier

16-1,2: A / D converter 17-1,2: D flip flop

18-1,2: Alpyrom 19-1,2: D / A converter

20-1,2: integrator 21: analog adder

The AGC circuit in the base station of the WLL system of the present invention for achieving the above object is a voltage control signal inputted so as to filter only the desired band of the IF signal output from the base station RF portion of the WLL system, the gain is kept constant According to the present invention, the gain of the IF signal is amplified or attenuated by a certain level.Then, the I, Q mixer, the low pass filter, and the OP amplifier generate I, Q signals, remove the noise of the I, Q signals, and then amplify them again. After converting the amplified I and Q signals into 8-bit digital data, they are temporarily latched and output to the channel card in the base station, and the 8-bit digital data is stored through a memory element called apyrom that operates according to a system clock. Is inputted to output 8-bit gain control data that has been previously calculated and stored according to the input address, and the output gain control data is output. After converting to an analog signal, it is integrated, added to the analogue, and then outputted to control the gain of the IF signal constantly.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the AGC circuit in the base station of the WLL system according to the present invention.

2 is a block diagram of an AGC circuit in a base station of a WLL system according to the present invention, and a band pass filter (BPF) for passing only a desired band of an IF signal output from an RF part of a base station of a WLL system (11). And a voltage controlled amplifier (VCA) 12 that amplifies or attenuates a predetermined level so that the gain of the IF signal passing through the band pass filter 11 is maintained at a constant value according to the input voltage control signal. And a mixer 13-1 for outputting an I signal by mixing a gain-controlled IF signal and a local signal having a phase of 0 ° in the voltage controlled amplifier 12, and the voltage controlled amplifier 12. Q mixer 13-2 for outputting a Q signal by mixing a gain-controlled IF signal with a local signal having a phase of 90 DEG and outputs the I mixer 13-1 and Q mixer 13-2. A low pass filter (LPF) 14-1, 2 for removing noise of a signal, and each of the low OP amplifiers 15-1, 2 for a predetermined level amplification of the IF signal passing through the reverse pass filters 14-1, 2, and amplified by the respective OP amplifiers 15-1, 2 according to the system clock. A / D converters 16-1 and 2 for converting analog IF signals into 8-bit digital data and digital data converted by the respective A / D converters 16-1 and 2 are latched. D flip-flops 17-1 and 2, which are output to a channel card in the base station and gain control data for controlling the voltage control amplifier 2, are calculated in advance and stored for each address, and the system clock is stored. By using the digitized I and Q signals outputted through the respective D flip-flops 17-1 and 2 as address inputs, an apyrom outputting the 8-bit gain control data stored in advance according to this input address ( RPROM) 18-1, 2 and 8-bit gain control data output from the respective apyroms 18-1, 2 as analog signals. The integrators 20-1 and 2 integrating the converted D / A converters 19-1 and 2, the analog signals converted in the respective D / A converters 19-1 and 2, and the respective It is composed of an analog adder (Analog summing) 21 for outputting the voltage control signal to the voltage control amplifier 12 by analog addition of the output value of the integrator 20-1,2.

While the conventional AGC circuit is suitable for a narrow-band CDMA system, the resultant bits of the A / D converters 6-1 and 2 are too low to be applied to the WLL system. The converters 16-1 and 2 have an 8-bit result, and accordingly, the calculated values of the tables of the alpha pyroms 18-1 and 2 are also converted into new values to use the converted values.

3 is a diagram illustrating a table structure of a memory according to the present invention, that is, the apyroms 18-1 and 2, in which a value calculated in advance according to an input address is output, and the calculated value is determined according to the address.

That is, the present invention calculates the energy estimates for the I and Q signals through the Alpyroms (18-1, 2) to generate a voltage control signal for gain control using the calculated values.

Referring to the operation of the AGC circuit in the base station of the WLL system according to the present invention configured as described above are as follows.

First, when only the desired band of the IF signal output from the RF section of the base station of the WLL system is passed through the band pass filter 11, the voltage control amplifier 12 generates a band according to the voltage control signal output from the analog adder 21. The IF signal is amplified or attenuated by a certain level so that the gain of the IF signal passing through the pass filter 11 is maintained within a constant value, i.e., a total of 20 dB.

That is, the reason for adjusting the level of the IF signal as described above is that the inputs of the A / D converters 16-1 and 2 should be within a certain range.

Subsequently, the I mixer 13-1 mixes the IF signal adjusted by the voltage control amplifier 12 with a local signal having a phase of 0 ° to output an I signal, and the Q mixer 13-2 outputs the I signal. The voltage control amplifier 12 outputs a Q signal by mixing a gain-controlled IF signal with a local signal having a phase of 90 °.

Then, after removing the noise of the I signal and the Q signal output from the I mixer 13-1 and the Q mixer 13-2 through the respective low pass filters 14-1 and 2, each OP The amplifier 15-1 and 2 pass through the low pass filters 14-1 and 2 and amplify a predetermined level of the IF signals of the I and Q signals.

Thereafter, the A / D converters 16-1 and 2 convert the analog IF signal amplified by the OP amplifiers 15-1 and 2 into 8-bit digital data according to the system clock. The digital data is temporarily latched on the D flip-flops 17-1, 2 and output to the channel card in the base station.

At this time, the gain adjustment control signal according to the 8-bit I signal and the Q signal output from the D flip-flop 17-1, 2 is generated through the Alpyroms 18-1, 2 operating according to the system clock. do.

In other words, each of the apyroms 18-1 and 2 inputs 8 bits of digital data output from the D flip-flops 17-1 and 2 as an address. Output gain control data.

Accordingly, each of the D / A converters 19-1 and 2 converts the 8-bit gain control data output from the Alpyroms 18-1 and 2 into an analog signal, and then each integrator 20-1. (2) integrates an analog signal between 0 and 1 V converted by the D / A converters 19-1 and 2.

The time constants of the integrators 20-1 and 2 determine the response of the AGC loop circuit according to the present invention.

Thereafter, the analog adder 21 adds the output values of the integrators 20-1 and 2 to output the voltage control signal to the voltage control amplifier 12.

As described above, in the present invention, the amplification and attenuation operations of the voltage control amplifier are performed through a voltage control configuration using an apyrom, a D / A converter, and an integrator so that the level of the IF signal output to the channel card in the base station of the WLL system is kept constant. Take control.

As described above, the present invention provides a memory based gain control circuit used in a base station of a CDMA mobile communication system by adding an A / D converter and an Alpyrom memory element for outputting an IF signal at a sampling rate of 8 bits. By changing, the IF board of the base station of the WLL system can more effectively control the gain of the IF signal.

Claims (1)

A band pass filter 11 for passing only a desired band of the IF signal output from the RF section in the base station of the WLL system, and a gain of the IF signal passing through the band pass filter 11 according to the input voltage control signal is a constant value. An I-mixer for outputting an I signal by mixing a voltage-controlled amplifier 12 which is amplified or attenuated by a certain level so as to be maintained at a predetermined level, and a IF signal gain-adjusted by the voltage-controlled amplifier 12 and a local signal having a phase of 0. 13-1), a Q mixer 13-2 for outputting a Q signal by mixing the IF signal gain-adjusted in the voltage control amplifier 12 with a local signal having a phase of 90 DEG, and the I mixer 13 -1) and a low pass filter (14-1, 2) for removing the noise of the output signal of the Q mixer 13-2, and the IF signal passed through each of the low pass filters (14-1,2) OP amplifiers 15-1 and 2 for constant level amplification, and analog amplifiers amplified by the respective OP amplifiers 15-1 and 2 according to a system clock. The A / D converters 16-1 and 2 converting the IF signal into 8-bit digital data and the digital data converted by the respective A / D converters 16-1 and 2 are latched and then stored in the base station. The D flip-flops 17-1 and 2 outputted to the channel card and the gain control data for controlling the voltage control amplifier 2 are calculated in advance and stored for each address, and the respective D flip-flops according to the system clock. Alpiroms (18-1, 2) for outputting 8-bit gain control data stored in advance according to the input address, using the digitized I and Q signals output through (17-1, 2) as address inputs; D / A converters 19-1, 2 for converting 8-bit gain control data output from the respective apyroms 18-1, 2 into analog signals, and the respective D / A converters 19-. Integrators 20-1 and 2 for integrating the analog signals converted in 1 and 2), and output values of the respective integrators 20-1 and 2 are analogized. And an analog adder (21) for adding and outputting a voltage control signal to the voltage control amplifier (12).