KR20000013742A - Single port random access memory in a semiconductor memory device - Google Patents

Abstract

PURPOSE: A single port RAM(Random Access Memory) is provided to reduce a layout area and a time delay caused by an increased length of wiring by preventing an interference between bit lines. CONSTITUTION: A bit cell of the single port RAM comprises: a latch circuit; a first and a second word lines elongated along a row direction; a first and a second bit lines disposed along a column direction, the bit lines being transposed with the first and the second word lines; a first and a second transfer transistors for connecting the first and the second bit lines with the latch circuit according to a voltage level.

Description

SINGLE PORT RAM OF SEMICONDUCTOR MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a bit cell of a single port RAM.

Referring to FIG. 1, a bit cell of a single port RAM according to the related art includes first and second word lines W / L1 and W / L1b extending in a row direction and first and second columns extending in a column direction. It is connected to the second bit lines B / L1 and B / L1b, respectively. The bit cell is composed of transistors PM1, PM2, NM1, NM2 and first and second transfer transistors N1, N2. The transistors PM1, PM2, NM1, and NM2 are composed of two inverters connected to intersect input / output terminals. The first transfer transistor N1 transfers charges from the first bit line B / L1 to the gates of the transistors PM1 and NM1 according to the voltage level of the first word line W / L1. do. The second transfer transistor N2 transfers charges from the second bit line B / L1b to the gates of the latch transistors PM2 and NM2 according to the voltage level of the first word line W / L1. To pass.

2A to 2C, the bit cell of FIG. 2A is in a row direction with the transistors PM1, PM2, NM1, NM2, P1, N1 formed on an active region on a semiconductor substrate (not shown). The first and second word lines W / L1 and W / L1b extending along the first side and the first and second bit lines B / L1 and B / L1b extending along the column direction. . FIG. 2B is a layout of a spacer cell for supplying voltage to the semiconductor substrate and the bulk of the transistors PM1, PM2, NM1, NM2, P1, and N1. The single port RAM requires the spacer cell at a ratio of one per four bit cells to supply voltage to the semiconductor substrate and the bulk of the transistors PM1, PM2, NM1, NM2, P1, and N1. . FIG. 2C is a simplified diagram of the layout of FIG. 2A. Referring to FIG. 2C, the bit cell has the first word line (W / L1) region 4 and the second word line (W / L2) region 5 extending in the row direction on the upper layer of the active region. And a region 6 of the first bit line B / L1 region 7 and a second bit line B / L1b extending in the column direction on the upper layers of the word lines regions 2 and 3. It has a structure that is arranged.

Referring to FIG. 3, no signal lines can be arranged in the upper layer of the bit cell in which the bit line regions 6 and 7 are formed as the uppermost layer. For example, when the wirings of a signal for an operation other than the write or read operation of the bit cell, that is, the upper layer of the bit cell are arranged, data is written to the bit cell or data stored in the bit cell is read. In this case, a malfunction may occur in which the data of the first and second bit lines B / L1 and B / L1b are modified by interference of a signal flowing through the wires. As a result, wirings of signals unrelated to the operation of the bit cell cannot be arranged in the upper layer of the bit cell, but wirings metal4 and metal5 must be arranged around the bit cell. Such an arrangement of the wirings metal4 and metal5 causes other signal delays in wasting the layout area of the bit cell and increasing the length of the wirings metal4 and metal5.

The bit line present in the single port RAM has a very large capacitance. However, since the driving capability of the transistor for driving the bit line is very small compared to the capacitance, the bit line is susceptible to other signals independent of data writing or reading operations. However, the bit lines B / L1 and B / L1b regions 2 and 3 of the structure shown in FIG. 2C are located at the uppermost layer of the bit cell. Thus, when the wirings metal4 and metal5 for routing other signals not related to the operation of the memory cell are arranged in the upper layer of the memory cell, the signals are transferred to the bit lines B / L1 and B. / L1b) can not be prevented. Accordingly, as shown in FIG. 3, the wirings metal4 and metal5 may be arranged around the memory cell to ensure stability of operation. However, when the wiring is performed as described above, the length of the wiring increases, which causes a problem of waste of an area on the layout and an increase in signal delay due to an increase in the wiring length.

Accordingly, an object of the present invention is to provide a single port RAM of a semiconductor memory device which can reduce the layout area and reduce the delay time caused by the increase in the wiring length by preventing the interference generated in the bit line.

1 is a circuit diagram showing a bit cell of a single port RAM according to the prior art;

2A through 2C illustrate a layout structure of the bit cell of FIG. 1;

3 shows a wiring arranged on an upper layer of the bit cell of FIG. 1;

4 is a circuit diagram showing a bit cell of a single port RAM according to the present invention;

5A and 5B show a layout structure of the bit cell of FIG. 4;

FIG. 6 is a diagram illustrating a wiring arranged on an upper layer of the bit cell of FIG. 4.

(Configuration)

According to one aspect of the present invention for achieving the above object, a single port RAM comprises: first and second word lines extending in a row direction along the memory cell; First and second bit lines extending in a column direction along the memory cells to intersect the first and second word lines; Latch means; Switching means for selectively coupling said latch means and said first and second bit lines in accordance with a voltage level of said first and second word lines, wherein said first and second bit lines comprise: first and second bit lines; It is formed in the lower layer of the second word lines.

In this embodiment, the memory cell additionally includes at least one contact for supplying a substrate bias voltage to the semiconductor substrate.

(Action)

By such an arrangement, by enabling the wiring arrangement on the upper layer of the memory cell, the signal delay caused by the area of the layout and the length of the wiring can be reduced.

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 4 to 6 according to an embodiment of the present invention.

Referring to FIG. 4, each bit cell of the novel single port RAM of the present invention is a latch circuit, and the first and second word lines W / L1 and W / L1b extending along the direction of a row, and the direction of a column. First and second bit lines B / L1 and B / L1b and the first and second word lines arranged to intersect the first and second word lines W / L1 and W / L1b. First and second transfer transistors N1 connecting the latch circuits to the first and second bit lines B / L1 and B / L1b according to voltage levels of the signals W / L1 and W / L1b. , N2). The first and second bit lines B / L1 and B / L1b are formed on lower layers of the first and second word lines W / L1 and W / L1b. Thus, by enabling the arrangement of the wiring of signals unrelated to the operation of the bit cell on the upper layer of the bit cell, it is possible to reduce the waste of layout area and the signal delay according to the length of the wiring. In addition, the bit cell additionally includes contacts C3 and C4 for supplying a voltage to the semiconductor substrate, thereby further reducing the layout area of the bit cell.

Referring to 4, the bit cell of the single port RAM according to the present invention is a latch circuit, the first and second word lines (W / L1, W / L1b) extending along the direction of the row, the first and second The first and second bit lines B / L1 and B / L1b extending along the column direction to intersect the word lines W / L1 and W / L1b and the first and second in write and read operations. First and second transfers selectively connecting the first and second bit lines B / L1 and B / L1b and the latch circuit according to voltage levels of word lines W / L1 and W / L1b. Transistors N1 and N2.

The latch circuit includes inverters including MOS transistors PM1, PM2, NM1, NM2. The PMOS transistor PM1 has a current path formed between the power supply voltage VCC and the node n1 and a gate connected to the node n2. The PMOS transistor PM2 has a current path formed between the power supply voltage VCC and the node n2 and a gate connected to the node n1. The NMOS transistor NM1 has a current path formed between the node n1 and the ground voltage VSS and a gate connected to the node n1.

The NMOS transistor NM2 has a current path formed between the node n2 and the ground voltage VSS and a gate connected to the node n1. The first transfer transistor N1 has a current path formed between the first bit line B / L1 and the node n1 and a gate connected to the first word line W / L1. The second transfer transistor N2 has a current path formed between the second bit line B / L1b and the node n2 and a gate connected to the second word line W / L1b.

Hereinafter, a layout structure of a bit cell according to the present invention will be described with reference to FIGS. 4 to 6.

4 through 6, the bit cell of FIG. 5A has an active region formed on a semiconductor substrate (not shown), and the MOS transistors PM1, PM2, NM1, NM2, Regions of N1 and N2 are formed. The first and second bit lines B / L1 and B / L1b extending in the column direction are arranged on the regions of the MOS transistors PM1, PM2, NM1, NM2, N1, and N2. The first and second word lines W / L1 and W / L1b extending in the row direction are arranged on the upper layers of the first and second bit lines B / L1 and B / L1b.

5B is a simplified diagram of the layout of the bit cell. Referring to FIG. 5B, the first and second bit lines B / L1 and B / L1b regions 104 and 105 may be formed on the upper layer of the active region 101 and the power supply voltage VCC region 102. ) And the ground voltage VSS region 103 are arranged in parallel with the power supply voltage and the ground voltage regions 102 and 103 in the column direction. The regions 106 and 107 of the first and second word lines W / L1 and W / L1b are formed on the upper layer of the first and second bit line regions 104 and 105. It is arranged along the direction of the row to intersect the two bit line regions 104, 105. The contact C1 on the ground voltage region 103 is electrically connected between the first bit line B / L1 of FIG. 4 and the first transfer transistor N1. The contact C2 on the ground voltage region 103 is electrically connected between the second bit line B / L1b and the second transfer transistor N2. Contacts C3 and C4 are electrically connected between the active region 101 and the outside to supply a substrate bias voltage to the active region 101 and the semiconductor substrate.

Referring to FIG. 6, the first and second word line regions 106 and 107 are arranged in an upper layer of the first and second bit line regions 104 and 105, so that the upper layer of the bit cell is located in the upper layer. The wirings metal4 and metal5 of any signal independent of the operation of the bit cell may be arranged. For example, when the wirings metal4 and metal5 for routing signals for an operation other than the write or read operation of the bit cell, that is, the upper layer of the bit cell, are arranged, data in the bit cell is arranged. When is written or data stored in the bit cell is read, the first and second word lines W / L1 and W / L1b are interfered with a signal flowing through the wires. However, the influence on the first and second word lines W / L1 and W / L1b of the wirings metal4 and metal5 can be predicted, and the influence of the signals on the data is insignificant.

The bit cell of the single port RAM according to the present invention includes first and second bit lines B / L1 and B / L1b formed on lower layers of the first and second word lines W / L1 and W / L1b. It includes. Accordingly, the lengths of the wirings metal4 and metal5 may be reduced by arranging the wirings metal4 and metal5 of signals unrelated to the operation of the bit cell on the upper layer of the bit cell. If the length of the wiring is reduced, the layout area of the bit cell can be reduced and the delay time according to the length of the wirings metal4 and metal5 can be reduced. In addition, the bit cell further includes contacts C3 and C4 capable of supplying a voltage to the semiconductor substrate and the active region, thereby eliminating the need to arrange spacer cells, thereby further reducing the layout area. Can be.

As described above, by enabling the wiring arrangement on the upper layer of the memory cell, it is possible to reduce the signal delay according to the layout area and the wiring length.

Claims (2)

A semiconductor memory device having at least one memory cell for storing data; First and second word lines extending in a row direction along the memory cell; First and second bit lines extending in a column direction along the memory cells to intersect the first and second word lines; Latch means; And switching means for selectively connecting the latch means and the first and second bit lines in accordance with the voltage level of the first and second word lines. The first and second bit lines, And a lower layer of the first and second word lines. The method of claim 1, And the memory cell further comprises at least one contact for supplying a substrate bias voltage to the semiconductor substrate.