KR20000013593U - ATM Cell Boundary Detection Device in ATM Cell Transmission Using First-In First-Out Buffer - Google Patents

Abstract

The present invention relates to an Asynchronous Transfer Mode (ATM) transmission / reception apparatus, and particularly, when a first-in-first-out buffer transmits / receives by cell, due to a pointer error that may occur during I / O control of the first-in first-out buffer. A device for detecting a mistake in ATM cell boundary identification. The present invention provides at least one first-in first-out (FIFO) buffer for simultaneously storing ATM cell data bits and an identification bit indicating an intercell boundary; And an ATM processor that determines whether the bit string of the cell of the FIFO buffer is normal by using the identification bit and controls the input / output of the FIFO buffer. The ATM processor identifies a cell boundary by using an identification bit allocated to each byte of cell data, and detects a cell error due to a pointer error that may occur during input / output control of a buffer. In addition, when the cell error is detected, a cell transmission error may be prevented by retransmission after the reception FIFO buffer is reset.

Description

ATM cell boundary detection apparatus on ATM cell transmission using first-in first-out buffer

The present invention relates to an Asynchronous Transfer Mode (ATM) transmission / reception apparatus, and particularly, when a first-in-first-out buffer transmits / receives by cell, due to a pointer error that may occur during I / O control of the first-in first-out buffer. A device for detecting a mistake in ATM cell boundary identification.

The ATM communication method combines real-time signals with a wide bandwidth distribution from narrowband service (telephone, facsimile) to wideband service (video conferencing, high-speed data / video transmission) and aggregated data signals that can aggregate clustered data signals. It is proposed to implement the BISDN. In BISDN, service information is delivered by a continuous flow of packets of a certain size. The packets of fixed size are called ATM cells. Thus, service information is first truncated to a size and then mapped to an ATM cell, followed by asynchronous time division multiplexing (ATDM) with other ATM cells, thereby forming a BISDN internal transmission signal.

Here, ATDM is a kind of statistical multiplexing method for time-division multiplexing ATM cells of multiple channels coming in asynchronously from each other. ATDM is a multiplexing scheme in which incoming low-speed service signals are first stored in each buffer, and then taken out one by one according to the priority processing policy of the multiplexing system and inserted into the multiplexing slot. The simplest example of the priority processing policy is FIFO; First-In First-Out). The service signals input at this time are ATM cells in the case of an ATM communication system. The ATM cell length is a total of 53 bytes consisting of a 5-byte header and a 48-byte payload.

ATM cell transmission using a first-in first-out (FIFO) buffer in a typical ATM transmission equipment is shown in FIG.

In the ATM transmitter 100, the ATM cells multiplexed by the ATM processor 110 that processes the physical layer ATM cells are temporarily stored in the FIFO buffer 120 for transmission in byte units and then output in byte units. The ATM receiver 150 temporarily stores an ATM cell received in bytes by the reception FIFO buffer 160, outputs the bytes in bytes, and provides the same to the ATM processor 170. The ATM processor detects a cell error by extracting a header of an ATM cell and checking a Cyclic Redundancy Check CRC value.

In practice, the FIFO buffer size uses 9 bits, of which only 8 bits are used for data, and the last ninth bit is not used or its purpose is different depending on the user's intention. As a method of realizing the FIFO buffer program, there is a method of identifying the starting point and the ending point of the buffer in a ring shape (circulating buffer), or connecting the elements of the buffer with a pointer.

Therefore, in the prior art as shown in FIG. 1, the cell boundary due to a pointer error that may occur during input / output control in the FIFO buffer may be shifted, and there is a problem in that the error cannot be detected.

Accordingly, an object of the present invention is to provide an apparatus for detecting the boundary of a received cell using the identification bit by adding the identification bit indicating the cell boundary to the byte unit data of the ATM cell and storing the data in the FIFO buffer. There is.

Accordingly, the cell transmission error can be prevented by detecting an error in which the cell boundary is shifted during I / O control of the FIFO buffer and retransmitting the corresponding cell when an error occurs.

An ATM cell boundary detection apparatus in ATM cell transmission using a first-in, first-out buffer of the present invention for achieving the above object,

One or more first-in, first-out (FIFO) buffers that simultaneously store ATM cell data bits and identification bits indicating intercell boundaries; And an ATM processor that determines whether the bit string of the cell of the FIFO buffer is normal by using the identification bit and controls the input / output of the FIFO buffer.

1 is a diagram illustrating ATM cell transmission using a first-in, first-out buffer in a general ATM transmission equipment.

2 is a block diagram of an ATM cell boundary detection apparatus for ATM cell transmission using a first-in, first-out buffer according to the present invention;

3 is a structure diagram of ATM cell data bits and identification bits of the first-in, first-out buffer of FIG. 2;

<Explanation of symbols for the main parts of the drawings>

200: ATM transmitter 210: transmit ATM processor 220: transmit FIFO buffer

250: ATM receiver 260: Receive FIFO buffer 270: Receive ATM processor

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

2 is a block diagram of an ATM cell boundary detection apparatus for ATM cell transmission using a first-in, first-out buffer according to the present invention.

The ATM transmitter 200 receives an ATM processor 210 for multiplexing a physical layer ATM cell and an ATM cell processed by the ATM processor 210 in byte units D0 to D7 and simultaneously identifies cell boundaries. It consists of a transmission FIFO buffer 220 for receiving and storing the identification bit (D8). The ATM processor 210 further includes an input / output control function of the normal FIFO buffer 220 by using an identification bit in addition to the existing processor function.

The ATM receiver 250 includes a reception FIFO buffer 260 for storing the received byte cell ATM cell data and identification bits, and an ATM processor 270 for demultiplexing and processing the ATM cells of the FIFO buffer 260. do. The ATM processor 270 may further include an input / output control function of the normal FIFO buffer 260 using an identification bit in addition to the existing processor function.

Referring to the operation at the transmitting side 200, the ATM processor 210 stores the ATM cell data in bytes D0 to D7, and at the same time, identifies an identification bit D8 for separating the boundary of the ATM cell composed of 53 bytes. 9 bit FIFO buffer 220 for transmission. That is, the ATM processor allocates an identification bit of '1' value to the first byte of the ATM cell and an identification bit of '0' value to the remaining 52 bytes.

That is, as shown in Figure 3, the FIFO buffer 220 stores in the memory in the order in which the transmission, the first byte (BYTE1) content and identification bit (9th bit) of the cell to the signal level of '1' Each of the remaining 52 bytes (BYTE2 to BYTE53) of the cell and the identification bit of each byte are stored as the signal level of '0'. This operation is performed each time a new ATM cell is entered.

If the transmit FIFO buffer 220 is operated by normal input / output control, the bit string of the cell will not be shifted. When the cell request from the receiving side 250 is received in this normal state, the ATM processor 210 provides the write clock and the control signal to the transmitting FIFO buffer 220, and the FIFO buffer 220 receives the receiving side 250. Start the transfer with.

Referring to the operation on the receiving side 250, the receiving FIFO buffer 260 temporarily stores the received cell data in the memory, and outputs it by the cell request of the ATM processor 270. Here, the ATM processor 270 examines the ninth bit (identification bit) while the first byte data is read. If the identification bit is '1', it is determined that the cell boundary is not shifted, and data is read from the reception FIFO 260 by the read clock READ CLK. This means that at least one cell CELL has been transmitted without error.

If the identification bit is '0', it is determined that the cell boundary is out of alignment, and the reception FIFO buffer 260 is reset to transmit a cell request for receiving the cell again to the transmitter.

This operation can be performed cell-by-cell to detect cell boundary deviations that may occur due to pointer errors in the FIFO buffer.

As described above, the present invention allocates an identification bit for each byte of cell data and stores it in the FIFO buffer, thereby identifying each cell boundary and forcing a cell due to a pointer error that may occur during buffer input / output control. Error can be detected.

In addition, when the cell error is detected, a cell transmission error may be prevented by retransmission after the reception FIFO buffer is reset.

Claims (3)

One or more first-in, first-out (FIFO) buffers that simultaneously store ATM cell data bits and identification bits indicating intercell boundaries; And An ATM processor for determining whether a bit string of a cell of the FIFO buffer is normal by using the identification bit, and controlling an input / output of the FIFO buffer. Cell boundary detection device. 2. The first-in, first-out buffer of claim 1, wherein in the case of ATM cell transmission, the ATM processor allocates a first level with the identification bit of the first byte of the ATM cell and a second level with the identification bit of the remaining bytes. An ATM cell boundary detection apparatus for ATM cell transmission using a DMA. 3. The method of claim 2, wherein in the case of ATM cell reception, the ATM processor examines the identification bit of the first byte of the ATM cell, reads and controls the FIFO buffer at the first level, and if not at the first level, the FIFO buffer. An ATM cell boundary detection device in ATM cell transmission using a first-in, first-out buffer, after resetting, requesting retransmission of the cell.