KR20000013502A - Hybrid semiconductor device having a memory and a logic and a hold time control method - Google Patents

Abstract

PURPOSE: A hybrid semiconductor device composed of a memory and a logic is provided to reduce transition current of data inputted to the memory while securing enough margin of data hold time. CONSTITUTION: The hybrid semiconductor device comprising a logic, a memory and data bus for electrically connecting them which operates in synchronism with an external clock signal supplied from the exterior, further comprises: a rising delay circuit for delaying a rising edge of the external clock signal; a falling delay circuit for delaying a falling edge of the external clock signal; a first switching circuit for receiving data outputted from the logic and outputting the data in response to an output of the falling delay circuit; a first latch circuit for storing the data output from the first switching circuit; a second switching circuit for receiving data outputted from the first latch circuit and outputting the data in response to an output of the rising delay edge; and a second latch circuit for storing the data output from the second switching circuit, a data output from the second latch circuit being transmitted through the data bus to the memory.

Description

Memory Logic Composite Semiconductor Device and Hold Time Control Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a memory logic compound semiconductor device in which memory and logic are combined in one chip and a hold time control method thereof.

Recently, the trend of integrating DRAM and logic into one chip is spreading. Integrating DRAM and logic into a single chip can significantly increase the number of data buses because the interface between DRAM and logic is possible with Complementary Metal Oxide Semiconductors (CMOS). However, as the number of data buses increases, the number of input buffers in the DRAM also increases by the number of data buses. Delay means is added.

1 illustrates a conventional memory logic complex semiconductor device. Referring to FIG. 1, the conventional memory logic complex semiconductor device 101 includes a logic 111, a plurality of logic flip-flops (LFFi; i = 1, 2,...), A memory 121, and a plurality of memory flip-flops. (MFFi; i = 1,2, ...), multiple delay means (DELAYi; i = 1,2, ...), multiple data buses (DBi; i = 1,2, ...) and internal clock generator 131 is provided. The logic 111 transmits data to the memory 121 through a plurality of logic flip-flops LFFi and a plurality of data buses DBi. The memory 121 inputs the data through a plurality of delay means DELAYi and a plurality of memory flip-flops MFFi. When the external clock signal ECLK is applied to the internal clock generator 131, the internal clock generator 131 converts the voltage level to the CMOS level, and also internal clock signal PCLK delayed by a predetermined time from the external clock signal ECLK. Is generated and applied to the memory flip-flops MFFi. The plurality of delay means DELAYi delays data applied to the memory 121 through the data buses DBi for a predetermined time. The reason why the plurality of delay means DELAYi is used is because the internal clock signal PCLK used for latching in the memory 121 is inevitably delayed compared to the external clock signal ECLK. This is because the data should be delayed as much as.

As described above, according to the conventional memory logic compound semiconductor device 101, a plurality of delay means DELAYi are used to delay data input to the memory 121. Such delay means DELAYi are composed of resistor (s) and capacitor (s) in order to be insensitive to process changes, voltage changes or temperature changes, which causes the data to be logic. The amount of current consumed when transitioning from low to logic high or from logic high to logic low, i.e., the amount of transition current, increases. When the number of data buses DBi is small, the ratio of the amount of transition current to the current consumed in the entire memory logic composite semiconductor device 101 is relatively small, but as the number of data buses DBi increases, The amount of transition current becomes insignificantly large.

Accordingly, an aspect of the present invention is to provide a memory logic complex semiconductor device which reduces a transition current of data input into a memory.

Another object of the present invention is to provide a hold time control method of a memory logic complex semiconductor device for sufficiently securing a hold time margin of data while reducing a transition current of data input to the memory.

1 is a schematic circuit diagram of a conventional memory logic complex semiconductor device.

2 is a schematic circuit diagram of a memory logic complex semiconductor device according to a preferred embodiment of the present invention.

3 is a circuit diagram of the delay circuit shown in FIG.

4 is a circuit diagram of the logic flip-flop shown in FIG.

5 is a timing diagram of the signals shown in FIG. 2;

The present invention to achieve the above technical problem,

A memory logic compound semiconductor device having a logic and a memory and a data bus electrically connecting the logic and the memory and operating in synchronization with an external clock signal applied from an external device, comprising: a clock delay circuit configured to delay the external clock signal by a predetermined time; And a flip-flop for inputting data output from the logic and transferring the data to the data bus in response to a clock signal generated from the clock delay circuit.

The present invention also to achieve the above technical problem,

A memory logic compound semiconductor device having a logic and a memory and a data bus electrically connecting the logic and the memory and operating in synchronization with an external clock signal applied from the outside, the rising delay delaying a rising edge of the external clock signal. A circuit, a falling delay circuit for delaying a falling edge of the external clock signal, switching means for inputting data output from the logic and outputting the data in response to an output of the falling delay circuit, data output through the switching means And other switching means for inputting data output from the latch and for outputting the input data in response to the output of the rise delay circuit, and another latch for storing data output from the other switching means. And the second latch portion Data output provides a logic composite semiconductor memory device characterized in that the transfer to the memory via the data bus.

Preferably, the rising delay circuit has a delay for delaying the external clock signal by a predetermined time, and a logic gate for ANDing the output of the delay and the external clock signal, the logic gate being the output of the delay. And a NAND gate for inputting the external clock signal, and an inverter for inverting the output of the NAND gate. Further, the falling delay circuit includes another delayer for delaying the external clock signal by a predetermined time, and a logic gate for ORing the output of the other delayer and the external clock signal, the logic gate being an output of the delayer. And a Noah gate for inputting the external clock signal, and an inverter for inverting the output of the Noah gate.

Preferably, the switching means inputs an inverted signal of the output of the falling delay circuit and the output of the falling delay circuit to control electrodes and is turned on when the output of the falling delay circuit is logic low to output the data. And another switching means inputs an inverted signal of the output of the rise delay circuit and the output of the rise delay circuit to control electrodes and is turned on when the output of the rise delay circuit is logic high to receive the input data. It is a transmission gate to output.

According to the present invention, the current consumption of the memory logic composite semiconductor device is reduced.

The present invention to achieve the above other technical problem,

A hold time control method of a memory logic compound semiconductor device having a logic and a memory and a data bus electrically connecting the logic and the memory and operating in synchronization with an external clock signal applied from an external device, the method comprising: delaying the external clock signal; And delaying data output from the logic by using the delayed external clock signal, wherein the delayed data is transferred to the memory through the data bus to sufficiently hold time margin of data input to the memory. Provided is a hold time control method of a memory logic composite semiconductor device, which is secured.

According to the present invention, the hold time margin of the signal input to the memory of the memory logic complex semiconductor device is sufficiently secured.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic circuit diagram of a memory logic complex semiconductor device according to a preferred embodiment of the present invention. Referring to FIG. 2, the memory logic complex semiconductor device 201 according to an exemplary embodiment of the present invention may include a logic 211, logic flip-flops (LFFi; i = 1, 2,...), A memory 221, a memory. Flip-flops MFFi; i = 1, 2,..., Data buses DBi; i = 1.2..., An internal clock generator 231, and a delay circuit 241. The logic 211 transmits data Di to the memory 221 through a plurality of logic flip-flops LFFi and a plurality of data buses DBi. The memory 221 inputs the data Di through a plurality of memory flip-flops MFFi. The memory flip-flops MFFi operate in synchronization with the internal clock signal PCLK, respectively. The internal clock signal PCLK is generated from the internal clock generator 231. The internal clock generator 231 receives the external clock signal ECLK and converts the voltage level of the external clock signal ECLK to a CMOS level to generate the internal clock signal PCLK.

When the external clock signal ECLK is applied to the delay circuit 241, the delay circuit 241 generates the signals DLCLK, DLCLKB, DHCLK, and DHCLKB to control the plurality of logic flip-flops LFFi. The logic flip-flops LFFi input data Di output from the logic 211, respectively, and output data Di controlled and controlled by the signals DLCLK, DLCLKB, DHCLK, and DHCLKB.

As described above, the internal clock signal PCLK is transmitted by delaying the data Di output from the logic 211 to the memory 221 through the delay circuit 241 delaying the external clock signal ECLK by a predetermined time. By synchronizing with the data Di, a hold time margin of the data Di can be sufficiently secured. In addition, the power consumption of the memory logic compound semiconductor device is reduced because the transition current generated when the data Di transitions from logic low to logic high or from logic high to logic low is very small.

3 is a circuit diagram of the delay circuit 241 shown in FIG. Referring to FIG. 3, the delay circuit 241 includes a rising delay circuit 301 and a falling delay circuit 303. The rise delay circuit 301 includes a delay 311, a NAND gate 321, and an inverter 323, and the fall delay circuit includes a delay 312, a noah gate 331, and an inverter 333. .

The delay unit 311 delays the external clock signal ECLK by a predetermined time and applies it to the NAND gate 321. The NAND gate 321 negates AND of the output of the delay unit 311 and the external clock signal ECLK. That is, the NAND gate 321 outputs a logic high when any one of the output of the delayer 311 and the external clock signal ECLK is logic low, and the output of the delayer 311 and the external clock signal ECLK are If all are logic high, output logic low. Therefore, the NAND gate 321 generates a signal DHCLKB having a low pulse. The inverter 323 inverts the signal DHCLKB to generate a signal DHCLK having a high pulse. The rising edge of the external clock signal ECLK is delayed by the rising delay circuit 301.

The delay unit 312 delays the external clock signal ECLK by a predetermined time and applies it to the NOR gate 331. The NOR gate 331 negates the OR of the output of the delay unit 312 and the external clock signal ECLK. That is, the NOR gate 331 outputs a logic low when any one of the output of the delay unit 312 and the external clock signal ECLK is logic high, and the output of the delay unit 312 and the external clock signal ECLK are If all are logic low, output a logic high. Therefore, the NOR gate 331 generates a signal DLCLKB having a high pulse. The inverter 333 inverts the signal DLCLKB to generate a signal DLCLK having a low pulse. The falling edge of the external clock signal ECLK is delayed by the falling delay circuit 303.

FIG. 4 is a circuit diagram of the logic flip-flop LFF1 shown in FIG. 2. Referring to FIG. 4, the logic flip-flop LFF1 includes switching means 411 and 431 and latches 421 and 441. The switching means 411 comprises a transfer gate that receives data Di outputted from logic (211 in FIG. 2), receives the signal DLCLK at the gate of the PMOS transistor, and receives the signal DLCLKB at the gate of the NMOS transistor. do. Accordingly, the switching means 411 is turned on when the signal DLCLKB is logic high, and the signal DLCLK is logic low to output the data Di, and the signal DLCLKB is logic low, If the signal DLCLK is logic high, it is turned off and does not output the data Di. The latch 421 inverts and stores the data Di output from the switching means 411.

The switching means 431 inputs the data Di output from the latch 421, and constitutes a transfer gate that receives the signal DHCLKB at the gate of the PMOS transistor and the signal DHCLK at the gate of the NMOS transistor. Accordingly, the switching means 431 is turned on when the signal DHCLK is logic high and the signal DHCLKB is logic low to output the data Di, the signal DHCLK is logic low, and the signal DHCLKB is If it is a logic high, it is turned off and does not output the data Di. The latch 441 inverts and stores the data Di output from the switching means 431 and transfers the data Di to the data bus DB1 of FIG. 2.

FIG. 5 is a timing diagram of the signals shown in FIG. 2. As shown in FIG. 5, the data Di carried from the logic 211 of FIG. 2 to the data buses DBi of FIG. 2 is delayed by a predetermined time, so that the margin of the setup time tSS and the hold time tSH is delayed. This is secured enough.

The best embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, the signals DLCLK, DLCLKB, DHCLK, and DHCLKB are generated from the external clock signal ECLK and transmitted from the logic 211 to the memory 221 through the data buses DBi. By delaying the data Di, the power consumed by the memory logic compound semiconductor device 201 is reduced, and the hold time margin of data Di input to the memory 221 is sufficiently secured. ) Malfunction is prevented and noise of the data Di is reduced.

Claims (9)

A memory logic compound semiconductor device having a logic and a memory and a data bus electrically connecting the logic and a memory, and operating in synchronization with an external clock signal applied from the outside. A clock delay circuit for delaying the external clock signal by a predetermined time; And a flip-flop for inputting data output from the logic and transferring the data to the data bus in response to a clock signal generated from the clock delay circuit. A memory logic compound semiconductor device having a logic and a memory and a data bus electrically connecting the logic and a memory, and operating in synchronization with an external clock signal applied from the outside. A rising delay circuit for delaying a rising edge of the external clock signal; A falling delay circuit for delaying a falling edge of the external clock signal; Switching means for inputting data output from said logic and outputting said data in response to an output of said falling delay circuit; A latch for storing data output through the switching means; Another switching means for inputting data output from the latch and outputting the input data in response to an output of the rise delay circuit; And Another latch for storing data output from said other switching means, And output the data output from the second latch to the memory via the data bus. 3. The circuit of claim 2 wherein the rise delay circuit A delayer for delaying the external clock signal by a predetermined time; And And a logic gate for ANDing the output of the delay and the external clock signal. 4. The logic gate of claim 3 wherein the logic gate is A NAND gate configured to input an output of the delay unit and the external clock signal; And And an inverter for inverting the output of the NAND gate. 3. The circuit of claim 2, wherein the falling delay circuit Another delayer for delaying the external clock signal by a predetermined time; And And a logic gate for ORing the output of the other delayer and the external clock signal. 6. The logic gate of claim 5 wherein the logic gate is A noah gate for inputting the output of the delay and the external clock signal; And And an inverter for inverting the output of the NOR gate. 3. The switching circuit according to claim 2, wherein the switching means inputs an inverted signal of the output of the falling delay circuit and the output of the falling delay circuit to control electrodes and is turned on when the output of the falling delay circuit is logic low to output the data. A memory logic composite semiconductor device, characterized in that the transfer gate. The switching device of claim 2, wherein the other switching unit inputs an inverted signal of the output of the rising delay circuit and the output of the rising delay circuit to control electrodes and is turned on when the output of the rising delay circuit is logic high. A memory logic compound semiconductor device, characterized in that the transfer gate outputs data. A method of securing a hold time margin of a memory logic compound semiconductor device having a logic and a memory and a data bus electrically connecting the logic and the memory and operating in synchronization with an external clock signal applied from an external device, the method comprising: Delaying the external clock signal; Delaying a signal output from the logic by using the delayed external clock signal, And a hold time margin of a signal input to the memory by sufficiently transmitting the delayed signal to the memory through the data bus.