KR20000012943A - Data output buffer in synchronous semiconductor memory device - Google Patents

Abstract

PURPOSE: A data output buffer of a synchronous semiconductor memory device is provided to output normal data even in a high frequency operation. CONSTITUTION: The synchronous semiconductor memory device comprises: a cell array for storing data; a data output buffer element for outputting data read from the cell array to the exterior in response to a data output buffer control signal; and a data output buffer control circuit for outputting the data output buffer control signal in response to a first and a second control signals and a latency signal.

Description

DATA OUTPUT BUFFER OF SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous memory device, and more particularly to a data output buffer.

In general, a synchronous semiconductor memory device has a latency that determines at which clock the initial data is input / output after a data write and read command. The number of latch circuits of the data output buffer provided in the synchronous memory device is determined according to the latency. 1 is a circuit diagram of a synchronous semiconductor memory device having the data output buffer when the latency is '3'. Referring to FIG. 1, a conventional synchronous semiconductor memory device includes a memory structure array 10, a data output buffer 20, and a data output buffer control circuit 30. The data output buffer 20 latches data output from the memory cell array 10 under the control of the data output buffer control signal? TRST supplied from the data output buffer control circuit 30. The first latch circuit 21 of the data output buffer 20 latches data output from the memory cell array 10 under the control of a first latency signal L1.

The second latch circuit portion 22 latches the data supplied from the first latch circuit portion 21 under the control of the second latency signal L2. The third latch circuit section 23 latches the data supplied from the second latch circuit section 22 under the control of a third latency signal L3 and the data output buffer control signal? TRST. The inverter 24 inverts the data supplied from the third latch circuit unit 23 and supplies the inverted data to the output terminal. The data output buffer control circuit 30 outputs the data output buffer control signal? TRST by combining the applied signal? DQM and the signal LAT.

Referring to FIG. 2, the first latch circuit 21b of the first latch circuit unit 21 of FIG. 1 may have the memory cell array 10 when the first latency signal L1 is at a high level. The first data from is latched. The second latch circuit 22b of the second latch circuit portion 22 latches the first data from the first latch circuit 21 when the second latency signal L2 is at a high level. At this time, the second data from the memory cell array 10 is latched in the first latch circuit 21b. The third latch circuit 23b of the third latch circuit section 23 is separated from the second latch circuit section 22 when the third latency signal L3 and the data output buffer signal? TRST are at a high level. The first data is latched. In this case, the second latch circuit 22b latches the second data from the first latch circuit portion 21, and the first latch circuit 21b latches the third data from the memory cell array 10. Is latched.

3A and 3B, the data output buffer control circuit 30 outputs the data output buffer control signal øTRST combining the signals øDQM and LAT to be applied to the third latch circuit unit 23. To supply. The data output buffer control signal? TRST maintains a constant margin W1, W2; ①, ②, ③, and ④ between the third latency signals L3 and the third latch circuit 23. Is supplied. 3A illustrates a case in which the signal LAT is supplied at a high level to block the remaining data after the second data is output among the data output from the third data latch circuit unit 23. However, when the clock signal input to the synchronous semiconductor memory device has a high frequency and the signal LAT is changed due to a change in power supply voltage or temperature, the signal LAT is supplied and then the signal is supplied. Due to the change in LAT, the margins ①, ②, ③, and ④ of the data output buffer control signal? TRST are changed so that unwanted data is output from the third latch circuit section 23.

3B illustrates a case in which the signals? DQM and LAT are varied in order to output the second and third data among the data output from the third data latch circuit unit 23. In this case, as in FIG. 3A, when the clock signal input to the synchronous semiconductor memory device has a high frequency and the signals? DQM and LAT vary according to a change in power supply voltage or temperature, the signals? DQM, After the LAT is supplied, the third latch circuit unit 23 generates margins W3, W4; ⑤, ⑥, ⑦, of the data output buffer control signal øTRST due to the change of the signals øDQM, LAT. (8) is changed so that unwanted data is outputted from the third latch circuit section 23 or invalid data is outputted. As described above, in the synchronous semiconductor memory device according to the related art, when the signals øDQM and LAT change in high frequency operation, normal data may not be output or wrong data due to a change in the margin of the signals. A malfunction such as is output.

Accordingly, an object of the present invention is to provide a synchronous semiconductor memory device that outputs normal data even in high frequency operation.

1 is a circuit diagram of a synchronous semiconductor memory device according to the prior art;

FIG. 2 is an operation timing diagram of the synchronous semiconductor memory device of FIG. 1; FIG.

3A and 3B are operation timing diagrams of the data output buffer control circuit of Fig. 1;

4 is a detailed circuit diagram of a synchronous semiconductor memory device according to the present invention; And

5A and 5B are operation timing diagrams of the data output buffer control circuit of FIG. 4.

* Explanation of symbols on the main parts of the drawings

10, 100: memory cell array 20, 200: data output buffer

30, 300: data output buffer control circuit

(Configuration)

According to one aspect of the present invention for achieving the above object, a synchronous semiconductor memory device comprises an array of memory cells for storing data; Data output buffer means for outputting data from the memory cell array to outside in response to a data output buffer control signal; And a data output buffer control circuit for outputting the data output buffer control signal in response to the first and second control signals informing the output of the data and the latency signal.

In this embodiment, a data output buffer control circuit includes an inverting circuit for inverting the first and second control signals, and the first and second control signals inverted by the inversion circuit in response to the latency signal. A transfer circuit for transmitting, a first latch circuit for latching the first control signal from the transfer circuit, a second latch circuit for latching the second control signal from the transfer circuit, and the first and second And a logic circuit for combining the first and second control signals from a latch circuit to output the data output buffer control signal.

(Action)

By such a device, the data output buffer control signal for controlling the data output is synchronized with the latency signal, whereby normal data can be read during a read operation at a high frequency.

(Example)

Hereinafter will be described in detail based on the reference drawings 4 to 5b according to an embodiment of the present invention.

Referring to FIG. 4, the novel synchronous memory device of the present invention includes a memory cell array 100, a data output buffer 200, and a data output buffer control circuit 300. The data output buffer 200 latches data supplied from the memory cell array 100 in response to a data output buffer control signal? TRST supplied from the data output buffer control circuit 300. The data output buffer control circuit 300 outputs the data output buffer control signal? TRST, which is a combination of the signals? DQM and LAT input in response to a third latency signal L3, to the data output buffer circuit 200. To supply.

Referring to FIG. 4, a synchronous memory device according to the present invention includes a memory cell array 100, a data output buffer 200, and a data output buffer control circuit 300. The memory cell array 100 includes a plurality of memory cells that store data. The data output buffer 200 includes first, second, and third latch circuit parts 210, 220, and 230. The first latch circuit unit 210 includes a first transfer circuit 211 and a first latch circuit 212. The first transfer circuit 211 includes an inverter I1 and a transfer gate G1. The inverter I1 inverts the first latency signal L1. The transfer gate G1 is a current path formed between the memory cell array 100 and the first latch circuit 212, and is inverted by the first latency signal L1 and the inverter I1. 1 latency signal Gates controlled by the memory cell, and transfer data supplied from the memory cell array 100 to the first latch circuit 212. The first latch circuit 212 includes inverters I3 and I4. The inverters I3 and I4 are connected such that input / output terminals cross each other between the first transfer circuit 211 and the second latch circuit 220, and through the first transfer circuit 211. Latch the supplied data.

The second latch circuit unit 220 includes a second transfer circuit 221 and a second latch circuit 222. The second transfer circuit 221 includes an inverter I4 and a transfer gate G2. The inverter I4 inverts the second latency signal L2. The transfer gate G2 is inverted by the current path formed between the first latch circuit 210 and the second latch circuit 222 and the second latency signal L2 and the inverter I4. Second latency signal Gates controlled by the controller, and transfer the data supplied from the first latch circuit unit 210 to the second latch circuit 222. The second latch circuit 222 includes inverters I5 and I6. The inverters I5 and I6 are connected such that input / output terminals cross each other between the second transfer circuit 221 and the third latch circuit unit 230, and through the second transfer circuit 221. Latch the supplied data.

The third latch circuit unit 230 includes a third transfer circuit 231 and a third latch circuit 232. The third transfer circuit 231 includes a NAND gate N1, an inverter I7, and a transfer gate G3. The NAND gate N1 combines a third latency signal L3 and the data output buffer control signal? TRST. The inverter I7 inverts the combined signal S output from the NAND gate N1. The transfer gate G3 is a current path formed between the second latch circuit 220 and the third latch circuit 232 and the combination inverted by the combination signal S and the inverter I4. It has a gate controlled by the signal S, and supplies the data from the second latch circuit unit 220 to the third latch circuit 232. The second latch circuit 222 includes inverters I8 and I9. The inverters I8 and I9 are connected such that input / output terminals cross each other between the third transfer circuit 231 and the third latch circuit unit 230 and are supplied through the third transfer gate. Latch the data.

The data output buffer control circuit 300 includes an inversion circuit 310, a transfer circuit 320, first and second latch circuits 330 and 340, and a logic circuit 350. The inversion circuit 310 includes inverters 311 and 312. The inverter 311 is connected between the signal? DQM input terminal and the transfer circuit 320, and inverts the signal? DQM. The inverter 312 is connected between the signal LAT input terminal and the transfer circuit 320 and inverts the signal LAT. The transfer circuit 231 includes an inverter 321 and transfer gates 322 and 323. The inverter 321 inverts the third latency signal L3. The transfer gate 322 is inverted by the current path and the third latency signal L3 and the inverter 321 formed between the inversion circuit 310 and the first latch circuit 330. Third latency signal Gates controlled by the signal, and transfer the signal? DQM to the first latch circuit 330.

The transfer gate 323 is inverted by the current path and the third latency signal L3 and the inverter 321 formed between the inversion circuit 310 and the second latch circuit 340. Third latency signal Gates controlled by the signal, and transfer the signal LAT to the first latch circuit 330. The first latch circuit 330 is the signal transmitted from the transfer circuit 320 Latch. The second latch circuit 340 is the signal transmitted from the transfer circuit 320 Latch. The logic circuit 350 includes a NAND gate 351 and an inverter 352. The logic circuit 350 is connected between the first and second latch circuits 330 and 340 and the third latch circuit portion 230 of the data output buffer 200 and the first and second latch circuits 230. The signals from latch circuits 330, 340 To output the data output buffer control signal? TRST.

Hereinafter, the operation of the synchronous semiconductor memory device of the present invention will be described with reference to FIGS. 5A and 5B.

5A and 5B, the data output buffer control circuit 300 of the synchronous semiconductor memory device of the present invention is output from the data output buffer 200 by the control of the third latency signal L3. The data output buffer control signal? TRST, which combines the signals? DQM and LAT, is supplied to the data output buffer 200 to control data. The transfer circuit 320 of the data output buffer control circuit 300 may output the signals? DQM and LAT when the third latency signal L3 is at a low level as shown in FIGS. 5A and 5B. Supply to the first and second latch circuits (330, 340). The logic circuit 350 outputs the data output buffer control signal? TRST combining the signals? DQM and LAT from the first and second latch circuits 330 and 340. The data output buffer 200 is controlled from the memory cell array 100 under the control of the first, second and third latency signals L1, L2, L3 and the data output buffer control signal øTRST. Output data to the output terminal. The synchronous semiconductor memory device in this embodiment has a case where the latency is '3'.

FIG. 5A illustrates a case where the signal LAT is transitioned to a low level to block the remaining data after latching the second data among the data latched in the third latch circuit 230 of FIG. 4. When the signal LAT transitions to the low level, the data output buffer control signal? TRST does not immediately transition to the low level, but the third latency signal L3 transitions to the low level and then has a constant time delay. The low level is shifted in synchronization with the third latency signal L3. This eliminates the need to consider the margins W1 ', W2'; ① ', ③' of the data output buffer control signal øTRST even during high frequency operation in which the input interval of the third latency signal L3 is shortened. In addition, by considering only the margins W1 ', W2'; ② ', and ④' of the section in which the data is latched, output of erroneous data can be prevented.

Referring to FIG. 5B, the signals? DQM and LAT are varied to output first data and third data among the data latched in the third latch circuit 230 of FIG. 4. When the signals? DQM and LAT are variable, the data output buffer control signal? TRST is not immediately changed according to the signals? DQM and LAT that are varied, but is constant for the third latency signal L3. The delay is varied in synchronization with the third latency signal L3. This eliminates the need to consider margins W3 ', W4'; ⑤ ', ⑦', even during high frequency operation in which the input interval of the third latency signal L3 is shortened as shown in FIG. 5A, and the data is latched. By considering only the margins W3 ', W4'; ⑥ ', ⑧' of the sections, it is possible to prevent the output of wrong data. As described above, the data output buffer 200 of the synchronous memory device of the present invention is controlled by the data output buffer control signal? TRST, which is synchronized by the third latency signal L3. As a result, in the data reading operation in the high frequency operation, normal data can be read by preventing the malfunction caused by an external factor.

As described above, the data output buffer control signal for controlling the data output is synchronized with the latency signal, whereby normal data can be read during the read operation at a high frequency.

Claims (2)

In a synchronous semiconductor memory device: An array of memory cells that store data; Data output buffer means for outputting data from the memory cell array to outside in response to a data output buffer control signal; And a data output buffer control circuit for outputting the data output buffer control signal in response to a first and second control signals informing the output of the data and a latency signal. The method of claim 1, The data output buffer control circuit is An inversion circuit for inverting the first and second control signals; A transfer circuit for transferring the first and second control signals inverted by the inversion circuit in response to the latency signal; A first latch circuit for latching the first control signal from the transfer circuit; A second latch circuit for latching the second control signal from the transfer circuit; And a logic circuit for combining the first and second control signals from the first and second latch circuits to output the data output buffer control signal.