KR20000012006U - Charge pump circuit of semiconductor memory device - Google Patents

Abstract

The present invention relates to a charge pump circuit of a semiconductor memory device, and receives a first clock signal having a predetermined frequency through one end of the electrode and the other end of the first capacitor connected to the first node, and through one end of the electrode. A second capacitor having a second clock signal having a phase opposite to that of the one clock signal, and having the other end connected to the second node;

An NMOS transistor having a source connected to the first node, a drain and a gate commonly connected to an operating voltage terminal, a channel connected between the gate and the first node of the NMOS transistor, and a gate connected to the first node, and a substrate terminal A first PMOS transistor having a first PMOS transistor connected to a second node, a second PMOS transistor having a channel connected between the first node and the second node, a gate connected to the second node, and a substrate terminal connected to the third node; And a third PMOS transistor having a channel connected between the second node and the third node, a gate connected to the third node, and a substrate terminal connected to the third node or in a floating state. The voltage drop due to the circuit can be minimized, and can be applied to low voltage circuits, as well as reducing chip size and power consumption.

Description

Charge pump circuit of semiconductor memory device

The present invention relates to a circuit embedded in a semiconductor memory device, and more particularly to a charge pump circuit for outputting a boosted voltage of a potential higher than the operating voltage.

In general, a memory device such as a dynamic RAM uses a boosted voltage VPP higher than the operating voltage VDD to compensate for the loss caused by the threshold voltage of the cell transistor. The overall system block diagram of the pumping circuit for generating such boosted voltage is shown in FIG.

Referring to FIG. 1, the pumping circuit includes an oscillator 1, a driver 2 that receives a signal of the oscillator 1 and outputs a pumping clock of a predetermined level, and a boosting voltage VPP of a predetermined level in response to the pumping clock output from the driver 2. It consists of a charge pump circuit 3 to output.

A conventional charge pump circuit that substantially boosts the operating voltage to a predetermined level is shown in FIG. The configuration of FIG. 2 is briefly described as follows.

Four NMOS transistors 30, 40, 50, and 60 are connected in series between the operating voltage terminal VDD and the boosting node 61, and a drain and a gate are commonly connected to each transistor. The NMOS transistor 30 is for precharging the voltage level of the node 31 before the pumping operation. The NMOS transistors 40 and 50 output respective pumping voltages in response to the pumping clock, and the last NMOS transistor 60 It transmits the pumping voltage to the boosting node 61.

The capacitor 20 is connected between the node 31 to which the source of the NMOS transistor 30 and the drain of the NMOS transistor 40 are connected and the input node 10 which receives the pumping clock CLKX. The capacitor 21 is connected between the node 41, to which the source of the NMOS transistor 40 and the drain of the NMOS transistor 50 are connected, and the input node 11 receiving the pumping clock CLKY.

Looking at the operation according to the configuration of Figure 2 as follows.

Before the pumping operation, that is, when the pumping clock CLKX is 0 volts, the node 31 is precharged to VDD-Vtn by the NMOS transistor 30. When pumping clock CLKX increases from 0 volts to VDD, the potential at node 31 is increased by capacitor 20 to 2VDD-Vtn.

The pumping voltage 2VDD-Vtn at node 31 is dropped to 2VDD-2Vtn by the NMOS transistor 40 and output to node 41. At this time, when the pumping clock CLKY rises from 0 volts to VDD, the potential of the node 41 rises by VDD by the capacitor 21 to be 3VDD-2Vtn.

The pumping voltage 3VDD-2Vtn at the node 41 is dropped to 3VDD-3Vtn by the NMOS transistor 50 and outputted to the node 51. The pumping voltage 3VDD-3Vtn at the node 51 is dropped by the NMOS transistor 60 so that the voltage of 3VDD-4Vtn is output to the boosting node 61.

Therefore, the final boosted voltage can be expressed by the following equation.

VPP = {VDD + n (VCLK-Vt)}-Vt

Where n; The number of stages outputting the pumping voltage, VCLK-Vt; Voltage level at each stage during the pumping operation, -Vt; Voltage drop by means of transfer of pumping voltage

As can be seen from the above equation, in the conventional charge pump circuit, the voltage drop occurs by the threshold voltage of the MOS transistor in each stage, thereby lowering the voltage level of the boosted voltage VPP output. In addition, a voltage drop by the transmission means is also generated, resulting in a lowered voltage level. In addition, as the number of stages increases, the voltage is also affected by the body effect of the MOS transistor, so that the boost voltage is lowered, and thus there is a problem that it cannot be applied to a circuit using a low voltage.

Accordingly, an object of the present invention is to provide a charge pump circuit which minimizes the voltage drop caused by the threshold voltage of the MOS transistor in each stage of outputting the pumping voltage and removes the effect of the body effect.

Another object of the present invention is to provide a charge pump circuit that eliminates the voltage drop caused by the threshold voltage of the pumping voltage transmission means.

The charge pump circuit of the present invention for achieving the above object is the first and second pumping capacitors for receiving the first and second pumping clocks having a phase opposite to each other and outputting to the first and second nodes, respectively; A channel connected between the first node and the operating voltage terminal and a gate having a common contact with the drain to precharge the first node to a predetermined level, and a channel between the gate and the first node of the first transistor A second transistor having a connection and a gate connected to a first node, a substrate terminal connected to a second node, a channel connected between the first node and a second node, a gate connected to a second node, and a substrate terminal connected to the second node. A third transistor connected to the third node, a channel is connected between the second node and the third node, a gate is connected to the third node, and a substrate terminal is connected to the third node so that the voltage of the second node The comprise a fourth transistor for transferring to the third node.

Another configuration of the charge pump circuit according to the present invention for achieving the above object is a first capacitor which has a predetermined frequency through the first end of the electrode and the other end is connected to the first node, and one end of the electrode A second capacitor having a second clock signal having a phase opposite to that of the first clock signal through the second capacitor connected to the second node;

An NMOS transistor having a source connected to the first node, a drain and a gate commonly connected to an operating voltage terminal, a channel connected between the gate and the first node of the NMOS transistor, and a gate connected to the first node, and a substrate terminal A first PMOS transistor having a first PMOS transistor connected to a second node, a second PMOS transistor having a channel connected between the first node and the second node, a gate connected to the second node, and a substrate terminal connected to the third node; And a third PMOS transistor having a channel connected between the second node and the third node, a gate connected to the third node, and having a substrate terminal in a floating state.

1 is an overall system block diagram of a boosted voltage generation circuit.

2 is a conventional charge pump circuit diagram.

3 is a charge pump circuit diagram according to the present invention.

Explanation of symbols on the main parts of the drawings

10, 11, 100, 110: input node 20, 21, 200, 210: pumping capacitor

30-60, 150: NMOS transistors 31-51, 310, 410: pumping node

61, 510: boosting node 300-500: PMOS transistor

Referring to Figure 3 describes a preferred embodiment of the present invention in detail as follows.

3 illustrates a charge pump circuit according to the present invention, which is an example of outputting a final boosted voltage through a two-step pumping operation. Referring to FIG. 3, the NMOS transistor 150 has a drain and a gate connected to the operating voltage terminal VDD in common, and a source connected to the first pumping node 310 to set a voltage level of the first pumping node 310 before the pumping operation. Precharges the role.

Three PMOS transistors 300, 400, and 500 are connected in series to the gate of the NMOS transistor 150. Each of these PMOS transistors has a gate and a drain connected in common to form a diode connection. Two PMOS transistors 300 and 400 output the pumping voltage through two stages, and the last PMOS transistor 500 transmits the pumping voltage to the boosting node 510. The substrate terminal of the PMOS transistor 300 that outputs the first pumping voltage is connected to the drain of the PMOS transistor 400 of the next stage. The substrate terminal of the PMOS transistor 500 that transmits the pumping voltage is in a floating state or connected to the boosting node 510.

The pumping capacitor 200 is connected between the input node 100 receiving the pumping clock C1 and the first pumping node 310, and the pumping capacitor 210 is connected between the input node 110 receiving the pumping clock C2 of the oscillator and the second pumping node 410.

The charge pump circuit of the present invention configured as described above operates as follows.

Prior to the pumping operation, the first pumping node 310 is precharged to VDD-Vbi by the NMOS transistor 150. Where Vbi is the built-in voltage of the NMOS transistor 150. When the pumping clock C1 rises from 0 volts to the VDD level, the voltage level of the first pumping node 310 is increased to 2VDD-Vbi by the first pumping capacitor 200.

The pumping voltage 2VDD-Vbi at the first pumping node 310 is dropped to 2VDD-2Vbi by the PMOS transistor 400 and output to the second pumping node 410. At this time, when the pumping clock C2 rises from 0 volts to VDD, the voltage level of the second pumping node 410 is increased by VDD by the second pumping capacitor 210 to the level of 3VDD-2Vbi.

The pumping voltage 3VDD-2Vbi at the second pumping node 410 is dropped to 3VDD-3Vbi by the PMOS transistor 500 and output to the boosting node 510.

Therefore, the final boosted voltage can be expressed by the following equation.

VPP '= {VDD + m (VDD-Vbi)}-Vbi

Where m; The number of stages outputting the pumping voltage, VDD-Vbi; Voltage level at each stage during the pumping operation, -Vbi; Voltage drop by means of transfer of pumping voltage

As described above, the charge pump circuit of the present invention can minimize the voltage drop due to the threshold voltage of the MOS transistor performing the pumping operation, and the voltage drop due to the threshold voltage of the transmission transistor transferring the pumping voltage to the boosting node. Can be removed. In addition, by eliminating the effect of the body effect of the MOS transistor in each stage, it can be applied to a circuit using a low operating voltage, and the implementation of the circuit in fewer stages can take up less space and reduce power consumption.

Claims (3)

In the charge pump circuit of a semiconductor memory device, First and second pumping capacitors receiving first and second pumping clocks having opposite phases and outputting to the first and second nodes, respectively; A first transistor having a channel connected between the first node and an operating voltage terminal and a gate having a common contact with a drain to precharge the first node to a predetermined level; A second transistor having a channel connected between the gate of the first transistor and the first node, a gate connected to the first node, and a substrate terminal connected to the second node; A third transistor having a channel connected between the first node and the second node, a gate connected to the second node, and a substrate terminal connected to a third node; A fourth channel connected between the second node and the third node, a gate connected to the third node, and a substrate terminal connected to the third node to transmit a voltage of the second node to the third node; A charge pump circuit composed of transistors. The method according to claim 1, Wherein the first transistor is an NMOS transistor, and the second to fourth transistors are PMOS transistors. In the charge pump circuit of a semiconductor memory device, A first capacitor receiving a first clock signal having a predetermined frequency through one end of the electrode and the other end connected to the first node; A second capacitor receiving a second clock signal having a phase opposite to that of the first clock signal through one end of the electrode, and the other end thereof connected to a second node; An NMOS transistor having a source connected to the first node, a drain and a gate commonly connected to an operating voltage terminal; A first PMOS transistor having a channel connected between the gate of the NMOS transistor and the first node, a gate connected to the first node, and a substrate terminal connected to the second node; A second PMOS transistor having a channel connected between the first node and the second node, a gate connected to the second node, and a substrate terminal connected to a third node; A charge pump circuit comprising a third PMOS transistor having a channel connected between the second node and the third node, a gate connected to the third node, and having a substrate terminal in a floating state.