KR20000011125A - Wafer-level burn-in process and test - Google Patents

Abstract

PURPOSE: A wafer-level burn-in process and test is provided, which identifies a known good die to perform a semiconductor device in a wafer level. CONSTITUTION: The apparatus for wafer-level burn-in process and test comprises: test substrates (106, 108) for having active electronic components such as ASICs (106) mounted to an interconnection substrate or incorporated therein; a metallic spring contact element (110) for effecting interconnections between the ASICs (106); and a plurality of devices-under-test (DUTs) to be located on a wafer-under-test (WUT)(102), wherein test substrates (106, 108), the metallic spring contact element (110) and DUTs are all disposed in a vacuum vessel so that the ASICs (106) and can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. Thereby, it is possible to mount the precise alignment of a plurality of ASICs on the support substrate.

Description

Wafer Level Burn-in Process and Test

<Cross-Reference to Related Application>

This patent application is commonly filed on May 26, 1995, filed with US Patent No. 08 / 452,255 (hereinafter referred to as “the parent application”), and the corresponding PCT patent application filed on November 13, 1995. Part of a series of US95 / 14909 applications, the two applications of which are commonly owned and pending together with US Patent No. 08 / 340,144 filed November 15, 1994 and corresponding PCT filed November 16, 1994 United States Patent Application No. 08 / 152,812, now filed on November 16, 1993, filed on November 16, 1993, which is commonly owned and pending together; US Patent No. 5,476, 211, which is incorporated herein by reference, incorporated herein by reference in its entirety.

In addition, this patent application is part of the serial application of the following US patent applications, commonly owned and pending together:

08 / 526,246 filed September 21, 1995 (PCT / US95 / 14843, November 13, 1995);

08 / 533,584, filed Oct. 18, 1995 (PCT / US95 / 14842, Nov. 13, 1995);

08 / 554,902, filed Nov. 9, 1995 (PCT / US95 / 14844, Nov. 13, 1995);

08 / 558,332, filed November 15, 1995 (PCT / US95 / 14885, November 15, 1995);

08 / 573,945, filed Dec. 18, 1995 (PCT / US96 / 07924, 1996.5.24);

08 / 602,179 filed February 15, 1996 (PCT / US96 / 08328, May 28, 1996);

60 / 012,027, filed February 21, 1996 (PCT / US96 / 08117, 1996.5.24);

60 / 012,040, filed February 22, 1996 (PCT / US96 / 08275, May 28, 1996);

60 / 012,878, filed March 5, 1996 (PCT / US96 / 08274, May 28, 1996);

60 / 013,247, filed March 11, 1996 (PCT / US96 / 08276, May 28, 1996); And

60 / 005,189, filed May 17, 1996 (PCT / US96 / 08107, 1996.5.24)

All applications (except for provisional patent applications) are some consecutive applications of the aforementioned parent applications, all of which are incorporated herein by reference.

In addition, this patent application is part of the serial application of the following US patent applications, commonly owned and pending together:

60 / 030,697, filed November 13, 1996 by Khandros and Pedersen, and 60 / -tbd- filed December 13, 1996

〈Technical Field of Invention〉

FIELD OF THE INVENTION The present invention generally relates to implementing semiconductor devices, and more particularly, to conducting test and burn-in processes on semiconductor devices to identify known good dies (KGDs), In particular, it relates to the implementation of a semiconductor device at the wafer level (before singulated from a wafer or "diced").

〈Background of the invention〉

Semiconductor devices from microprocessors to memory chips are fabricated by performing a long series of processing steps such as etching, masking, depositing, etc. on a silicon wafer. Typical silicon wafers are disk shapes having a diameter of 6 inches or more. Many semiconductor devices, which are typically identical to one another, are fabricated on a single silicon wafer by placing them in a regular rectangular array. Cutting lines (scribe streets) are disposed between adjacent semiconductor devices on the wafer. Eventually, the device is unified from the wafer by sawing along the needle point street.

Due to a defect on the wafer or one or more of the processes, one of the semiconductor devices does not work as designed, and such defects may appear initially and become apparent only after the device has been used for an extended period of time. Therefore, it is important to test and electrically run the device for an extended period of time to ascertain which device is good and bad.

Typically, semiconductor devices are run (burn-in and test) only after undergoing another long series of "back-end" process steps that are unified (isolated) from the wafer and assembled into a final "package" form. do.

From a "total" standpoint, the conventional "back-end" process flow of the prior art is as follows (starting with a wafer fab):

Wafer sort # 1;

Laser repair;

Wafer sort # 2;

Wafer cutting;

Package assembly processes such as die attach, wire bond, encapsulation, lead trimming and forming, lead plating;

Electrical test;

Burn-in;

Electrical test; And

Indication and shipment of products.

Current semiconductor devices often include hundreds of terminals (ie, "pads" such as power supplies, ground, input / output, etc.), and current semiconductor wafers often include hundreds of semiconductor devices, so that each wafer has a die It has tens of thousands of pads or test points that need to be accessed to perform a test and / or burn-in process at the wafer level (ie, test all dies at a time) before unifying from the wafer. Precise alignment is also an important issue when dealing with pitches as close as 4 mils between adjacent pads. Again, it has been a long-standing goal to conduct test and / or burn-in processes on semiconductor devices before they are unified from the wafer.

U.S. Patent 5,570,032 (Atkins, et al.); "Micron patent"; 10/96 is a wafer scale burn-in wherein burned-in wafer 14 is bonded to printed circuit board 13 in electrical contact with pads on each die on the wafer using small conductive struts 15 on the printed circuit board. The phosphorus apparatus and process are described. Precise total wafer alignment with the printed circuit board is required to allow testing all dies on the wafer in parallel and eliminates the need to probe each die individually. The equipment is equipped with heating elements and cooling channels to generate the wafer temperatures needed for burn-in processes and testing. The method of use passes through burn-in and testing to eliminate processing of the defective die. Figure 1 of the Micron patent provides a general overview of the prior art process steps for shipping a wafer form article of manufacture. Figure 8 of the Micron patent provides a similar schematic of prior art process steps for shipping a wafer form article of manufacture when using the described methods of wafer scale burn-in process and testing. Providing a printed circuit board with reduced connections and control logic elements (microprocessors, multiple channels, etc.), and providing pre-test electronics contained within the printed circuit board (5 columns, see lines 53 to 60) It is also proposed in the micron patent that this is also possible.

US Patent No. 5,532,610 (Tsujide et al .; " NEC Patent "; 7/96) discloses a test substrate, an active circuit disposed on a test substrate for activating chips disposed on a wafer to be tested, and a pad. The equipment for the test semiconductor wafer is described with a plurality of pads arranged in an aligned state and positioned so that the bond pads of the chip are placed on the wafer when the test substrate is placed on the wafer. The test substrate 2 may be a wafer made of the same material as the wafer 1 tested in this manner. On the test substrate (wafer) 2, the conductive wire 7 extends from the pad 4 and is connected to a power source, a ground wire 18, an input / output line 9, and a chip select line 10. Figure 4 of the NC patent shows a test equipment 16 composed of a silicon wafer, wherein the backside of the silicon wafer is etched to have a square pyramid-shaped hole 21 that can serve as an alignment mark. ) Is easily brought into the resist state with the wafer 17 to be tested.

U.S. Patent No. 5,434,513 (Fujii et al., &Quot; Rohm Patent "; 7/95) is formed on the bottom surface of an intermediate semiconductor wafer in which bump electrodes are employed as test substrates, A semiconductor wafer testing equipment is described using an intermediate semiconductor wafer with electrodes formed on the top (opposite) side of the test substrate. A switching circuit is formed on the intermediate semiconductor wafer, and serves to connect a selected one of the bump electrodes to the pickup electrode in accordance with a switching control signal provided from the tester through the control electrode. The pickup electrode and the control electrode are connected to the tester via a pogo pin.

U.S. Patent No. 5,497,079 (Yamada et al., "Matsushida Patent"; 3/96) discloses that a plurality of semiconductor test chips 2 are mounted on one side of the main board 4 and the plurality of semiconductor integrated circuit chips 1 to be tested. The item describes a semiconductor test equipment, a semiconductor test circuit chip, and a probe card mounted on the opposite side of the main board 4. A computer 3 is provided for controlling the semiconductor test chip 2. Since the main test function has been incorporated into the test circuit chip 2, the computer 3 for selecting the test result may be a low cost computer. 5, 7 and 10 of the Matsushita patent show a test pattern generating means, a driver for applying the test pattern to the apparatus to be tested, data sorting means, and data determining means for determining whether or not the stored output data has failed. And a representative semiconductor test circuit chip 2 having means for transmitting the determination result to the workstation. 12 of the patent of Matsushida shows that a plurality of semiconductor test chips 2 are mounted on the probe card 103, and a plurality of probe needles 104 extend from the probe card (presumably from the opposite side of the probe card). The structure of the semiconductor test apparatus used for the wafer test in which the wafer 106 is tested is shown. When the control signal is transferred from the workstation to the semiconductor test circuit chip, the semiconductor test chip starts testing the semiconductor integrated circuit formed on the semiconductor wafer.

In general, previous attempts at design implementation of wafer level testing involve providing a single test substrate with a plurality of contact elements in contact with corresponding pads on the wafer being tested. As mentioned above, this can require tens of thousands of contact elements and extremely complex interconnecting substrates. For example, an 8-inch wafer can contain 500 16 MB DRAMs, each with 60 bond pads, which can include a total of 30,000 connections. The wafer under test (WUT) has 30,000 connections, 30,000 additional connections on the intermediate substrate, 30,000 additional connections on the test electronics, and an undetermined number of connections on the control electronics. . The fine pitch requirements of modern semiconductor devices also require very high tolerances to be maintained when placing the test substrate with the wafer being tested.

<Summary of invention>

It is an object of the present invention to provide an improved technique for performing wafer level burn-in processes and tests.

Another object of the present invention is to reduce the cost of semiconductor fabrication by enabling a series of wafer level process steps that result in a finished device having superior physical quality and higher reliability levels than conventional techniques allow.

According to the present invention, semiconductor devices are executed at the wafer level before they are unified from the silicon wafers from which they are manufactured. The term "exercise" herein includes, but is not limited to, performing burn-in and functional tests on semiconductor devices. A plurality of pressurized connections are made between a plurality of ununited semiconductor devices under test (DUT) on a wafer under test (WUT) and a test substrate using interconnecting elements such as spring contact elements to press between them. Execute the connection. The spring contact elements preferably have free ends mounted at the base to the WUT, ie directly to the WUT (ie the DUT on the WUT) and extending in a common plane above the surface of the WUT. The test substrate preferably has a coefficient of thermal expansion that corresponds well to the WUT. Or spring contact elements are mounted to the test substrate.

According to one aspect of the invention, the spring contact element is arranged on the WUT to unfold or to have a larger pitch at the tip than at its base. The spring contact element is suitably a composite interconnect element as described in the parent application.

In one embodiment of the invention the test substrate comprises a relatively large interconnect substrate and a plurality of relatively small substrates mounted and connected to the interconnect substrate. Each small substrate has a size (area) smaller than the size (area) of one of the DUTs. The small substrate is disposed on the front (facing the WUT) surface of the interconnect (support) substrate. It is also possible for one small substrate to be larger than an individual DUT and "mate" with two or more DUTs. Small substrates are suitably active semiconductor devices such as application-specific integrated circuits (ASICs). The design of the ASIC allows the number of signals supplied to the test board from an external source (such as a host controller) to be minimized.

In the case of a spring contact element mounted on the DUT, the tip of the spring contact element is preferably spread out to be wider than its mounted base, and the ASIC can be extra sized to mitigate alignment tolerances. A pad (terminal) is provided. The tip of the spring contact element can be unfolded but disposed in a smaller area within the area of the DUT to which it is mounted. The ASIC implementing the DUT is sized to correspond to the area of the tip of the spring contact element.

In an embodiment of the invention, the ASIC is provided with an indentation in its front face, each indentation receiving the tip of a corresponding spring contact element mounted in the DUT. This indentation may be provided directly on the surface of the ASIC or provided by a layer disposed on the surface of the ASIC. After receiving the tip, the ASIC can be moved laterally or rotated (in plane) to join the tip of the spring contact element with the sidewall of the indentation feature.

In accordance with one aspect of the present invention, a means is provided for ensuring accurate alignment of a plurality of ASICs with respect to an interconnect (supporting) substrate, the means being indented on the back side of the ASIC and corresponding indentation on the front side of the interconnect substrate. And a sphere disposed between the ASIC and the interconnect substrate.

According to one aspect of the invention, the test substrate is maintained at a temperature lower than the temperature of the WUT. This allows the DUT on the WUT to be raised to higher temperatures for the purpose of accelerating its burn-in without adversely affecting the life expectancy of the ASIC mounted on the interconnect substrate. By the coefficient of thermal expansion of the test substrate closely corresponding to the WUT, this limits the thermal window of the test substrate to a lesser amount than the WUT. The significant temperature difference between the WUT and the test substrate is easily preserved by placing the entire device (WUT and test substrate) in a vacuum environment.

In use, the test substrate is placed in contact with the WUT at room temperature. The capture feature on the front face of the ASIC (eg, indentation) holds the spring contact element in place. The DUT may then be powered up. The vacuum environment prevents heat from the powered DUT to heat the ASIC, allowing the ASIC to be operated at temperatures well below the burn-in temperature of the DUT.

According to one aspect of the invention, a signal for testing a DUT is supplied by an external source (host controller) in a first format, such as a series of flows of data over a relatively few lines, of the spring contact elements in contact with the DUT. It is converted into a second format, such as an individual signal for an individual relatively large number. Alternatively, at least a portion of the signals that test the DUT may be generated within the ASIC rather than being supplied by an external host controller.

According to one aspect of the invention, the ASIC may accumulate (monitor) test results from the DUT for subsequent transmission to the host controller. This information (test results) can be used to individually characterize each DUT. Alternatively, based on the test results from the DUT, the ASIC may terminate the burn-in on the DUT that failed additional tests and / or critical tests.

In another embodiment of the present invention, the ASIC may be manufactured directly on the silicon wafer rather than mounted on the silicon wafer. Redundancy is provided so that defective ASICs or parts thereof can be electrically replaced with each other.

An advantage of the present invention is that ASICs can be made inexpensively, and each "type" of ASICs can be specifically designed to accommodate (correspond) to a particular type of DUT.

Conventional burn-in techniques include placing the DUT in a convection oven to raise its temperature. It is generally not desirable to allow the ASIC to undergo such repeated heating cycles in the present invention. According to the present invention, the DUT and ASIC are in contact with each other and the DUT is powered to perform burn-in. This causes heat to be generated by the DUT, and in most cases sufficient heat is generated to meet the temperature rise requirements of the DUT without additional heat sources.

According to one aspect of the invention, the assembly of the DUT and the test substrate (interconnect substrate and ASIC mounted thereon) is placed in a vacuum environment and the only heat that the ASIC receives is a spring contact element that performs electrical connection between the ASIC and the DUT. A small amount of heat is conducted to the ASIC along the line. The DUT substrate and the test substrate are in contact with a liquid cooling chuck whose fluid goes to different controllers. The DUT substrate is generally subjected to higher temperatures than can be accommodated with the package portion and the test substrate is maintained at or below room temperature to allow for significantly improved electrical operation of the tester.

An advantage of the present invention is that the DUT is in direct contact with the ASIC, and the interconnect substrate supporting the ASIC can be a low density wiring board that receives very little signal from the host controller, and the ASIC itself is required for the execution of multiple DUTs on the WUT That is, it generates many signals of significant magnitude (e.g., 30,000).

The advantage of the present invention is that the DUT operation can be reliably done over a wide temperature range from below room temperature to the maximum temperature allowed by the semiconductor process without applying thermal pressure to the ASIC.

The present invention provides the best possible technique for the entire wafer-level assembly process.

Other objects, features and advantages of the present invention will be apparent from the following description.

<Brief Description of Drawings>

Reference is now made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention has been described in terms of these preferred embodiments, it will be understood that they are not intended to limit the spirit and scope of the invention to these specific embodiments.

1A is a side cross-sectional view of an apparatus for performing a wafer level burn-in and test method in accordance with the present invention.

Is a plan view of a small test substrate such as an ASIC (shown in dashed lines) over a DUT (shown in solid lines) in accordance with the present invention.

1C is a schematic perspective view of the DUT of FIG. 1B in accordance with the present invention.

1D is a plan view of the front face of the ASIC of FIG. 1B in accordance with the present invention.

Is a plan view of a small test substrate such as an ASIC (shown in dashed lines) over two DUTs (shown in solid lines) in accordance with the present invention.

Figure 2 is a side view of another embodiment for making contact between an ASIC and a DUT in accordance with the present invention.

FIG. 3A is a side cross-sectional view of one of the plurality of ASICs with contact features that are the bond pads shown in FIG. 1D to contact the tip of a spring contact element mounted to the DUT in accordance with the present invention.

3B is a side cross-sectional view of another embodiment of one of the plurality of ASICs with features for contacting the tip of a spring contact element mounted to the DUT in accordance with the present invention.

3C is a side cross-sectional view of one ASIC showing another embodiment with features for contacting the tip of a spring contact element mounted to a DUT in accordance with the present invention.

4 is a side cross-sectional view of one of the plurality of ASICs with features on their back side to ensure precise alignment to the interconnect substrate in accordance with the present invention.

Figure 5 is a side view illustrating a technique for making electrical connections between ASICs and an interconnect substrate in accordance with the present invention.

5A, 5B and 5C are side cross-sectional views illustrating a technique for providing an electrical passage from the front face of an electrical element, such as the ASIC of the present invention, to the back face of the ASIC in accordance with the present invention.

6A and 6B are side cross-sectional views illustrating a technique for mounting a spring contact element to a DUT in accordance with the present invention.

Figure 6C is a perspective view of the spring contact element of Figure 6B in accordance with the present invention.

Figure 7 is a schematic diagram of the device of the present invention (compared to Figure 1A) showing connectivity and overall functionality for a more detailed description of the invention in accordance with the present invention.

<Detailed Description of the Invention>

1A illustrates an apparatus 100 for performing a method of wafer level burn-in process and testing in accordance with the present invention. The wafer under test (WUT) is a temperature controlled vacuum such that the semiconductor devices 102a, 102b, 102c, 102d formed on the WUT (which is commonly referred to herein as device 102) face upwardly (as observed). Disposed on a suitable support such as chuck 104.

Many relatively small active electronic devices 106a, 106b, 106c, 106d, such as application integrated circuits (ASICs, commonly referred to as device 106), typically have the same as WUT 102. It is mounted on a relatively large interconnect substrate (substrate) 108 that is the same size (ie, diameter). In one example, both interconnect substrate 108 and WUT 102 have a diameter of 8 or 12 inches. Electronic element (ASIC) 106 and interconnect substrate 108 together constitute a “test substrate”.

WUT 102 includes a plurality of (four of many shown) semiconductor devices 102a, 102b, 102c, 102d to be tested, or a device under test (DUT).

A plurality of (four of many shown) spring contact elements 110 are mounted to the front surface (as seen in the figure) top surface of each DUT by its base and extend in a common plane above the front surface of the DUT. It is provided with a tip. Such spring contact elements are suitable, but are not limited to long composite interconnect elements of independent type of parent.

In use, the test substrates 106, 108 and the WUT 102 have a tip of the spring contact element 110 connected to a corresponding terminal (contact pad) 120 (shown in FIG. 1D) on the front side of the ASIC 106. It is in a predetermined alignment state (toward each other) until a pressurized electrical connection is made. Guide pins 112 disposed around the WUT and test substrate ensure precise alignment. (Interconnect boards may have a larger diameter than the WUT, and the guide pins may pass through corresponding guide holes in the interconnect board. A compression stop (block ring) 114 properly positioned on the WUT face limits the amount of travel, ie distance, that the tip of the spring contact element 110 is deflected when pressed against the contact pad 120.

As shown in FIG. 1A, the host computer 116 provides a signal to the ASIC 106 via an interconnect substrate 108. These signals are test signals for implementing multiple DUTs. Since the DUTs on the WUT are usually identical to each other, a pair of test signals (vectors) can be generated for multiple DUTs. Alternatively, test vectors are generated by each ASIC under the full control of the host computer. Power (eg, Vdd and Vss) is also properly supplied (eg, directly through the ASIC) from the power supply 118 to the DUT via the ASIC 106.

The interconnect substrate 108 is actually a wiring (interconnect) substrate, preferably a silicon wafer having the same coefficient of thermal expansion as the WUT 102. The ASIC 106 is suitably connected to the interconnect substrate by a coupling wire extending between the front (base when viewed in view) base of the ASIC to the front (base when viewed in view) plane of the support substrate.

An important feature of the present invention is the direct connection between the DUT and the ASIC (via the spring contact element 110). The location is where the majority of the connections of the entire system are made (described in detail below), and very few (very few) connections need to be made within the interconnect substrate 108 itself. Direct connection between the ASIC and the DUT is facilitated by placing the ASIC on the DUT side (front side) of the interconnect substrate. For example, regardless of where the ASIC is placed, tens of thousands (e.g., 30000) connections to the DUT may be connected to the interconnect substrate (i.e. by the various types of spring contact elements disposed on the interconnect substrate rather than through the ASIC). If not, these 30,000 connections would have had to enter the interconnect substrate. As described in detail below, these tens of thousands of signals can be generated directly to the DUT by the ASIC itself according to very few (eg, four) signals entering the ASIC from the host controller through the interconnect substrate.

WUT 102 and test substrate 106/108 are hermetically sealed containers in communication with a vacuum source (not shown) such that the techniques of the present invention can be performed at least in some vacuums, including high vacuum or other controlled atmospheric conditions. It is appropriate to be placed in 130. As mentioned above, the vacuum advantageously thermally isolates the DUT from the ASIC.

According to a feature of the invention, the temperature of the test substrate 106/108 is controlled so that it can be maintained at a temperature that is generally independent of the temperature of the WUT 102 (typically significantly lower than the WUT 102) during burn-in. To the chuck 104a.

Panning out to the tip of the spring contact element

As mentioned above, modern semiconductor devices often have a large amount of bond pads disposed at a narrow pitch of approximately 0.0254 mm (4 mils). The spring contact element 110 has its base mounted to the coupling pad of the DUT. If there were no spring contact elements to project evenly (eg, parallel to each other) from the DUT, the tip would have been 0.0254 mm (4 mils) pitch and the alignment of the corresponding capture pad of the ASIC would have been difficult.

As shown in FIG. 1B, each DUT, such as DUT 102a, has a plurality of (only 24 shown) bond pads 107 (shown in rectangle) arranged along the centerline of the DUT. An independent spring contact element 110 is mounted to each engagement pad and is generally arranged at 90 ° to the centerline of the DUT. As shown in Fig. 1B, the spring contact elements can be arranged such that the lengths are not only staggered with each other but also extend in opposite directions to each other. For example, the first spring contact element 110a is relatively long and extends by a first distance in a first direction from the centerline of the DUT 106, and the second spring contact element 110b is relatively long and extends from the centerline of the DUT 106. Extends by a first distance in a second direction opposite the one direction, and the third spring contact element 110c extends by a second distance that is relatively short and is less than the first distance in the first direction from the centerline of the DUT 106. The fourth spring contact element 110d is relatively short and extends by a second distance in a second direction from the centerline of the DUT 106.

As best shown in FIG. 1B, the tips (shown as circles) of the spring contact element 110 are all disposed in an area smaller than the area of the DUT 106a (the area within the periphery), the small area corresponding to the corresponding ASIC. It is an area | region of 106a, and the outer periphery is shown with the dashed rectangle in the figure. In this way, the free end (tip) of the spring contact element 110 is facilitated to be larger in pitch (spacing) than the engagement pad 107 of the mounted DUT.

It is within the scope of the present invention that the tip of the spring contact element 110 is limited to a much smaller spacing than shown by the dashed rectangle of FIG. 1B, for example to accommodate a smaller DUT.

1C is a schematic perspective view of the DUT 102a of FIG. 1B with the base tip of the spring contact element 110 arranged along the centerline of the DUT.

As shown in FIG. 1D, the advantage of the present invention is that the spring contact element 110 is because the " capture " (coupling) pad 120 of the ASIC 106 is much larger (than the size of the coupling pad 107 of the DUT). It is possible to alleviate the tolerance limit for the tip position.

The parent application describes a number of ways in which an elastic interconnect element can be mounted to a semiconductor device while performing a pitch magnification between the base of the interconnect element and its tip.

The interface between the test board and the WUT is shown as having one ASIC per DUT, each of which is aligned with the corresponding one of the DUTs. It is within the scope of the present invention that other relationships can be established. For example, as shown in FIG. 1E, one ASIC (126, its periphery is shown by a dashed rectangle) may extend to two adjacent DUTs 102a and 102b.

The main feature of the present invention is that ASIC 106 disposed as close to DUT 102 as possible, i.e., located on the DUT side of interconnect substrate 108, is readily provided with unique functionality. Many advantageous results are achieved with this function. The number of signals that must be provided from the host computer 116 to the interconnect substrate 108 is considerably less, and the number of signals that must be entered by the interconnect substrate is less. The mitigation of signal carrying restrictions on these interconnect substrates allows for cost reduction through securing flexibility in the material, design and implementation of the interconnect substrate. The proximity of the ASIC to the DUT and thus the direct connection therebetween avoids the disadvantage of long signal paths and facilitates rapid testing of the DUT.

Appropriate spring contact elements as mentioned above may be employed to make a pressurized connection between the ASIC and the DUT.

It is also within the scope of the present invention that the spring contact element is mounted to the ASIC rather than the DUT. This is shown in FIG. 2, in which a plurality (only four are shown) of the spring contact elements 210 (compare 110) are mounted to the ASIC 206 by their base and the tip of the spring contact element 210. The (end) is positioned such that pressure contact of the DUT 202 (compared to 102) to a corresponding mating pad (not shown) is made. That is, suitable means for performing the connection between the ASIC and the DUT may be employed to put the techniques of the present invention into practice. It is also within the scope of the present invention that other than the spring contact element is not limited to microbumps or the like and is employed to perform the connection between the ASIC and the DUT.

Capture of the tip of the spring contact element

As discussed above, the tip of the spring contact element mounted on the DUT can simply be “captured” by pressing against the corresponding capture pad of the ASIC, and perform a pitch magnification along the spring contact element to achieve a very large size of the ASIC. It has been shown that tolerance limits are alleviated by having a capture pad. We will now discuss other techniques for making the connection between the tip of the spring contact element and the ASIC.

3A shows a spring contact element 310 mounted to a DUT 302 (compare 102) according to a collection pad, which is a bond pad 308 (compare 120) disposed on the front face of an ASIC 306 (compare 106). A basic embodiment is shown for capturing a tip (compare 110).

According to one aspect of the invention, within the front face of the ASIC to ensure reliable alignment of the tip of the spring contact element to the ASIC during burn-in process and testing according to the topology of the "capture". Or on the front face.

3B shows one 326 of a plurality of ASICs (compare 106) and one of a plurality of DUTs (compare 322, 102a) mounted on an interconnect substrate (not shown, see 108), between the two; A technique for performing a reliable pressure connection is shown. As in the previous example, a plurality of spring contact elements 330 and 110 are mounted to the front of the DUT 322 by its base and extend from the front of the DUT 332. In this example, the spring contact elements are arranged at a pitch whose tip (end) is larger (coarse) than its base.

A plurality of (only two are shown) indentations 328 (at least three sided pyramid shapes are suitable) extend from the front into ASIC 322. The indentations 328 as well as the other indentations described below are readily formed using conventional semiconductor manufacturing techniques such as micromachining.

Metallization (not shown) is applied to the sidewall of the indentation 328, and the metallization is in electrical communication with the active element (not shown) of the ASIC 326.

In use, as the ASIC 326 and DUT 322 are brought together, the tip of the spring contact element 330 enters the indentation 328, after which the ASIC (crosses the page as shown). Is moved laterally (slightly around an axis perpendicular to the page) to allow the tip of the spring contact element 330 to engage the sidewall of the indent 328 with sufficient force to ensure a reliable electrical pressurization connection .

An alternative technique for capturing (engaging) the tip of the spring contact element is shown in FIG. 3C. In this case, the ASIC 346 (compared to 326) is formed in a conventional manner with a plurality of pads (terminals) 344 in front (two of which are shown). An insulating material layer 350, such as a silicon die, micromachined so that a plurality of (two of which are shown) holes 348 (compared to 328) extends through and aligns with the contact pad 344 is provided with an ASIC 346. Is placed above the front. In other words, in this alternative technique, rather than directly forming an indentation 328 on the surface of the ASIC 346, a separate upper structure 350 provides equivalent capture features 348. As in the previous example, the sidewalls of the capture feature 348 can be metalized and the ASIC can be moved laterally or rotationally relative to the DUT (not shown), such that the ASIC 346 and the spring contact element 340 (Compared to 330) to ensure a reliable electrical pressurized connection. Silicon die 350 may be insulated with nitride.

It should be noted that the means on the ASIC intended to come into contact with the tip of the spring contact element should be rugged. To this end, for example, the capture pads 120 or 308 or 344 may be coated (eg, plated) from 0.5 mils to 1.0 mils with a wear resistant electrically conductive material such as nickel. In a similar manner, indentations (capture features) 328 may be coated with an equivalent amount of nickel.

Alignment of the small board with respect to the interconnect board

As discussed above, it is desirable for a plurality of electronic devices, such as ASICs, to be mounted on a larger interconnect substrate. In particular, this makes it possible to avoid the requirement to yield good active devices over the entire surface of the interconnect substrate. (I.e., in the case of a silicon wafer interconnect substrate, the circuitry of the ASIC can be incorporated directly on the silicon wafer.) Obviously, a suitable mechanism must be provided to ensure correct alignment of the plurality of ASICs with respect to the interconnect substrate. .

4 illustrates a technique 400 to ensure correct alignment of a plurality of ASICs 406 (106, 206, 306, 346) with respect to a large interconnect substrate 408 (compare 108). To show. In this case, at least two (only two are shown) indentations 412 on the back of each ASIC 406 (top view, in the figure) in a manner similar to the indents 328 and 348 described above. Is provided, the indentation 412 is in the form of a suitable pyramid that extends into the back of the ASIC 106. Such indentation 412 may be defined and formed by lithography with strict tolerances using conventional semiconductor fabrication techniques.

As described above, an equivalent indentation 414 is formed on the front side of the interconnect substrate 408, which is suitably a semiconductor wafer (shown as the bottom side in the figure). This indentation 414 can likewise be formed using conventional semiconductor fabrication techniques to have tight tolerances 306.

Each indentation 412, 414 has a dimension ("width") measured across the surface of the corresponding ASIC 406 or interconnect substrate 408 in which the indentation is formed. The width of the ASIC indentation 412 is preferably the same as the width of the interconnect substrate indentation 414, all of which are suitably in the range of 3 mils to 5 mils, for example 4 mils.

In order to assemble the ASIC 406 to the interconnect substrate 408, a small ball 420 having a diameter equal to the width of the indents 412, 414 corresponds to the indent 412. Disposed between the indents 414 to allow the ASIC 406 to be correctly aligned on the front of the interconnect substrate 408. The diameter of the ball 420 is preferably slightly larger than the width of the indents 412, 414, for example by 2 + 1 mil, which is the front (bottom view of the interconnecting substrate) 408 and the ASIC ( There is a small gap in the controlled dimension between the back side of the 406 (upper side in the figure). For example, the dimension of the gap (vertically when viewed) is in the range of 2 to 5 mils.

A suitable adhesive (not shown), preferably thermally conductive, is disposed in the gap (ie between the ASIC and opposite sides of the interconnect substrate) to secure the ASIC to the interconnect substrate. One example of a suitable adhesive is a silver-filled epoxy, which is preferably of the kind that allows defective ASICs to be removed and replaced (by appropriate solvent or heat).

Any suitable mechanism for aligning the ASIC to the interconnect substrate may be employed within the scope of the present invention. For example, attention is directed to alignment techniques for aligning a large substrate (eg 622) and a small substrate (eg 620) described in PCT / US96 / 08117 described above. For example, within the scope of the present invention, soldering features of substantial size (eg, 10 mil X 20 mil rectangular, etc.) are provided on the back side of the ASIC, equally sized soldering features are provided on the front of the interconnect substrate, and solder Preforms (or gold-tin) are placed between them and flow back, so that the surface tension exerted by the solder in the liquid state will ensure correct alignment of the ASIC to the interconnect substrate.

Connection of ASICs to Interconnect Boards

As mentioned above, the ASIC is suitably electrically connected to the interconnect substrate using conventional wire bonding techniques.

In order to power a plurality of DUTs on the WUT, a relatively large amount of power is required for the purpose of burn-in the DUT. For example, several hundred watts for the entire WUT. Due to the physical arrangement of the system of the present invention, it is desirable to transfer this power through the ASIC and through the corresponding spring contact element. In the following description, a technique for power supply "through" ASCI is described.

5 is typically an ASIC 506 (compare 106, 206, 306, 326, 346, 406) electrically connected to an interconnect substrate 508 (compare 108) by a bonding wire (not shown, see 510). To show. In contrast to the relatively small connections required to start up an ASIC that provides a signal to the DUT (not shown), a significant amount of power is required to power the DUT to perform burn-in, and the ASIC and interconnect board It requires a significant number of mating wires in between. The number of coupling wire connections between the ASIC and the interconnect substrate is approximately equal to the number of power connections made to the DUT (eg, 102) (eg, via the spring connection element 110), which may be more than one hundred.

According to one aspect of the present invention, power is transferred between the interconnect substrate and the ASIC using an interconnect means capable of delivering greater power (watts) than conventional bonding wires, thereby reducing the number of required connections.

5A, 5B, and 5C illustrate a technique 500 for making electrical connections between an ASIC and an interconnect substrate.

5A shows the ASICs 106, 206, 306, 326, 406, 506 as compared, where the ASIC 526 extends completely through the body of the ASIC 526 from the front 526a to the back 528b. It has a plurality of small holes (522 shown). These holes 522 are suitably formed in a manner similar to that employed for creating the indents 308 on the front of the ASIC 306 and the indents 412 on the back of the ASIC 406, i.e. 522a (first portion of hole 522) is formed from the front surface 526a of the ASIC 526 to a depth of at least half the thickness (vertically in the figure) of the ASIC 526, and the indentation 522b (Second portion of the hole 522) is formed at the back surface 526b of the ASIC 526 to a depth sufficient for the second hole portion 522b to be adjacent to the first hole portion 522a. The dimensions of the apertures 522a and 522b are such that the continuous opening can extend through the ASIC die 526.

5B shows the next step of the process, where a conductive layer (e.g., titanium-tungsten, etc.) is deposited by sputtering or the like into the first and second holes, whereby the first conductive layer portion 524a is deposited. It extends to the first hole 522a and the second conductive layer portion 524b extends to the second hole 522b. As shown, there is a discontinuity between these two conductive layer portions 524a, 524b. As shown, the conductive layer portions 524a and 524b preferably extend from the interior of the apertures onto the corresponding surfaces 526a and 526b of the ASIC 526. In fact, one side (left or right in the drawing) of each hole 522a, 522b will accommodate more sputtering material than the opposite side (right or left in the drawing) of the hole.

5C shows the next step of the process, where the discontinuity between two conductive layer portions 524a and 524b is connected (bridged) by a mass of conductive material (eg gold or nickel) 528. The conductive material is suitably applied by plating (i.e. by immersing the ASIC in the plating bath and plating to a sufficient extent to connect the two conductive layer portions).

The above process for forming a conductive bias in an ASIC is equally applicable to the interconnect substrate of the present invention.

In addition to plating to connect the discontinuities, it is also within the scope of the present invention to place a mass of conductive material (eg, silver filled epoxy) in the apertures to connect the discontinuities.

Spring contact element

Long standing free spring contact elements, such as those shown in FIG. 1 (element 110) and those shown in FIG. 2 (element 210), and methods of mounting such spring contact elements to a substrate comprising a semiconductor device are for example. It is disclosed in detail in the above-mentioned U.S. applications and PCT applications, such as U.S. Patent Application 08 / 452,255 and its corresponding PCT Application US95 / 14909. The spring contact elements described in the patent applications are referred to as "composite interconnect elements" and "elastic contact structures" and the like, which usually wire-bond flexible (eg, gold) wires to terminals of electronic devices, and Forming and cutting the wire into a wire stem having a spring shape, involves overcoating the wire stem and adjacent areas of the terminal with at least one layer of hard material (eg nickel). Such a composite interconnect element can be mounted to an electronic device after being fabricated on a sacrificial substrate.

Any suitable spring contact element used to implement the wafer level burn-in process and test system of the present invention is also within the scope of the present invention.

6A-6C illustrate a modified technique for forming a spring contact element that can be used in the present invention. These spring contact elements are "manufactured" rather than "assembled".

As shown in FIG. 6A, one example of a technique 600 for fabricating an elastic free standing contact structure involves applying a plurality of patterned insulating layers 604, 606, and 608 on top of a semiconductor device 602. . The semiconductor device 602 has a number of bond pads 612 on its surface (or at an accessible portion thereof). The layers are patterned to have openings that are parallel to the bond pads and the openings allow the opening of one layer (eg, 608, 606) to extend from the bond pad more than the openings of the underlying layer (eg, 606, 604). Take shape and size. Layer 614 of conductive material is applied to the opening. Next, a conductive mass of material 620 may be formed in the opening by electroplating or the like. As shown, this mass is secured to the bond pad 412 and is free standing (only one end thereof is attached) after the insulating layer is removed (best shown in FIG. 6B). By appropriately selecting materials and shapes, these agglomerates 620 can function as an elastic free standing structure. As best shown in Figure 4C, the fabricated contact structure 620 of Figures 6A and 6B extends vertically as well as laterally over the surface of the component 602. In this manner, the contact structure 620 is readily manufactured to be flexible in the z-axis (as shown by arrow 622) as well as the xy plane (as shown by arrow 624) that is parallel to the surface of the component 602. .

Burn-in process of the DUT

The burn-in process of a semiconductor device is tasked with raising the power of the device at elevated temperatures to accelerate the failure of a potential faulty device (ie, which may inadvertently cause "infant mortality"). Entails. This acceleration can be enhanced by raising the temperature and the applied operating voltage. However, if the semiconductor device is already packaged, the material of the package (eg plastic) places a limit on the temperature at which the packaged semiconductor device can be exposed to a burn-in furnace. Very few of the packages can withstand prolonged exposure to high temperatures, especially when organic materials are included in the package.

A typical burn-in process involves heating a packaged semiconductor device to a temperature of 125 ° C. for a 96 hour period. Usually, the burn-in process time is halved every 10 ° C. rise in the junction temperature. For example, if the DUTs require one day to burn in at 150 ° C., they may be effectively burned in for half day at 160 ° C.

Another obstacle to elevated burn-in temperatures is that any test apparatus in the burn-in furnace will heat up, accelerating its failure. For example, the ASIC of the present invention accelerates failures when exposed to the same burn-in temperature as in the DUT.

According to one aspect of the invention, the burn-in process is carried out at a temperature of at least 150 ° C. Since the DUT is not yet packaged and the spring contact element mounted on the DUT (or ASIC) is entirely metal, this process step may result in the destruction of packaged semiconductor devices containing materials that cannot withstand these elevated temperatures. You can put the DUT on. The burn-in process may be performed in all portions of the wafer-resident (ununited) semiconductor device (DUT) or in certain portions of the wafer-resident semiconductor device.

As described above, ASIC 106 and WUT 102 are easily disposed in a container that can be evacuated to produce a substantial vacuum, and WUT 102 is easily mounted on temperature controlled chuck 104. The power controlled chuck 104 operates in cooling mode in most cases where the power required to initiate the burn-in process is sufficient to generate heat and to raise the DUT to the desired burn-in temperature. Since a vacuum is created, a minimum heat path is provided between the spring contact element 110 and the other DUT and ASIC, thereby allowing the ASIC to operate at a temperature substantially lower than the burn-in temperature of the DUT.

Reduced connection demands and other benefits

Figure 7 illustrates the case of the system 700 (compared to 100) of the present invention, showing various features applicable to various examples of the techniques of the present invention. These features allow a plurality of ASICs (compare 706; 106) to be mounted to an intermediate connection (support) substrate 708 (compare 108) and a plurality of DUTs (702; compare 102) to be connected to the front of the ASIC. Front-mounted spring contact elements 710 (compared to 110). The power source 718; compared to 118) provides power to the DUT 702 via the interconnect substrate 718; 118 and the ASIC 706 and means 710 for interconnecting the ASIC and the DUT. Bring it into a state for the process.

The host controller 716 (compare 116) provides a signal to the ASIC 706 via the interconnect substrate 708. Very few signals need to be provided to each ASIC 706, for example, a continuous stream of data, to individually control multiple ASICs 706 mounted on the interconnect substrate 708.

7 is an example of a system for testing a DUT that is a memory device. The host controller 716 has very few (e.g. four) lines, i.e. lines for data output (marked as DATA OUT), lines for data return (marked as DATA BACK), lines for ASIC reset (marked as MASTER RESET) And a data bus that requires a clock signal transfer line (denoted CLOCK) to a plurality of ASICs 708. All ASICs mounted on the interconnect board are connected to these four "common" lines connected on the interconnect board to all ASICs. This illustrates the simplicity in realizing (ie manufacturing) an interconnect substrate 708 that can be used to test a large number of complex electronic devices (DUTs).

The power (indicated by + V) and ground (indicated by GROUND) connections are likewise easily handled by the interconnect substrate. Basically, only two lines are needed in the interconnect substrate, which is preferably realized as planes (ie power plane and ground plane) in a multilayer interconnect substrate.

A problem associated with the prior art of raising the power of multiple DUTs is the power drop through the interconnect substrate. This problem is overcome by the present invention by supplying an elevated voltage to the ASICs 706 and mounting a voltage regulator (denoted as VOLTAGE REGULATOR) in the ASIC.

Those skilled in the art will appreciate that other functions, not particularly illustrated, may already be built into the ASIC. For example, a unique address and address decoding function can be assigned to each ASIC to individualize the response to a series of data flows coming from the controller 716.

As mentioned above, interconnect substrates require almost no separate lines or nodes. However, each ASIC can be easily connected directly to a DUT to which the interconnect element is directly connected through a plurality of interconnect elements (spring contact elements). Many ASICs on an interconnect substrate can connect several of the multiple connections between ASICs and DUTs. This is a significant advantage over the prior art. For example, referring to the Matsushita patent system as an example, in an example requiring multiple (eg five hundred) non-trivial DUTs (eg 16M DRAM), the interconnect substrate 4 Is very complex (e.g. providing 30,000 connections between each pin of the test circuit chip 2 and the corresponding 30,000 contact elements between the interconnect substrate 4 and the DUT 1), thus making And production will be very difficult.

A great advantage of the present invention is that the overall " connection count " can be substantially reduced, most notably in the interconnect substrate. The 8-inch wafer described above can include a total of 30,000 connections, including 500 16M DRAMs with 60 bond pads each. Using the present invention, these 30,000 connections are made directly between ASICs and DUTs. From the ASICs back to the host controller through the interconnect board. For example, power (two lines) and a series of signal paths (as little as two lines from the power source to the ground line). This is in particular in contrast to any prior art that requires connecting ASICs to means for interconnecting an interconnect substrate to DUTs via an interconnect substrate even when using the ASICs or similar means of the present invention. The present invention completely eliminates this problem by directly connecting between ASICs and DUTs and essentially reduces the number of nodes needed on the interconnect substrate.

Another advantage of the present invention is that ASICs are on the WUT side of the support substrate, thereby minimizing the signal path between ASICs and DUTs and facilitating at-speed testing of the DUT. Other structures, such as ASICs mounted on the opposite side (from the WUT) of a support (wiring) substrate, present additional signal risks to realizing a feasible system by the presence of signal delays and unnecessary paracitics. Will cause.

Techniques for providing the following back-end flow have been described. An interconnect element (eg, spring contact element) is fabricated on an ununited semiconductor device. Encapsulate (optionally), wafer level speed sort, wafer cut and unify, and ship product.

While the invention has been shown and described in detail in the drawings and above detailed description, it is to be understood that the preferred embodiments are by way of example and not limitation, and that all modifications within the spirit of the invention should be protected. . In addition, those of ordinary skill in the art will appreciate that many other variations of the subject matter described above are within the scope of the following claims. Many such variations are described in the original application.

For example, the test may be performed during burn-in and may be controlled in any test order with a relatively small signal to the ASIC with active semiconductor devices such as ASICs placed on the test substrate and reliable results may be obtained. It is within the scope of the present invention that the operation may be initiated in response to a signal by the ASIC.

For example, an interconnect substrate may be a silicon wafer without mounting multiple ASICs on one support (interconnect) substrate, and ASICs may be formed directly on the wafer using conventional semiconductor fabrication techniques. In such a case, it is advantageous to provide an extra test element of the wafer, test the wafer, and ensure that the element that is determined to function is turned on (the element that is determined to not function is turned off).

Claims (60)

A wafer level burn-in process and a method of performing a test of a plurality of semiconductor devices (DUTs) on a semiconductor wafer, Providing a plurality of active electronic devices having terminals on one side, A method for performing a wafer level burn-in process and testing comprising providing means for direct electrical connection between terminals of a plurality of DUTs and terminals of an active electronic device. 2. The method of claim 1, wherein the terminal of the active electronic device is a capture pad. 3. The method of claim 2, comprising reinforcing the capture pad. The method of claim 1, wherein the terminal of the electronic device is a collecting structure. The method of claim 1, wherein the ratio between the number of DUTs and the number of active electronic devices is 1: 1. 2. The method of claim 1, wherein the ratio between the number of DUTs and the number of active electronic devices is 2: 1. 2. The method of claim 1, wherein said means for performing direct electrical connection is a spring contact element mounted to a DUT. 2. The method of claim 1, wherein said means for making a direct electrical connection is a spring contact element mounted to an active electronic device. The method of claim 1, wherein the active electronic device is an ASIC. 2. The method of claim 1, further comprising mounting the active electronic device on an interconnect substrate. The method of claim 10, Providing a host controller, And connecting the host controller to the active electronic device through an interconnect substrate. 12. The method of claim 11, further comprising providing a test signal for testing the DUT over several common lines from the host controller to the interconnect substrate and from the interconnect substrate to the active electronic device. Processes and methods of performing tests. 13. The method of claim 12, further comprising selectively activating the active electronic element to selectively burn in and test a selected one of the DUTs. The method of claim 10, Providing power; And connecting the power supply to the active electronic device through an interconnect substrate. 15. The method of claim 14, further comprising providing a voltage regulator to the active electronic device. 2. The method of claim 1, further comprising maintaining the active electronic device at a lower temperature than the DUT when burn-in the DUT. A system for performing a test and wafer level burn-in process of a plurality of semiconductor devices (DUT) on a semiconductor wafer (WUT), A test substrate having a plurality of individual active electronic devices, Means arranged to receive a direct connection from a plurality of semiconductor devices (DUTs) arranged on the active electronic device and on a semiconductor wafer (WUT) in use. 18. The device of claim 17, wherein the means for receiving a direct connection comprises a capture pad on the active electronic device, wherein the integrated connection is mounted to a spring contact element that is mounted on the DUT and manufactured to make a press connection to the capture pad in use. System, characterized in that it is executed by. 18. The spring contact element of claim 17 wherein the means for receiving a direct connection comprises a capture feature on the active electronic device, wherein the integrated connection is mounted on a DUT and manufactured to make a press connection to the capture feature in use. The system characterized in that executed by. 18. The system of claim 17, further comprising a plurality of interconnecting elements extending directly between the DUT and the active electronic device. 21. The system of claim 20, wherein the interconnect element extends from the fine pitch in the DUT to the coarse pitch in the active electronic device. 21. The system of claim 20, wherein the interconnect element is mounted to a DUT. 21. The system of claim 20, wherein the interconnect element is mounted to the active electronic device. 21. The system of claim 20, wherein said interconnect element is a spring contact element. 25. The system of claim 24, wherein the spring contact element is a composite interconnect element. 25. The system of claim 24, wherein the spring contact element is a manufactured interconnect element. 18. The system of claim 17, comprising a vacuum vessel made to receive a test substrate and the WUT in use. 18. The system of claim 17, wherein the test substrate is a semiconductor wafer and the active electronic device is incorporated into the test substrate. 18. The system of claim 17, wherein the active electronic device is an ASIC mounted on the front side of the interconnect substrate. 18. The system of claim 17, further comprising means for aligning the ASIC relative to the interconnect substrate. 18. The system of claim 17, wherein, in use, the active electronic device accepts signals over a relatively small signal line from an external host computer and transmits the signals to a DUT over a relatively large number of interconnect elements. 18. The system of claim 17, wherein, in use, the active electronic device generates at least some of the plurality of signals required to test the DUT in response to control signals from an external host controller. A method for performing a burn-in process on a semiconductor device, the method comprising: Connecting a test substrate to at least one semiconductor device (DUT), Powering up to at least one DUT; Maintaining the at least one DUT at a first temperature; Maintaining the test substrate at a second temperature independent of the first temperature. The method of claim 33, wherein the second temperature is lower than the first temperature. 34. The method of claim 33, wherein the second temperature is not greater than the first temperature. 34. The method of claim 33, comprising placing a test substrate and at least one DUT in a vacuum environment, wherein the vacuum provides a thermal barrier between the at least one DUT and the test substrate. 34. The method of claim 33, wherein the at least one DUT is a plurality of semiconductor devices on a semiconductor wafer (WUT). 34. The method of claim 33, further comprising connecting the test substrate to at least one DUT having a plurality of spring contact elements. 34. The method of claim 33, further comprising connecting the test substrate to at least one DUT equipped with a plurality of spring contact elements. 40. The device of claim 39, wherein the spring contact element is elongated and mounted to the at least one DUT by its base and has a free end, The method comprising spreading the free end of the spring element such that the spring element has a coarse pitch at the free end than at its base. A method of testing a semiconductor die prior to singulation from a semiconductor wafer, Mounting a plurality of spring contact elements each having a free end on a plurality of semiconductor die on the first semiconductor wafer; Pressing a test substrate having a plurality of terminals towards the surface of the die to realize a plurality of pressure connections between the free ends of the spring contact elements and the respective terminals; Providing a signal to the die across a spring contact element to test the semiconductor die. 42. The method of claim 41 wherein the spring contact element is a composite interconnect structure. 42. The method of claim 41, further comprising unifying the die from the wafer after testing the semiconductor die. 42. The method of claim 41 wherein the test substrate is a second semiconductor wafer. 42. The method of claim 41 wherein the test substrate comprises a relatively large interconnect substrate and a plurality of relatively small electronic elements mounted to the front of the interconnect substrate. 42. The method of claim 41, further comprising performing a burn-in process on at least a portion of the semiconductor die while the test substrate and the semiconductor die are connected. 47. The method of claim 46, further comprising placing the test substrate and the semiconductor die in a vacuum during the burn-in process. 47. The method of claim 46, further comprising maintaining the test substrate at a temperature lower than the temperature of the semiconductor die during the burn-in process. A method of aligning a plurality of electronic elements relative to an interconnect substrate, Forming an indentation on the back side of each electronic element, Forming a corresponding indentation on the front side of the interconnect substrate; Disposing a spherical element between the indentation and the corresponding indentation. 50. The method of claim 49, wherein the electronic device is an ASIC, wherein the ASIC and the interconnect substrate comprise a test substrate of a system for performing wafer level burn-in processes and tests of a semiconductor device. A method of performing a connection between tips of an elongate interconnect element extending from a first electronic element and a second electronic element, Forming an indentation on the front surface of the second electronic element, Combining the first and second electronic elements such that the tips of the long interconnection element are disposed in the indentation, Moving the second electronic element in a direction selected from the group consisting of lateral or rotational directions to achieve a pressurized connection between the tip of the elongate interconnect element and the sidewall of the indentation. 53. The method of claim 51 wherein the long interconnection element is a spring connection element. 53. The method of claim 51, wherein the first electronic element is at least one semiconductor device. 53. The method of claim 51, wherein the first electronic device is a plurality of semiconductor devices on a semiconductor wafer. The method of claim 51, wherein the second electronic device is a test substrate. 53. The method of claim 51, wherein the second electronic device is an ASIC mounted on a test substrate of a system for performing a wafer level burn-in process of a semiconductor device. In the method of implementing at least one semiconductor device (DUT), Placing the active electronic device in direct electrical contact with the at least one DUT; At least one by passing power or a signal through an interconnecting element extending directly between a terminal on the active electronic device and a terminal on the DUT, without any other means such as an interconnect substrate in the electrical path between the active electronic device and the DUT. Powering the DUT. 59. The method of claim 57, wherein the interconnect element is a spring contact element. 58. The method of claim 57, further comprising: mounting a plurality of active electronic devices on an interconnect substrate; Transmitting a relatively small number of signals from the host controller to the active electronic device via the interconnect substrate; And transmitting a relatively large number of signals from the active electronic device to the plurality of at least one DUT directly above the plurality of at least one DUT and the interconnect elements extending between the plurality of active electronic devices. 59. The method of claim 57, wherein the active electronic device is an ASIC.