KR20000011052A - Address generation and data path control to and from multi-transmitting packet - Google Patents

Abstract

PURPOSE: An ethernet controller is provided to generate an address by efficiently converting 16-bit data into 32-bit data and control various write/read functions controlled by an ethernet. CONSTITUTION: The controller comprises a memory, a first FIFO(first-in, first-out) for managing transmission of CPU(central processing unit) data in a CPU, a second FIFO for managing transmission of the CPU data from the memory to an ethernet, and an arbiter for controlling the first and the second FIFOs. The controller controls data transmission between a station having the CPU and the ethernet.

Description

Address generation and data path adjustment to and from the SRM to coordinate multiple transport packets

A local area network ("LAN") is a limited geographic area description, such as a personal computer, workstation, file server, relay device, data terminal equipment ("DTE"), and an office, building, or cluster of buildings to communicate information electronically with each other. Communication system that enables such other information processing equipment located. Each part of the information processing equipment in the LAN communicates with other information processing equipment in the LAN according to a fixed protocol (or standard) that defines network operations.

The International Organization for Standardization Open Systems Interconnection Basic Reference Model defines a seven-layer model for data communication within a LAN. The lowest layer of the model is the physical layer of modules, which module comprises: (1) a physical medium capable of interconnecting network nodes and transmitting data electronically, (2) a manner in which network nodes interface to physical transmission media, ( 3) specify the process of delivering data over the physical medium, and (4) the protocol of the data stream.

IEEE Standard 802.3, Carrier Sense Multiple Access / Collision Detection (CSMA / CD) approach and physical layer specification is one of the standard specifications for the most widely used physical layer. IEEE Standard 802.3, commonly referred to as Ethernet, addresses data transfer over coaxial or twisted pair cables, which are typically more expensive than twisted-pair cables. The 10 Base-T protocol of IEEE Standard 802.3 specifies a rate of 10 megabits per second ("Mbps") for transferring data over twisted pair cable.

In the drawings, FIG. 1 shows that a prior art system 10 having a workstation, personal computer, file server, data terminal equipment, or such other information processing equipment, represented by CPU 12, is an Ethernet 22 or media independent interface. It is connected to data communication equipment of another type indicated by 24. In FIG. 1, an Ethernet controller 14, commonly known as a network interface controller, is located between the CPU 12 and the advent (and outgoing) Ethernet 22 lines. Typically, the Ethernet 22 connection consists of two pairs of twisted pair copper cables, the advent pair referred to as (10R) and the outflow pair referred to (10T).

The Ethernet controller 14 controls the transmission of outgoing data to the outgoing pair or cable and the receipt of the incoming data from the coming pair or cable. For example, before being provided to an outflow pair or cable, the outflow data is Manchester encoded to reduce electromagnetic interference. Manchester encoding causes some portion of the data stream to pulse at 10 MHz and other portions of the data stream to pulse at 5 MHz.

As data throughput increases, the need to deliver more information at higher speeds has to be extended to data rates considerably higher than the 10 Mbps rates specified in the 10 Base-T protocol. As a result, there is a 100 base-TX protocol that extends the IEEE standard 802.3 to handle data traveling at an efficient data rate of 100 Mbps over twisted pair cables in existing systems. There are situations where it is desirable for a physical transmission medium to be able to handle data delivered over twisted pair cable at 100 base-TX rates and low 10 base-T rates. Currently, it supports PCI speeds of 33 MHz on the internal PCI bus and Ethernet speeds of up to 25 MHz for 100 M bits per second operation, enabling pre-operation dual mode with an interpacket gap of 9.6 microseconds. There is a need to support.

In addition to the problems associated with data transfer at different rates over an Ethernet or media independent interface, problems related to the variable data coordination capabilities of personal computers, workstations, file servers, relays, data terminal equipment, and such other information processing equipment. There is this. For example, in a personal computer system, there may be other equipment or duty that the CPU 12 should pay attention to in addition to the reception or transmission of data via the Ethernet 22.

The Ethernet controller 14 controls the transfer of data from the CPU 12 to the Ethernet 22. One of the major problems facing the Ethernet controller 14 is that different memory elements of the various components have different sizes. For example, there is a need to keep the semiconductor device as small as possible. For this reason, it is advantageous to have a bus size as small as possible without degrading the performance of the device. As can be seen, it is desirable to design a component with a 16-bit bus if the 16-bit bus is half the size of the 32-bit bus and the 16-bit bus can provide the same performance as the 32-bit bus. In addition, the smaller the bus size, the less likely there is a manufacturing defect in the bus.

In Fig. 2, different size parts are described. SRAM 16 is a 16-bit memory device, data bus 20 is a 16-bit data bus, and PCI bus 18 is typically a 32-bit bus. There is now a 64-bit PCI bus, and all future computer systems can have a 64-bit PCI bus as a standard bus size. The SRAM 16 is used as a buffer by the Ethernet controller 14 so that there is no delay in transferring data from the Ethernet 22 to the CPU 12 or from the CPU 12 to the Ethernet 22. . Such a delay is caused, for example, by high latency of the CPU 12 or by a collision on the Ethernet 22 where the transmitting station retransmits the information just sent. Various FIFOs, BX FIFOs 26, MX FIFOs 28, BR FIFOs 30, and MR FIFOs 32 control the transfer of data between various components. For example, the BX FIFO 26 receives data from the CPU 12 via the PCI BUS 18 and changes the format from 32 bits to 16 bits to the SRAM 16 via the 16 bit data bus 20. Can be sent. In addition, an address needs to be created by the BX FIFO 26 and the MR FIFO 32 so that the information is located in the SRAM 16 and efficiently retrieved by the MX FIFO 28 and the BR FIFO 30, respectively. The MX FIFO 28 and BR FIFO 30 change the 16-bit format received from the SRAM 16 into a 32-bit format.

In addition, when the data needs to be transmitted through the Ethernet 22, the data needs to be received, and when the data needs to be transmitted to the CPU 12, the Ethernet controller 14 causes the CPU 12 to receive the data. Since there is a possibility that there is a need to receive data from, the Ethernet controller 14 needs to make an intelligent selection, for which data is transmitted or received first, in which sequence the next data is transmitted or received.

Efficiently change the size of data from 32 bits to 16 bits for storage in memory devices, address generation method for 16-bit data to be stored in SRAM, efficiently size data from 16 bits to 32 bits for retrieval from SRAM A method of generating an address for retrieved 32-bit data and a method of adjusting between various write and read functions controlled by an Ethernet controller are required.

Summary of the Invention

According to the present invention, there is provided an Ethernet controller for controlling data transmission between a station and Ethernet. The Ethernet controller includes four logical FIFOs that manage the transfer of data from the station CPU to the buffer memory and from the buffer memory to the station CPU. The Ethernet controller includes an arbiter that adjusts the FIFO to prioritize the transmission of data.

The logic associated with each FIFO converts the bit size of the data from the first bit size to the second bit size and generates an address for writing or reading to or from the buffer memory. The logic also converts the 16-bit address into two 8-bit portions and also the two 8-bit portions into the original 16-bit address for communicating over an 8-bit address bus.

The arbitr limits each FIFO to 32 byte transfers per request, and polls another FIFO to determine if there is a pending request for transmission after each 32 byte transfer. The arbiter allows requests for each tuning algorithm.

Each FIFO has a selection size chosen to maximize the performance of the Ethernet controller.

The invention is further understood by the following detailed description with reference to the accompanying drawings. As will be apparent to those skilled in the art from the following description, the preferred embodiments of the present invention are described in the best mode for carrying out the present invention. As will be realized, the invention may be of different embodiments, the details of which may vary within the scope of the invention. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature and not as restrictive.

FIELD OF THE INVENTION The present invention generally relates to methods and elements for controlling the transmission of information to and from the ethernet by means of stations, in particular methods and elements for increasing the information transmission capability, and more particularly to data in a first bit width. To a second bit width, to generate an address for the converted data, and to adjust access to the data path for read and write access to and from the SRAM buffer.

The accompanying drawings included in the specification are intended to explain the invention and to explain the principles of the invention.

1 is an overview of a prior art system having an Ethernet controller and a CPU in accordance with an Ethernet connection and a media independent interface connection.

2 shows a system according to the invention.

3 is a detailed view of the Ethernet controller.

4 illustrates a tuning algorithm used with an Ethernet controller to adjust the sequence of read and write accesses.

5 illustrates how different bit size data is located in different size memory locations.

6 illustrates an address generation method for writing data to an SRAM buffer memory.

7 illustrates an address generation method for retrieving data from an SRAM buffer memory.

details

In FIG. 1, an overview of a prior art system 10 having a CPU 12 and an Ethernet controller 14 with a connection Ethernet 22 and a media independent interface 24 is shown. The CPU 12 is connected to the Ethernet controller 14 by the bus 17.

In Fig. 2 a system 11 according to the invention is shown. In the drawings, like numerals denote like elements. A portion of the Ethernet controller 14 is shown in FIG. The Ethernet controller 14 has many functions different from those of the present invention, and only components belonging to the present invention will be described.

The function of the described portion of the Ethernet controller 14 is to manage the transfer of data to and from the Ethernet 22 and / or media independent interface 24. The Ethernet controller 14 manages data transfer by using the SRAM 16 as a buffer to prevent deceleration of data transfer to and from the CPU 12 or the Ethernet 22 or media independent interface 24. . There are a number of reasons why the transfer of data may be slowed down, for example, the CPU 12 has a long wait time, and the data transfer from the Ethernet 22 will continue until the CPU 12 escapes from another interrupt. It is time to stop. Conversely, the CPU 12 attempts to transfer data through the Ethernet 22, and the Ethernet 22 causes the data from the CPU 12 to stop when in use, or there is no Ethernet 22. Keep until you lose.

To solve the problems caused by the inability to complete the transmission or reception of information, the Ethernet controller 14 has four FIFOs, each of which has a selection size that will maximize the performance of the Ethernet controller 14. . BX FIFO 26 is a 180 byte FIFO, MX FIFO 28 is a 112 byte FIFO, BR FIFO 30 is a 160 byte FIFO, and MR FIFO 32 is a 108 byte FIFO. The BX FIFO 26 and BR FIFO 30 are on the BUS side of the Ethernet Controller 14, and the MX FIFO 28 and MR FIFO 32 are the MAC (Media Access Control) of the Ethernet Controller 14. Is on. Each of the FIFOs manages input or output functions. The BX FIFO 26 manages the transfer of data from the CPU 12 to the SRAM 16. The MX FIFO 28 manages the transfer of data from the SRAM 16 to the Ethernet 22 or media independent interface 24. Similarly, MR FIFO 32 manages the transfer of data from Ethernet 22 or media independent interface 24.

In Fig. 3, the Ethernet controller 14 is shown in more detail. Each of the four FIFOs described in connection with FIG. 2 includes or is coupled to a logical block. The BX FIFO 26 is coupled to the BX logic 34, which generates an address for the SRAM 16 and sends it from the CPU to the SRAM 16 via the 16-bit data path 20. Preparing 32-bit data, MX FIFO 28 is coupled with MX logic 36, MX logic 36 generates an address for the 16-bit data retrieved from SRAM 16, and 16 in SRAM 16. Read bit data, convert 16 bit data retrieved from SRAM 16 into 32 bits, and write 32 bit data to MX FIFO 28. The MR FIFO 32 is coupled with the MR logic 38, which converts the data received by the MR FIFO 32 into the 16-bit size in the Ethernet 22 and into the SRAM 16. Generates an address for 16-bit data that can be written, and the BR FIFO 30 is coupled with the BR logic 40 and the BR logic 40 stores data in the SRAM 16 received at the Ethernet 22. It reads, changes data from 16 bit size to 32 bit size, and writes 32 bit size data in BR FIFO 30, in which the data is transferred to CPU 12.

The SRAM controller 42 controls four FIFOs, and in the event of a conflict, that is, when one or more FIFOs request the bus to transmit data, the SRAM controller 42 has the FIFOs prioritized in any order. Adjust according to the intended algorithm for determining behavior. This algorithm is described below.

The overall operation of the system shown in FIG. 3 is as follows. The Ethernet controller 14 is responsible for the overall operation of the data transfer from the CPU 12 to the Ethernet 22 and the transfer of the data from the Ethernet 22 to the CPU 12. As mentioned above, one of the major problems with the transmission of data to and from Ethernet 22 is that there are a number of factors that can affect the efficient transmission of any such data. One factor is the different speeds that must be adjusted. PCI bus 18 operates at a rate of 33 MHz, and Ethernet 22 operates at a maximum rate of 25 MHz during 100 M bit operation supporting full duplex operation in an interpacket gap of 0.96 microseconds. One of the main functions of the Ethernet controller 14 is to manage the transmission of data between the various elements in a manner that minimizes any delay in receiving or transmitting such data. For example, when CPU 12 (not shown) wishes to send data to Ethernet 22, it communicates with BX FIFO 26 to send data to BX FIFO 26. BX FIFO 26 requests access to the bus from SRAM controller 42 via BX request line 44. When the BX logic 34 receives a grant from the SRAM controller 42 via the BX control line 46, the BX logic 34 receives 16 bits of 32-bit size data received from the CPU 12. Change to size data and generate an address for SRAM 16 for storage of data in 16-bit format. The converted data is communicated with the SRAM 16 via the 16 bit bus 20 and written therein. The BX logic 34 is a state machine that controls the flow of data from the BX FIFO 26 to the SRAM 16 and operates when receiving a permission signal from the SRAM controller 42. Since the BX FIFO 26 is 32 bits and the data bus 20 is 16 bits, 16 bits size data is written to the SRAM 16 when only 16 bits can be written on the 16 bits size data bus in each cycle. Take two cycles of BX logic 34 to write. It is determined that data transmission through the BX FIFO 26 is maximized. That is, any delay in the transmission of data through the BX FIFO 26 is minimized by having the size of the BX FIFO 26 at 180 bytes. As described below, the SRAM controller 42 manages the reception and transmission of data through all FIFOs, including the BX FIFO 26, in accordance with a tuning algorithm that maximizes the performance of the system 11.

The size of the SRAM 16 is selectable, and in this embodiment it has been selected as 64 K bytes, but can be extended to at least 128 K bytes. Thus, it is necessary to have 16 bits of address to access each memory location. However, the Ethernet controller 14 has only 8 bits of the address port to save space and make the cost more efficient. For this reason, the 16 bit address is divided into an upper 8 bit portion and a lower 8 bit portion, transmitted over an 8 bit address bus, and reassembled into a 16 bit address outside the Ethernet controller 14. Details of address generation and transmission are described below with reference to FIGS. 6 and 7.

The Ethernet controller 14 communicates constantly with the Ethernet network via the MX FIFO 28, and depends on some type of protocol, and the system determines when it is transmitted over the data Ethernet 22. When data is sent over Ethernet 22, MX FIFO 28 requests access to data bus 20 from SRAM controller 42 via MX request line 47. When access is allowed and communicated with the MX logic 36 via the MX control line 48, data written temporarily in the SRAM 16 or in the MX FIFO 28 is stored by the BX FIFO 26 by the CPU. As received from 12, it is converted to the original 32-bit type and transmitted by MX FIFO 28 via Ethernet 22. The MX FIFO 28 is a state machine that operates upon controlling the data flow from the SRAM 16 to the MX FIFO 28 and receiving a permit signal from the SRAM controller 42. Since MX FIFO 28 is 32 bits and data bus 20 is 16 bits, MX logic 36 reads 16 bits of data twice and assembles them into double words (32 bits) using logic. Later, a write signal is provided to the MX FIFO 28. This means that it is written to MX FIFO 28 every optional cycle and read from SRAM 16 every cycle. The MX FIFO 28 controls reading from the SRAM 16 and writing to the MX FIFO 28.

Upon sensing whether there is information from the Ethernet to be received, the MR FIFO 32 requests access from the SRAM controller 42 to the data bus 20 via the MR request line 50. do. When the SRAM controller 42 allows access via the MR control line 52, the data received by the MR FIFO 32 is converted by the MR logic 38 into a 16-bit format, which results in a 16-bit data bus. Transferred to SRAM 16 via 20. The operation of MR logic 38 is similar to the operation of BX logic 34 described above.

When the CPU is ready to receive data received from the Ethernet, the BR FIFO 30 requests access from the SRAM controller 42 to the data bus 20 via the BR request line 54. When access is allowed, the SRAM controller 42 communicates with the BR logic 40 that reads data from the SRAM 16, converts the data stored in the 16-bit data format to the 32-bit data format, and Is forwarded to the BR FIFO 30, which in turn sends data to the CPU. The operation of the BR logic 40 is similar to the operation of the MX logic 36 described above.

In FIG. 4, an adjustment algorithm 56 (FIG. 4) is shown that indicates in which order the SRAM controller 42 adjusts the request for the bus when there are multiple requests at the same time. The SRAM controller 42 uses the adjustment scheme shown in FIG. 4 to coordinate the requests in all four logic blocks.

In addition, the present invention suggests that there is an optimal number of bytes transferred between the elements in the Ethernet controller 42. This optimal number of bytes was determined to be approximately 32. This means, for example, that 32 bytes of data are assembled in the BX FIFO 26 before being requested by the BX FIFO 26 for the bus (the only exception is that the last byte to be delivered is in the BX FIFO 26). When it is detected). In addition, it has also been determined that 32 bytes is the optimal number of bytes to be transferred from one device to the next. In this case, when the limit of 32 bytes has been reached, the system stops sending or receiving and polls other functions to determine if there is any other information that needs to be sent or received.

In FIG. 4, in the first case where there are multiple requests at the same time and the system is in the idle state 58, the system is directed to the first receiving side 60 and accessing the first MAC side receiving unit 62. Allow. If there is no pending request at 62, the system proceeds to the transmitting side 64, and if there is a pending request at the bus transmitting unit 66, the access is allowed to the bus transmitting unit. If there is no request pending at the bus transmitter, the system withdraws and proceeds to the receiver 60, allowing access to the bus receiver 68. If there is no pending request at 68, the system then directs to the transmitter 64 and then to the MAC transmitter 70.

If the system stops to poll another function to determine if there is a hold request for the data bus, the system allows the hold request in the same order as described above. In Fig. 5, a method is described in which the visor size data is stored in various elements in the system. A small portion of the BX FIFO 26 is shown with five bytes (D0-D4) of data stored in the FIFO in the locations indicated by 72 and 74. Further, 32 bits of STATUS data stored as 8-bit bytes S0 to S3 in the position indicated by 76 are shown. Thirty-two bits of DESCRIPTOR data stored as eight-bit bytes in the memory location indicated by 78 are shown. The BX logic 34 reads 32 bit data from the BX FIFO 26, converts it into 16 bit size at 80, and the 16 bit data is written into the SRAM 16 and recorded as shown. The first memory location 82 contains two 8-bit bytes, reserved by the system and labeled EOP0 and EOP1, which are associated with where the packet end-of-packet is located. Information, that is, information in which memory location data byte D4 is located. The second memory location 84 is also reserved by the system and is located in two 16-bit memory locations 88 and 90 which in this example read HEX10 in the upper byte position and HEX00 in the lower byte position. Following the STATUS data, the information memory location is four 8-bit bytes of the DESCRIPTOR data DA0 to DA3 located in the memory locations 92 and 94.

When MX FIFO 28 allows access to data bus 20 as described above, 16 bit data is read from SRAM 16, converted to 32 bit data at 96, and MX FIFO 28 Forward).

The foregoing is from the bus side to the MAC side of the Ethernet controller 14, i.e., in the CPU 12 (not shown), the BX FIFO 26, the SRAM 16, the MX FIFO 28, and the Ethernet 22. ) Is for the transfer of data. The same description as described above is applicable when data is received at MR FIFO 32, transmits SRAM 16, read by BR FIFO 30, and transmitted to CPU 12.

In Fig. 6, the method of address generation when data is written into the SRAM 16 is described. The address generator of the BX logic 26 is shown in the dotted line 98, and is also within the address generator of the MR logic 38 (FIG. 3). The address generation method for the SRAM 16 begins with the BX write pointer 100 pointed at the memory location where the next bit of information is written. At the beginning of the packet to be written into memory, the starting memory location is stored in the register starting packet pointer 102. Thus, the start packet pointer 102 holds the address at a memory location in the SRAM 16 where the BX logic 26 begins to write the packet. The starting memory location is written to the memory location at the end of the packet. Since the 16 bit address must be communicated via an 8 bit address bus, the 16 bit address is divided into two 8 bit portions. In order to generate an address when data is recorded, it is necessary to increase the lower 8 bits of the address when each byte is written. Each time a page is written, i.e., when the lower 8 bits read HEXFF, the upper 8 bits portion is incremented. Thus, the BX write pointer 100 has an increment lower input 104 that increments the BX write pointer 100 each time a byte is written into the SRAM 16, and the increment upper input 106 causes a new page to be started. Each time, that is, the BX write pointer 100 is incremented after the lower address byte reaches the value HEXFF. The BX write pointer 100 then contains the 16 bit address of the memory location where the just written byte is written. Since the 16 bit address is communicated via an 8 bit address bus, the MUX 108 reformats the 16 bit address into an upper 8 bit portion and a lower 8 bit portion, wherein the 8 bit portion is 8 bits indicated by (110). It communicates with the SRAM 16 via a bus, a portion of which is shown in dashed line 112. SRAM 16 at 114 converts the two 8-bit address portions to 16-bit addresses 116. When the end of the packet is written into the SRAM 16, the memory location where the end of the packet is recorded is written into the start memory location recorded in the start packet pointer 102.

In Fig. 7, the read address generator shown in dotted line 124 of the MX logic 36 for generating a read address for reading data from the SRAM 16 is shown. The read pointer 126 of the portion of SRAM 16 (shown in dashed line 127) points to the 16-bit memory location where the byte just read is located. The 16 bit memory location is converted into two 8 bit portions to be located on the 8 bit address bus, indicated by 130 by MUX 128. Two 8-bit address portions are received by MX logic 36 and reassembled to 16-bit address 134 by flip-flop 132.

The foregoing description of the preferred embodiment of the present invention is merely illustrative, and the present invention is not intended to be limiting. Modifications or variations are possible in light of the above teachings. The embodiments have been selected and described in order to provide a best description of the principles and practical applications of the invention to enable those skilled in the art to make and use the invention in various modifications and in various embodiments suitable for a particular use. All such variations and modifications are possible within the scope of the invention as determined by the appended claims.

Claims (19)

In an Ethernet controller for controlling the transfer of data between a station having a CPU and an Ethernet, Memory, A first FIFO for managing the transfer of memory CPU data from the CPU, A second FIFO for managing transfer of CPU data from memory to Ethernet, and And an arbiter for controlling the first and second FIFOs. The method of claim 1, First logic coupled to the first FIFO for converting CPU data from a first bit size to a second bit size and generating an address for writing the second bit size of CPU data into memory; And a second logic coupled to the second FIFO to generate an address for reading CPU data in the memory and to convert the data from a second bit size to a first bit size. Controller. The method of claim 2, A third FIFO that manages the transfer of Ethernet data from Ethernet to memory, and And a fourth FIFO for managing the transfer of Ethernet data from memory to the CPU, wherein the arbiter controls the third and fourth FIFOs. The method of claim 3, wherein Third logic coupled to the third FIFO for converting Ethernet data from a first bit size to a second bit size and generating an address for writing the second bit size of Ethernet data into memory; And a fourth logic coupled to the fourth FIFO, generating an address for reading the Ethernet data in the memory and converting the Ethernet data from a second bit size to a first bit size. Ethernet controller. The method of claim 4, wherein The arbiter comprises means for limiting transmissions over each FIFO to a selected number of bytes. The method of claim 5, And the selected number of bytes is 32 bytes. The method of claim 6, The arbiter comprises means for including each FIFO after 32 bytes of transmission to determine if a request for transmission is pending. The method of claim 7, wherein The arbiter permits a request from a FIFO according to an adjustment algorithm. The method of claim 8, The coordination algorithm allows priority at the first level to access the receive FIFO, and between receive FIFOs, the coordination algorithm allows priority for the receive FIFO according to the hold request on the media access side of the Ethernet controller. The coordination algorithm allows a second priority at the first level to the transmit FIFO, and the coordination algorithm between the transmit FIFOs allows priority for the transmit FIFO according to the hold request on the bus side of the Ethernet controller. Ethernet controller. The method of claim 9, And wherein the first FIFO has a first selected size. The method of claim 10, And wherein the second FIFO has a second selected size. The method of claim 11, And wherein the third FIFO has a third selected size. The method of claim 12, And wherein the fourth FIFO has a fourth selected size. The method of claim 13, And the first selected size is 180 bytes. The method of claim 14, And said second selected size is 112 bytes. The method of claim 15, And said third selected size is 108 bytes. The method of claim 16, And said fourth selected size is 160 bytes. The method of claim 17, And first means for reformatting a 16 bit address into a first 8 bit portion and a second 8 bit portion for transmission over an 8 bit address bus. The method of claim 18, And second means for reformatting the first and second eight bit address portions to sixteen bit addresses after being transmitted over an eight bit address bus.