KR100474658B1 - Address generation and data path arbitration to and from sram to accommodate multiple transmitted packets - Google Patents

Abstract

An Ethernet controller is disclosed that controls the transfer of data between the station and the Ethernet, which has four FIFOs that manage the transfer of data between the station CPU, the memory buffer, and the Ethernet. Each of the four FIFOs has a size selected to maximize the performance of the controller. The controller includes a coordinator that adjusts which outstanding requests from each of the FIFOs will take priority. This controller limits the transfer of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data from the first bit size format to the second bit size format. The controller also includes logic to convert the 16 bit address into two 8 bit portions for transmission over an 8 bit address bus, and logic to reformat the two 8 bit portions into a 16 bit address.

Description

ADDRESS GENERATION AND DATA PATH ARBITRATION TO AND FROM SRAM TO ACCOMMODATE MULTIPLE TRANSMITTED PACKETS

The present invention relates generally to a method and apparatus for controlling the transmission of information between an ethernet and a station, and more particularly to a method and apparatus for increasing the transmission performance of information. More specifically, the present invention converts data from a first bit width to a second bit width, generates addresses for the converted data, and for a data path for write or read access to / from an SRAM buffer. A method and apparatus for coordinating access.

Local Area Networks (“LANs”) are personal computers, workstations, file servers, repeaters, data terminal devices (“DTEs”), and others, within a limited geographic area such as a workplace, building, or cluster of such buildings. A communication system that enables information processing apparatuses to transmit information electronically to each other. Each information processing device in the LAN communicates with other information processing devices in the LAN according to a fixed protocol (or standard specification) that defines the operation of the network.

The interconnect basic reference model of ISO's open systems defines a seven-layer model for data communication in the LAN. The lowest layer of the model is the physical layer. This physical layer is (a) a path through which data is transmitted electronically, a physical medium that connects network nodes to each other, (b) how the network nodes interface with a physical transmission medium, and (c) a physical transmission medium. A process of transmitting data, and (d) modules characterizing the protocol of the data stream.

IEEE Standard 802.3, Carrier Detection Multiple Access Collision Detection (CSMA / CD) access method and physical layer specification are one of the most widely used standards for the physical layer. IEEE standard 802.3, commonly called Ethernet, deals with the transmission of data over twisted pair cables or coaxial cables that are more expensive than these twisted pair cables. The 10Base-T protocol of IEEE Standard 802.3 specifies a data transfer rate of 10 Mbps over twisted pair cables.

Referring to the drawings, FIG. 1 illustrates how the prior art system 10 having a workstation, a personal computer, a file server, a data terminal device, or other information processing device, represented by the CPU 12, or the Ethernet 22, or It is connected to other types of data communication devices represented by a media independent interface 24. In FIG. 1, an Ethernet controller 14, also commonly known as a network interface controller, is located between the power line (and output) lines of the CPU 12 and the Ethernet 22. Typically, the connection of Ethernet 22 consists of two pairs of twisted pair copper cables, an input pair referred to as 10R and an output pair referred to as 10T.

The Ethernet controller 14 controls the transmission of output data to the output pair or output cable and the reception of input data from the input pair or input cable. For example, output data is Manchester encoded to reduce electromagnetic interference before being provided to an output pair or output cable. By this Manchester encoding, part of the data stream is pulsed at 10 MHz and other parts of the data stream are pulsed at 5 MHz.

The constant need to transfer more data faster and the need to increase data processing performance requires expansion to data rates considerably higher than the 10 Mbps rate specified by the 10Base-T protocol. . As a result, there is a 100Base-TX protocol that extends IEEE standard 802.3 to cope with data traveling at effective transmission rates of 100 Mbps over twisted-pair cables in current existing systems. It is sometimes desirable for a physical transmission medium to be able to process data transmitted over twisted pair cables at both 100Base-TX speeds and later 10Base-T speeds. Currently, to support full-duplex mode operation with an interpacket gap of 9.6 microseconds, it is necessary to support PCI speed of 33 MHz on the internal PCI bus and Ethernet speed of up to 25 MHz for 100 Mbps operation. There is.

In addition to the problems associated with transferring data at different speeds via an Ethernet or media independent interface, the data processing capabilities of personal computers, workstations, file servers, repeaters, data terminal devices, and other such information processing devices may be compromised. Problems arise with regard to change. For example, in a personal computer system, the CPU 12 must handle other devices or duties in addition to receiving or transmitting data via the Ethernet 22.

The Ethernet controller 14 controls the transfer of data from the CPU 12 to the Ethernet 22. One of the main problems faced by the Ethernet controller 14 is that different memory devices of various components have different sizes. For example, semiconductor devices need to be kept as small as possible. Accordingly, it is advantageous to make the size of the bus as small as possible without degrading the performance of the device. As can be appreciated, a 16 bit bus is half the size of a 32 bit bus. If such a 16-bit bus can provide the same performance as a 32-bit bus, it is desirable to design that part as a 16-bit bus. Also, the smaller the bus size, the less defects there are in the bus.

2 shows components of different sizes. SRAM 16 is a 16-bit memory device, data bus 20 is a 16-bit data bus, and PCI bus 18 is typically a 32-bit bus. Although there is now a 64-bit PCI bus, all future computer systems will have a 64-bit PCI bus as the standard bus size. The SRAM 16 is used as a buffer by the Ethernet controller 14 to prevent a delay in transferring data from the Ethernet 22 to the CPU 12 or from the CPU 12 to the Ethernet 22. prevent. This delay can be caused, for example, by a long wait time in the CPU 12 or by a collision on the Ethernet 22 (by which the transmitting station must retransmit the information just sent). . Various FIFOs, such as BX FIFO 26, MX FIFO 28, BR FIFO 30, and MR FIFO 32, control the data transfer between the various components. For example, the BX FIFO 26 may receive data from the CPU 12 via the PCI bus 18 and then transfer the format of this data to the SRAM 16 via the 16-bit data bus 20. Switch from 32 bits to 16 bits so that. In addition, the BX FIFO 26 and the MR FIFO 32 are required to locate addresses in order for the information to be placed in the SRAM 16 and efficiently retrieved from the SRAM 16 by the MX FIFO 28 and the BR FIFO 30, respectively. Should be created. The MX FIFO 28 and BR FIFO 30 convert the 16-bit format received from the SRAM 16 into a 32-bit format.

In addition, it may be necessary to receive the data and at the same time it may be necessary to transmit the data via the Ethernet 22, while the Ethernet controller 14 needs to receive the data from the CPU 12 and at the same time the CPU 12 Since it may be necessary to transmit data in a network, the Ethernet controller 14 needs to intelligently select which data will be transmitted or received first, and in what order subsequent data will be transmitted or received. .

How to efficiently change the size of data from 32 bits to 16 bits for storage in a memory device, How to generate addresses for 16 bit data to be stored in SRAM, Efficiently size data from 16 to 32 bits to retrieve from SRAM And a method of generating addresses for retrieved 32-bit data, and a method of performing an adjustment between the various write and read functions controlled by the Ethernet controller.

EA-A-150 084 discloses a network controller for controlling data transfer between a network and a CPU, which includes a memory, a FIFO for managing the transfer of data, and an arbiter for controlling this FIFO. However, this does not disclose for Ethernet networks.

The accompanying drawings, which are incorporated in and form a part of the invention, together with the description, explain the principles of the invention.

1 is an overview of a prior art system having an Ethernet controller coupled to an Ethernet and media independent interface, and a CPU.

2 illustrates a system taught by the present invention.

3 is a detailed view of the Ethernet controller.

4 shows a tuning algorithm used by the Ethernet controller to adjust the order of read and write accesses.

5 shows how data of different bit sizes are located in memory locations of different sizes.

6 shows a method of generating an address for writing data to an SRAM buffer memory.

7 shows a method of generating an address for retrieving data from an SRAM buffer memory.

Example

1 is an overview of a prior art system 10 having an Ethernet controller 14 connected to an Ethernet 22 and a media independent interface 24, and a CPU 12. CPU 12 is connected to Ethernet controller 14 by bus 17.

2 shows a system 11 according to the invention. In the drawings, like numerals represent like components. A portion of the Ethernet controller 14 is shown in FIG. As will be appreciated, the Ethernet controller 14 has many other functions than those taught by the present invention, but only the functions related to the present invention are described herein.

The function of the illustrated portion of the Ethernet controller 14 is to manage the transmission of data to / from the Ethernet 22 and / or the media independent interface 24. The Ethernet controller 14 uses the SRAM 16 as a buffer to transfer data to and from the CPU 12 or the Ethernet 22 or the media independent interface 24 to slow down. Manage. There are various reasons for the slow data transfer, for example, the CPU 12 may have a long wait time and the Ethernet 22 until the CPU 12 is free from other interrupts. The transfer of data is slowed down because the transfer of data from < RTI ID = 0.0 > Conversely, the data from the CPU 12 may not be used when the CPU 12 attempts to transfer data through the Ethernet 22, so that data from the CPU 12 may be used. It is stopped or held until it is finished.

To solve problems caused by the inability to complete the transmission or reception of information, the Ethernet controller 14 has four FIFOs, each of which is selected to maximize the performance of the Ethernet controller 14. Has a size. BX FIFO 26 is a 180 byte FIFO, MX FIFO 28 is a 112 byte FIFO, BR FIFO 30 is a 160 byte FIFO, and MR FIFO 32 is a 108 byte FIFO. The BX FIFO 26 and BR FIFO 30 are on the BUS side of the Ethernet Controller 14, and the MX FIFO 28 and MR FIFO 32 are on the MAC (Media Access Control) side of the Ethernet Controller 14 Is in. Each of the FIFOs manages an input function or an output function. The BX FIFO 26 manages the transfer of data from the CPU 12 to the SRAM 16. The MX FIFO 28 manages the transfer of data from the SRAM 16 to the Ethernet 22 or the media independent interface 24. Similarly, MR FIFO 32 manages the transfer of data from Ethernet 22 or media independent interface 24.

3 shows the Ethernet controller 14 in more detail. Each of the four FIFOs described in connection with FIG. 2 includes or is coupled to a logical block. The BX FIFO 26 is coupled to the BX logic 34, which generates addresses for the SRAM 16, and from the CPU 12 through the 16 bit data path 20 through the SRAM ( 16) Prepare 32-bit data to be transferred. MX FIFO 28 is coupled to MX logic 36, which generates the addresses for the 16 bit data to be retrieved from SRAM 16, and reads the 16 bit data in SRAM 16. The 16-bit data retrieved from the SRAM 16 is converted into 32 bits, and the 32-bit data is recorded in the MX FIFO 28. The MR FIFO 32 is coupled to the MR logic 38, which converts the data received by the MR FIFO 32 from the Ethernet 22 into a 16 bit size, and the SRAM 16 Generate addresses for the 16-bit data to be written. The BR FIFO 30 is coupled to the BR logic 40, which reads the data in the SRAM 16 received from the Ethernet 22 and converts the data into 32 bits in a 16 bit size. After changing to the size, this 32-bit size data is recorded in the BR FIFO 30. This 32-bit size data is transferred from the BR FIFO 30 to the CPU 12.

SRAM controller 42 controls four FIFOs. If a collision occurs, that is, if one or more FIFOs require access to the bus to transfer data, then the SRAM controller 42 is in what order. Adjust this situation according to some algorithm that determines whether the FIFO will have priority. This algorithm is described below.

The overall operation of the system shown in FIG. 3 is as follows. The Ethernet controller 14 manages the overall operation of the transfer of data from the CPU 12 to the Ethernet 22 and the transfer of the data from the Ethernet 22 to the CPU 12. As described above, one of the major problems in the transmission of data to and from Ethernet 22 is that there are a number of factors that can affect the transmission of such arbitrary data. One factor is the need to cope with different speeds. PCI bus 18 operates at a rate of 33 MHz, and Ethernet 22 operates at up to 25 MHz for 100 Mbps operation supporting full duplex operation with an inter-packet interval of 9.6 microseconds. One of the main functions of the Ethernet controller 14 is to manage the transmission of data between the various components in a manner that minimizes all delays in receiving or transmitting such data. For example, if CPU 12 (not shown) wants to send data to Ethernet 22, this CPU 12 communicates with BX FIFO 26 to send data to this BX FIFO 26. do. The BX FIFO 26 requests access to the bus from the SRAM controller 42 via the BX request line 44. When the BX logic 34 receives a grant from the SRAM controller 42 via the BX control line 46, the BX logic 34 receives 16 bits of 32-bit data received from the CPU 12. After changing to size data, addresses for SRAM 16 are generated to store this 16-bit format data. The converted data is transferred to the SRAM 16 via the 16 bit bus 20 and written therein. The BX logic 34 is a state machine that controls the flow of data from the BX FIFO 26 to the SRAM 16 and operates when a permission signal is obtained from the SRAM controller 42. The BX FIFO 26 is 32 bits wide and the data bus 20 is 16 bits wide. Accordingly, since only 16 bits can be written on the 16-bit data bus between each, two cycles are required for the BX logic 34 to write 16-bit size data to the SRAM 16. . When the BX FIFO 26 has a size of 180 bytes, it has been found that data transmission through this BX FIFO 26 is maximized, that is, all delays in data transmission through the BX FIFO 26 are minimized. As described below, the SRAM controller 42 manages the reception and transmission of data through all FIFOs, including the BX FIFO 26, in accordance with a tuning algorithm that maximizes the performance of the system 11.

The size of the SRAM 16 is selectable, although in this embodiment it has been chosen to be 64 kilobytes, it may extend to at least 128 kilobytes. Thus, in order to access each memory location, it is necessary to have a 16-bit address. However, the Ethernet controller 14 has only 8 bit address ports to save space and make it more cost effective. For this reason, the 16 bit address must be divided into an upper 8 bit portion and a lower 8 bit portion, transmitted over an 8 bit address bus, and then reassembled into a 16 bit address outside of the Ethernet controller 14. Details of address generation and transmission are described below with reference to FIGS. 6 and 7.

The Ethernet controller 14 is always in communication with the Ethernet network via the MX FIFO 28 so that, depending on the type of protocol used, the system determines when data can be transmitted over the Ethernet 22. . Once the data can be transmitted over Ethernet 22, MX FIFO 28 requests access to data bus 20 from SRAM controller 42 via MX request line 47. When access is granted and sent to the MX logic 36 via the MX control line 48, data written to the SRAM 16 temporarily or in the MX FIFO 28 is transferred from the CPU 12 to the BX FIFO 26. Converted to the original 32-bit form received by < RTI ID = 0.0 > and transmitted via < / RTI > The MX FIFO 28 is a state machine that controls the flow of data from the SRAM 16 to the MX FIFO 28 and operates upon obtaining a permission signal from the SRAM controller 42. The MX FIFO 28 is 32 bits wide and the data bus 20 is 16 bits wide. Thus, after the MX logic 36 reads the 16 bit data twice and assembles them into double words (32 bits) using logic, a write signal is provided to the MX FIFO 28. This means that writing to the MX FIFO 28 is made every other cycle, and reading from the SRAM 16 is made every cycle. MX FIFO 28 controls reading from SRAM 16 and writing to MX FIFO 28.

If the MR FIFO 32 detects that there is data to be received from the Ethernet, the MR FIFO 32 requests access to the data bus 20 from the SRAM controller 42 via the MR request line 50. do. When the SRAM controller 42 grants access via the MR control line 52, the data received by the MR FIFO 32 is converted by the MR logic 38 into a 16 bit format and then a 16 bit data bus 20 Is transmitted to the SRAM 16 via. The operation of MR logic 38 is similar to the operation of BX logic 34 described above.

When the CPU is ready to receive data received from the Ethernet, the BR FIFO 30 requests access to the data bus 20 from the SRAM controller 42 via the BR request line 54. If access is granted, the SRAM controller 42 communicates with the BR logic 40, which reads data from the SRAM 16 to convert the data stored in the 16-bit data format into the 32-bit data format. After conversion to the BR FIFO (30). The BR FIFO 30 sends this data to the CPU. The operation of the BR logic 40 is similar to the operation of the MX logic 36 described above.

4 shows an adjustment algorithm 56 that indicates in what order the SRAM controller 42 (FIG. 4) processes requests for the bus when there are multiple requests at the same time. SRAM controller 42 processes the requests from all four logical blocks using the algorithmic scheme shown in FIG.

In addition, the present invention teaches that there is an optimal number of bytes that must be transmitted between the components of the Ethernet controller 42. The optimal number of bytes was determined to be about 32. This means, for example, that 32 bytes of data must be assembled within the BX FIFO 26 before a request to the bus is made by the BX FIFO 26 (the only exception is that the last byte to be transmitted is BX When detected within the FIFO 26). In addition, the optimal number of bytes sent from one component to the next was determined to be 32 bytes. When the limit (32 bytes in this case) is reached, the system stops transmitting or receiving and then polls other functions to determine if there is any other information that needs to be sent or received.

Referring back to FIG. 4, in the first case where multiple requests exist simultaneously and the system is in an idle state 58, the system first looks at the receiving side 60 and then the MAC side 62. Grant access to the reception for the first time. If no outstanding request is made at 62, the system goes to the transmitting side 64, and if there is a pending request at bus transmission 66, grants access to the bus transmission. If there is no outstanding request in the bus transmission, the system goes to the receiving side 60 and grants access to the bus receiving 68. If there is no outstanding request at 68, the system looks at the transmitting side 64 and then the MAC transmission 70.

If the system stops to poll other functions to determine whether there are open requests for the data bus, the system grants open requests in the same order as described above. 5 illustrates how byte sized data is stored in various components of the system. At the locations indicated by 72 and 74, a small portion of the BX FIFO 26 is shown with five data bytes D0-D4 stored in the FIFO. Also, at the position indicated by 76, 32 bits of STATUS data S0 to S3 stored in 8 bit bytes are shown. In the memory location indicated by 78, 32 bits of DESCRIPTOR data DA0 to DA3 stored in 8 bit bytes are shown. The BX logic 34 reads 32 bit data from the BX FIFO 26, converts it to 80 to 16 bit size, and then transfers the 16 bit data to the 16 bit data bus 20. This 16-bit data is written into the SRAM 16 as shown. The first memory location 82 is reserved by the system and includes two 8-bit bytes (EOP0 and EOP1), where the end of the packet is located, i.e. in which memory location the data byte D4 is located. Indicates information about where it is located. The second memory location 84 is also reserved by the system and contains two 8-bit bytes, in this example they are HEX10 in the upper byte position and HEX00 in the lower byte position. Memory locations 86 contain data D0 through D4, followed by two 16-bit data followed by memory locations 88 and 90, four eights in memory locations 88 and 90. STATUS data S0 to S3 of the bit byte are located. Following these STAWS data information memory locations, four 8-bit bytes of DESCRIPTOR data DA0 to DA3 located at memory locations 92 and 94 are followed.

When the MX FIFO 28 is granted access to the data bus 20 as described above, 16 bit data is read from the SRAM 16, converted into 96 to 32 bit data, and then to the MX FIFO 28. Is sent.

In the above, from the bus side of the Ethernet controller 14 to the MAC side, that is, from the CPU 12 (not shown) to the BX FIFO 26, the SRAM 16, the MX FIFO 28 and the Ethernet 22. The transfer of data has been described. As will be appreciated, the same description may also apply when data is received at MR FIFO 32, transmitted to SRAM 16, read by BR FIFO 30, and then transmitted to CPU 12.

6 shows a method of generating an address when data is being written into the SRAM 16. The address generator of the BX logic 34 is in the dotted line 98, and the address generator of the MR logic 38 (Fig. 3) is also therein. The method of generating addresses for the SRAM 16 begins with the BX write pointer 100 indicating the memory location where the next packet of information is to be written. When a packet begins to be written into memory, the starting memory location is stored in the starting packet pointer 102. Thus, the start packet pointer 102 holds the address of the memory location in the SRAM 16 where the BX logic 34 begins to write the packet. The location of the starting memory is recorded along with the memory location at the end of the packet. Since the 16 bit address must be transmitted over the 8 bit address bus, this 16 bit address must be divided into two 8 bit portions. In order to generate addresses when data is written, it is necessary to increment the lower 8 bit portion of the address as each byte is written. The upper 8 bit portion is incremented each time a page is written, ie when the lower 8 bits are HEXFF. Thus, the BX write pointer 100 is incremented lower input 104 which increments the BX write pointer 100 each time a byte is written into the SRAM 16 and whenever a new page is started, i.e., the lower one. It has an incremental upper input 106 that increments the BX write pointer 100 after the address byte reaches the HEXFF value. The BX write pointer 100 contains the 16 bit address of the memory location where the byte was just written. Since the 16-bit address is transmitted over the 8-bit address bus, the MUX 108 is sent to the upper 8-bit portion and the lower 8-bit portion to transfer the 16-bit address to the SRAM 16 via the 8-bit bus, represented by 110. Reformatted, FIG. 6 shows a portion of SRAM 16 as dotted line 112. At 114 SRAM 16 converts the two 8-bit address portions to 16-bit address 116, represented by 116. When the end of a packet is written into the SRAM 16, the memory location where the end of this packet is written is written into the start memory location recorded in the start packet pointer 102.

7 shows a read address generator shown in dotted line 124 of the MX logic 36 for generating a read address for reading data from the SRAM 16. A read pointer 126 of a portion of SRAM 16 (shown in dashed line 127) indicates the 16-bit memory location where the byte just read is located. This 16-bit memory location is converted by MUX 128 into two 8-bit portions disposed on the 8-bit address bus, indicated at 130. These two 8 bit address portions are received by the MX logic 36 and reassembled to the 16 bit address 134 by the flip flop 132.

The foregoing description of the preferred embodiments of the present invention has been presented for purposes of illustration only, and is not intended to limit the present invention to the disclosed form. Obvious modifications and variations may be made in light of the above description. The embodiments described above provide the best examples of the principles and practical applications of the present invention, enabling those skilled in the art to make appropriate adaptations to the various embodiments in accordance with the particular application contemplated. All such variations and modifications are included within the scope of the invention as defined by the appended claims.

The present invention relates to a network controller for controlling the transfer of data between a station having a CPU and a network, the network controller comprising a memory, at least one FIFO managing data transfer, and a coordinator 42 controlling each of the FIFOs. Embodiment is an SRAM controller).

The network is an Ethernet network;

The at least one FIFO is:

A first FIFO 26 for managing transfer of CPU data from the CPU to the memory, and coupled to the first FIFO to convert the CPU data from a first bit size to a second bit size and the second bit size First logic (34) for generating addresses for writing the CPU data of the memory to the memory;

A second FIFO 28 for managing the transfer of the CPU data from the memory to the Ethernet, and coupled to the second FIFO to generate addresses for reading the CPU data in the memory and storing the data; Second logic for converting from a two bit size to a first bit size;

The coordinator controls each of the FIFOs, limits the transmission over each FIFO to a selected number of bytes, and polls each FIFO after the selected number of bytes are transmitted to determine whether a transmission request is outstanding. Characterized in that.

The Ethernet controller includes four FIFOs with associated logic forms that manage data transfer from station CPU to buffer memory, from buffer memory to Ethernet, from Ethernet to buffer memory, and from buffer memory to station CPU. The Ethernet controller includes a coordinator that adjusts which FIFOs will be prioritized for data transmission.

The logic associated with each FIFO converts the bit size of the data from the first bit size to the second bit size and generates addresses for writing to or reading from the buffer memory. This logic also converts the 16-bit address into two 8-bit portions so that it can be transmitted over an 8-bit address bus, and also converts these two 8-bit portions into the original 16-bit address.

The coordinator limits each FIFO to 32 byte transfers per request, and polls other FIFOs after each 32 byte transfer to determine whether there is an outstanding transfer request. This coordinator grants requests by the coordination algorithm.

Each FIFO has a size chosen to maximize the performance of the Ethernet controller.

The present invention will become apparent from the following detailed description with reference to the accompanying drawings. As will be apparent to those skilled in the art from the following description, the preferred embodiments to be considered as the best way for carrying out the invention are illustrated and described by way of example. As can be appreciated, other embodiments are possible without departing from the scope of the present invention, and variations may be made in various and obvious aspects. Accordingly, the drawings and detailed description are to be regarded as illustrative rather than restrictive.

Claims (16)

A network controller for controlling the transfer of data between a station having a CPU and a network, the network controller comprising a memory, at least one FIFO for managing data transfer and a coordinator 42 for controlling each of the FIFOs. The network is an Ethernet network; The at least one FIFO is: A first FIFO 26 for managing transfer of CPU data from the CPU to the memory, and coupled to the first FIFO to convert the CPU data from a first bit size to a second bit size and the second bit size First logic (34) for generating addresses for writing the CPU data of the memory to the memory; A second FIFO 28 for managing the transfer of the CPU data from the memory to the Ethernet, and coupled to the second FIFO to generate addresses for reading the CPU data in the memory and storing the data; Second logic for converting from a two bit size to a first bit size; The coordinator controls each of the FIFOs, limits the transmission over each FIFO to a selected number of bytes, and polls each FIFO after the selected number of bytes are transmitted to determine whether a transmission request is outstanding. Network controller, characterized in that. The method of claim 1, A third FIFO (32) for managing the transfer of Ethernet data from the Ethernet to the memory; And A fourth FIFO (30) for managing the transfer of the Ethernet data from the memory to the CPU; And the coordinator controls the third FIFO and the fourth FIFO. The method of claim 2, Coupled to the third FIFO, converting the Ethernet data from the first bit size to the second bit size and generating addresses for writing the Ethernet data of the second bit size to the memory; 3 logic 38; And Further coupled to the fourth FIFO, fourth logic 40 for generating addresses for reading the Ethernet data in the memory and converting the Ethernet data from the second bit size to the first bit size. Network controller comprising a. The method according to any one of claims 1 to 3, And said selected number of bytes is 32 bytes. The method of claim 1, The coordinator granting requests from the FIFOs in accordance with a coordination algorithm. The method of claim 5, The arbitration algorithm prioritizes access of the receiving FIFO at a first level, among receiving FIFOs, prioritizing a receiving FIFO with an open request on the media access side of the Ethernet controller, and at the first level. Give a second priority to the transmit FIFO in a second order, and give a priority to the transmit FIFO with pending requests on the bus side of the Ethernet controller among the transmit FIFOs. The method of claim 1, And wherein the first FIFO has a first selected size. The method of claim 7, wherein And said first selected size is 180 bytes. The method of claim 1, And wherein the second FIFO has a second selected size. The method of claim 9, And said second selected size is 112 bytes. The method of claim 2, And wherein the third FIFO has a third selected size. The method of claim 11, And said third selected size is 108 bytes. The method of claim 2, And said fourth FIFO has a fourth selected size. The method of claim 13, And said fourth selected size is 160 bytes. The method of claim 1, And first means for reformatting the 16-bit address into a first 8-bit portion and a second 8-bit portion for transmitting over an 8-bit address bus. The method of claim 15, And second means for reformatting the first and second eight bit address portions to the sixteen bit address after being transmitted over the eight bit address bus.