KR20000010659A - Intergrated and switchable line termination - Google Patents

Abstract

PURPOSE: An integrated and switchable line termination is provided to achieve effective digital expression signalling. CONSTITUTION: The line receiver circuit includes an integrated input amplifier circuit and a line receiver circuit. The integrated input amplifier circuit(1) has a noninverting input terminal(11) and an inverting input terminal(12) for connection with a transmission line(31,32). The line receiver circuit includes line impedance termination means(2) for terminating the characteristic impedance of the transmission line(31,32). The input amplifier circuit(1) and the line impedance termination means(2) are integrated on a common semiconductor substrate.

Description

Circuit receiving circuit

Currently, various concepts are known for digital logic and digital signaling between circuits.

Early concepts are Diode-Transistor Logic (DTL), Transistor-Transistor Logic (TTL), and Emitter Coupled Logic (ECL), which not only support digital signaling between circuits or circuits or circuit boards, Was used for.

Concepts designed for transmitting digital data at high data rates preferably utilize differential transmission and reception of digital data, using a pair of signaling wires. Differential Positive Emitter Coupled Logic (DPECL), Low Voltage Differential Signaling (LVDS), and Grounded Low Voltage Differential Signaling (GLVDS) are examples of signaling concepts that use differential signaling. Differential concept across the ground wires connecting the transmitter and receiver Differential signaling that can maintain the differential voltage across a pair of signaling wires, which is lowered due to the spurious voltage drop, adversely affects the quality of the data transmission. The low differential signaling voltage in turn maintains the power transmitted over the low impedance transmission line within a reasonable range.

With the rapid increase in the ratio of integration and operating speeds, the complexity of digital circuits increases accordingly, so the number of signal channels between each circuit component and the number of pins of integrated circuits increase accordingly. Space on the printed circuit board surface for accommodating parts and for wiring between the parts and / or surroundings is very important.

In addition, complex systems often use different signaling techniques for different parts for a variety of different reasons. Given all of the differential signaling concepts currently available, signaling voltages are present at more than 4 volts, somewhat below zero volts. As a result, it is impossible to connect the output of a circuit according to one particular differential signaling concept and the input of another circuit according to another signaling concept. Thus, complex circuit designs must adhere to certain signaling concepts or include means for converting between different signal levels. The first alternative is a lack of flexibility and flexibility for future developments, while the latter alternative requires additional space and power independent of the system's main functions.

The present invention relates to a line receiver circuit which can be electrically connected to a transmission line for receiving information transmitted in the form of a digital electrical signal via the transmission line.

1 is a block diagram generally showing an embodiment of a circuit receiver circuit according to the present invention;

2 shows a first embodiment of the line termination impedance means;

Figure 3 shows a second embodiment of the line termination impedance means of the present invention;

4 shows a third embodiment of the line termination impedance means of the present invention;

Fig. 5 shows a fourth embodiment of the line termination impedance means of the present invention;

6A shows a symbol used to represent a transfer gate;

6b is a simplified illustration of an embodiment of a transmission gate in accordance with the present invention;

The present invention aims to solve the problems mentioned above. It is also an object of the present invention to make digital high speed signaling as simple and space and cost effective as possible. These objects have been solved as defined in claim 1. Embodiments of the invention are defined in the dependent claims.

To achieve these objects, the present invention provides an integrated input amplifier circuit having a non-inverting input terminal and an inverting input terminal for connecting with a transmission line; And a line receiving circuit including line termination impedance means for terminating the characteristic impedance of the transmission line. Here, the input amplifier circuit and the line termination impedance means are integrated on a common semiconductor substrate.

According to the present invention, the integrated line receiver not only reproduces the signal received through the transmission line but also provides suitable termination of the transmission line by including terminating impedance means in the chip of the integrated line receiving circuit. Of course, an integrated line receiving circuit including integrated termination impedance means may be integrated on the same chip as other circuitry for processing received information.

The circuit receiving circuit according to the present invention connects a transmission line directly to an input pin of an integrated circuit which receives data via the transmission line, without having to provide a proper termination for the transmission line. Therefore, if there is no extra space in the printed circuit board, there is a need for a component that terminates the transmission line. In this way, a large number of signal channels and input pins can be connected in a space- and cost-effective manner. The present invention uses current digital differentials with low signaling voltage differences in the 0.2 volt range, for example, so that the termination impedance does not consume much power and therefore can be integrated into the semiconductor substrate of the circuit receiving circuit without taking up much space. Use the signaling concept. In order to improve the stability of the overall circuit design, integrating the line termination impedance means and the input amplifier on the same chip will reduce the spurious resonance caused by the series connection of the capacitance of the inductive component of the bond wire and the amplifier input terminal very efficiently. There is an additional advantage that it can.

In order to avoid the need for means to move between different signaling levels in a mixed system using a variety of different digital signaling techniques, in accordance with an embodiment of the present invention, the termination means connected across the input terminals of the input amplification circuit remain floating. Can be. In other words, it does not require a certain common mode voltage for desirable operation, but can operate to a rather large level above the level of the power supply voltage of the circuitry circuit in a fairly large common mode voltage range, for example, slightly below ground level. If the input amplification circuit has a fairly wide common mode voltage level range, the line receiving circuit may be any one in the common mode operating voltage range of the input amplification circuit and the transmission impedance means until the common mode voltage on the transmission line is determined by the transmitter. It may be connected to the transmitter and will work preferably.

In addition, in order to process other characteristic impedance of the transmission line, the line receiving circuit according to the present invention includes a plurality of impedance circuits and at least one transmission gate circuit controllable to be in a low impedance or high impedance blocking state. An impedance circuit and the at least one transfer gate circuit are interconnected such that an impedance value of the line termination impedance means can be controlled by controlling the at least one transfer gate circuit.

A particular embodiment of the line receiving circuit of the present invention includes line termination impedance means including parallel connection across input terminals to an input amplifier circuit of each of a plurality of series circuits composed of impedance and transmission gate circuits.

If the transfer state or blocking state of each of these transfer gates is appropriately selected, it is possible to select an appropriate value of the total termination impedance as necessary. In addition, if termination of the transmission line is not required, for example, if the transmission line operates as a separately terminated data bus, the circuit receiving circuit according to the present invention transmits all switching gates to a high impedance blocking state. This can prevent the circuit from acting as a load. The transmission gate and the circuit terminating means are preferably designed so that the circuit receiving circuit is in a floating state in view of the above.

According to a particular embodiment of the present invention, each of one or more of the series circuits composed of the transmission gate and the impedance means may be provided such that the series circuit includes two impedance means connected to each other through the transmission gate. All terminals of the transfer gate can be connected to a voltage source of a suitable level and of a suitable source impedance through an additional transfer gate. If the type of transmitter used to drive the transmission line is assumed to be this type of common mode termination at the receiver end, or if a transmission line requiring this type of termination is used, then the transmission gates of the serial connection may be blocked. It is possible to achieve a separate common mode termination of each terminal of the input transmission line by maintaining and keeping the additional transmission gates in a low impedance transmission state.

In yet another embodiment of the present invention, such a series circuit comprises a plurality of impedance means connected in series, each transmission means being connected in parallel. By appropriately selecting the transfer state or blocking state of each of these transfer gates, the overall impedance of the series circuit can be adjusted as needed.

The transmission state of each transmission gate may be controlled by a reception control terminal for each transmission gate. If multiple similar line receiving circuits for multiple signal channels are integrated in a common semiconductor chip, the corresponding control terminals of the corresponding transfer gate circuits can be connected together. The control terminal of the circuit receiving circuit may be connected to a dedicated input configuration pin or driven by a logic circuit that blocks unnecessary or negative coupling of the transmission state of each circuit receiving circuit transmission gate.

In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall block diagram of a line receiver embodiment in accordance with the present invention. In this figure, reference numeral 1 denotes a differential input amplifier circuit having a non-inverting input terminal 11 and an inverting input terminal 12. The voltage difference between the input terminals 11 and 12 is amplified by the amplifier 1 in linear or nonlinear form and the amplified signal is shown at the output terminal 13 of the amplifier. Reference numeral 2 denotes line termination impedance means connected to both ends of the input terminals 11 and 12 of the amplifier 1. The conductors 31 and 32 constitute a transmission line driven by a data transmitter (not shown) and are connected to the input terminals 11 and 12 of the amplifier 1. The dotted box around the input amplifier 1 and the line termination impedance means 2 means that both the input amplifier circuit 1 as well as the line termination impedance means 2 are integrated on a common semiconductor substrate, i.e., the input amplifier ( 1) and the line termination impedance means 2 are components of the same integrated circuit. Of course, in addition to the elements in the dashed box of FIG. 1, other elements may be used for additional signal channels and other circuitry for processing information received over each of the transmission lines connected to the integrated circuit, for example, the integrated circuit. It can be provided for input amplifiers and line termination means.

(VDD) and (VSS) in Fig. 1 represent power supply terminals for the input amplifier circuit 1. While the line termination impedance means 2 of FIG. 1 receives power supply voltages across (VDD) and (VSS), the connection between the line termination impedance means 2 and (VDD) and (VSS) is connected to the line termination impedance means ( It is not a special embodiment of 2).

In most basic forms the line termination impedance means 2 is a resistor of a resistor selected according to the characteristic impedance of the transmission lines 31 and 32.

According to another basic embodiment, the line termination impedance means 2 comprises a common mode terminal for each signal conductor using one termination impedance for each of the conductors 31 and 32 of the transmission line. In this case each impedance is connected to (VDD) or (VSS) or to terminal (VT), depending on the type of transmission the transmitter is expected to transmit. If each of the termination impedances is connected to terminals VT, the action of the external voltage on these terminals is the common mode transmission of the conductors 31 and 32 of the transmission line at any potential which can be determined according to the type of transmitter used. Makes it possible.

2 shows a first embodiment of the line impedance terminating means 2. According to this embodiment, the line impedance terminating means 2 comprises a series connection of a first impedance R11, a transmission gate T1, and a second impedance R12, which series connection comprises an input amplifier circuit 1. Are connected to both ends of the input terminals 11 and 12. In this embodiment, 31 and 32 are symmetrical transmission lines (e.g., twisted pair or similar forms) terminated by the series connection of (R11), (T1) and (R12). Refer to the conductor of the transmission). In consideration of the symmetry of the transmission line, the impedances R11 and R12 preferably have the same impedance value.

C1 indicates the control terminal of the transfer gate T1. By supplying a suitable control voltage to the control terminal C1, the transfer gate T1 takes a low impedance transfer state, i.e., connects the impedances R11, R12 substantially like a short circuit, or takes a high impedance blocking state, i.e. Disconnect the connection between (R11) and (R12).

Thus, by means of the transfer gate T1, the first embodiment of the present invention allows switching on / off of the internal terminals composed of (R11) and (R12) connected in series. In this way, the circuit receiving circuit of the present invention according to this embodiment can be configured to operate as a dedicated transmission line or as a data bus transmission line. The transfer gate in the first case is controlled to take a low impedance transfer state, while in the latter case the transfer gate is controlled to take a high impedance blocking state.

Although not shown in FIG. 2, as shown in FIG. 2, a plurality of series circuits each consisting of a first impedance, a transmission gate, and a second impedance are provided, so as to be parallel to both ends of the input terminals 11 and 12 of the amplifier 1. It is possible for all connected series circuits to form terminal impedances across the input terminals 11 and 12 of the input amplifier 1 to match different impedance characteristics of the transmission lines 31 and 32. In this case, the transmission gate T1 of each series circuit selects specific series connections of impedances R11 and R12 so that they are connected in parallel so that the final impedance of such parallel connections can be adjusted as necessary.

3 shows a second embodiment of the line termination impedance means according to the present invention. A second embodiment similar to the embodiment shown in FIG. 2 includes a series connection of a first impedance R11, a transmission gate T1 and a second impedance R12, which series circuitry comprises an input of an input amplifier 1. It is connected to both ends of the terminals 11 and 12. Reference numerals 31 and 32 denote the conductors of the transmission lines connected to the input terminals 11 and 12 of the amplifier 1. In addition to the elements shown in FIG. 2, the second embodiment includes a pair of first transfer gates T11 and T12, a pair of second transfer gates T13 and T14, and a pair of third transfer gates T15 and T16. ). C11 is a control terminal for controlling the transfer state of the transfer gates T11 and T12. C12 is a control terminal for controlling the states of the transfer gates T13 and T14, and C13 is a control terminal for controlling the transfer states of the transfer gates T15 and T16. Transmission gates belonging to the same pair always take the same transmission state as determined by the signal supplied to the corresponding control terminal.

The first transfer gate T11 of the first transfer gate pair is connected between the terminal of the impedance R12 connected to the transfer gate T1 and the negative power supply terminal VSS. The second transfer gate T12 of the first transfer gate pair is connected between the terminal R11 and the terminal VSS connected to the transfer gate T1. The transfer gate T13 of the second transfer gate pair is connected between the terminal of the impedance R12 connected to the transfer gate T1 and the positive power supply VDD. The second transfer gate T14 of the second transfer gate pair is connected between the terminal of the impedance R11 connected to the transfer gate T1 and the power supply terminal VDD. The first transfer gate T15 of the third transfer gate pair is connected between the terminal of the impedance R11 connected to the transfer gate T1 and the terminal VT for supplying an external voltage potential. The second transfer gate T16 of the third transfer gate pair is connected between the terminal VT and the terminal of impedance R12 connected to the transfer gate T1.

The second embodiment allows the line impedance terminating means to be formed to terminate other various types of transmission lines. Depending on the control signal supplied to the control terminals C1, C11, C12 and C13, to terminate the symmetrical transmission line and / or to supply the positive power supply potential VDD or the negative power supply potential VSS or any termination voltage. In order to provide a common mode termination of each of the conductors 31 and 32 of the transmission line to the terminal VT, it is possible to construct a line receiving circuit including the line termination impedance means of the second embodiment. This embodiment also recognizes that no termination of the transmission line occurs.

To terminate the symmetrical transmission line, the transmission gate T1 is controlled to be in a low impedance transmission state while all other transmission gates shown in FIG. 3 are controlled to be in a high impedance blocking state. For common mode termination of the conductors 31 and 32 with respect to the positive supply voltage VDD, the transfer gates T13 and T14 are controlled to take a low impedance transfer state while all other transfer gates shown in FIG. It is controlled to take the impedance blocking state.

If common mode termination of the conductors 31 and 32 is required with respect to the negative power supply voltage VSS, the transfer gates T11 and T12 are controlled to take a low impedance state while all other transfer gates shown in FIG. It is controlled to take a high impedance blocking state. If a common mode termination of the conductors 31, 32 is required with respect to a potential other than (VDD) or (VSS), a voltage source providing a suitable voltage level is connected between the terminal VT and for example (VSS) All transmission gates except for (T15) and (T16) are controlled to take a high impedance blocking state, while (T15) and (T16) are controlled to take a low impedance state.

If at the same time as the symmetrical termination of the conductors 31 and 32, the common mode termination of the conductors 31 and 32 is required, i.e. if the Y-type termination of the transmission line is required, the transmission gate T1 has a low impedance. When controlled to be in a transfer state and at the same time a common mode termination is required for (VDD), the transfer gates T13 and T14 can be controlled to be in a low impedance state. Likewise, if a Y-type termination is required with respect to (VT), the transfer gates Tl, T15 and T16 are controlled to take a low impedance transfer state while all other transfer gates are in blocking state. For each kind of Y-termination, as shown in FIG. 3, the additional impedances RS1, RS2, RS3 can act as signal source impedances for common mode termination. Of course, the Y-type termination of the transmission lines 31 and 32 may be made by the transmission gate T1 in a blocking state. However, in this case, the current driving capability of the transfer gates T11 to T16 must be higher, and therefore, the size of these transfer gates is controlled when the transfer gate T1 is taken to have a low impedance state for the Y-type termination. Should be greater than

Fig. 4 shows a third embodiment of the line termination impedance means according to the present invention. This embodiment also shows that instead of connecting a single transfer gate T1 between the impedances R11 and R12, a series connection of two transfer gates T21 and T22 is connected between the impedances R21 and R22. It differs from the Example shown in 3. In addition, a single transfer gate T25 is provided instead of the pair of transfer gates T11 and T12. A single transfer gate T23 is provided instead of the pair of transfer gates T13 and T14, and a single transfer gate T24 is provided instead of the pair of transfer gates T15 and T16. As also shown in the figure, each of the transmission gates T23 to 25 is one of its transmission terminals connected to the transmission terminal of T21 connected to the transmission terminal of T22. Operation and control of the third embodiment are similar to those described with respect to the second embodiment.

With regard to the first, second and third embodiments, the impedances R11, R12, R21 and R22 and the impedances RS1, RS2 and RS3 need not all exist as separate components on the semiconductor chip but their respective low impedance transmission states. Can be implemented by designing each transmission gate so that they have the desired transmission impedance. When using field effect transistors to design the transfer gate, the desired transfer impedance can be obtained, for example, by properly designing the channel arrangement.

If the termination of the transmission lines 31, 32 by the line termination impedance means 2 is not necessary, all the transmission gates shown in Figs. 2, 3 or 4 are switched to the high impedance blocking state. In order to further lower the capacitive load on the transmission lines 31, 32, an additional transmission gate (not shown) is provided between the amplifier input terminal 11 and the first impedance R21 or R22 and also the second impedance R12. Or between R22) and the amplifier input terminal 12. These additional transfer gates can be controlled to take a high impedance blocking state if no termination is needed, otherwise take a low impedance transfer state.

Figure 5 shows a fourth embodiment of the line termination impedance means according to the invention. According to this embodiment, a series connection of three impedances R31, R32 and R33 is provided. Each of these impedances has transmission gates T31, T32 and T33 connected in parallel, respectively. For simplicity, the control terminals (T31 to T33) are not shown in FIG. In this embodiment, the line termination impedance can be adjusted between the conductors 31 and 32 of the transmission line by shorting the selected impedance among a plurality of impedances R31 to R33 connected in series. If necessary, in order to take into account the disconnection of the total line termination impedance means 2, additionally between the amplifier input terminal 11 and the series connection and between the amplifier input terminal 12 and the series connection as in the previous embodiment Transmission gates (not shown) may be provided.

For the Y-type termination, a variation of the line impedance termination means shown in FIG. 5 includes a termination transmission gate T32 which is replaced by a line termination impedance circuit 2 shown in FIG. 3 or a line termination impedance circuit shown in FIG. do.

The input terminals 11 and 12 of the input amplifier 1 are connected by connecting a plurality of circuit examples described with reference to FIGS. 2, 3, 4 and 5 in parallel across the input terminals 11 and 12 of the amplifier 1. It is possible to match the differential characteristic impedance of the transmission lines 31 and 32 used by forming the termination impedance and the desired termination voltage respectively at both ends. By appropriately selecting the transfer states of the transfer gates available in the circuit of the parallel connection, the value of the symmetric termination impedance and / or the value of each common mode termination impedance can be adjusted as needed by effectively connecting the appropriate number of impedances in parallel. Can be. If a number of circuits are connected in parallel in accordance with any of the embodiments described above, the transmission line 31 may be switched by switching these additional transmission gates in high impedance blocking state if both ends of the lines 31 and 32 need not be terminated. It is desirable to provide additional transmission gates in series with this parallel connection at all stages of the parallel connection in order to reduce the capacitive load on the circuit 32.

The control terminals C1, C11, C12, and C13 of each line impedance terminating means 2 are implemented as input component pins of an integrated circuit including the line receiving circuit of the present invention. In particular, a logic circuit for driving the control terminals C1, C11, C12, and C13 in accordance with the logic state of the logic circuit input terminal may be provided in order to exclude inappropriate coupling of the transfer states of the transfer gates of each transfer gate pair. . In this way, the number of component pins required for setting up the circuit-terminated impedance means 2 can be reduced and damage to the integrated circuit due to an incomplete state can be prevented. If such a logic circuit is provided, it can control the additional transmission gates not shown in the figure.

The logic circuit can receive binary information based on the termination value and binary information based on the termination type. No termination, i.e. contains very large impedance values close to infinity, or floating-mode (symmetric) termination, common mode termination for (VSS), (VT) or (VDD), and (VSS), (VT) or Y-termination for (VDD) is included in the form of termination.

As an alternative to controlling the logic circuit via an external control terminal for inputting termination impedance values and termination type information, the present invention relates to each transmission state when designing or manufacturing an integrated circuit including a circuit receiving circuit. It is possible to program the transmission status.

In addition, a control circuit can be provided to actively adjust the termination impedance to a desired value in order to compensate for processing variations and / or temperature variations and / or power supply variations. For this purpose, the active control circuit can include an external reference resistor.

6A shows a symbol used to represent the transfer gate of the present invention. The transmission gate includes a control terminal c in addition to the two transmission terminals a and b. In accordance with the signal supplied to the control terminal c, the transfer gate takes a low impedance transfer state or a high impedance blocking state with respect to the terminals a and b. FIG. 6B is an embodiment of the transfer gate of FIG. 6A. According to this embodiment, the transfer gate includes not only the NMOS transistor TR1 but also the channels of the NMOS transistor TR1 and the PMOS transistor TR2 connected between the PMOS transistor TR2 and the terminals a and b of the transfer gate. do. INV is an inverter of the output connected to the gate of the PMOS transistor TR2. The control voltage at terminal c is supplied to the inputs of the NMOS transistor TR1 and the inverter INV.

If the voltage supplied to the control terminal (c) is low, or close to (VSS), the potential of the terminal (a) or the potential of the terminal (b) is the threshold voltage of (TR1) at the potential of the terminal (c) NMOS transistor TR1 remains in a non-conductive state unless it is lower than minus. In addition, when the gate of the PMOS transistor TR2 is at a high potential (or close to VDD) due to the operation of the inverter INV, the transistor TR2 also has a potential of the terminal a or the potential of the terminal b. It exists in a non-conductive state unless it increases more than the gate potential of (TR2) plus the threshold voltage of (TR2). Thus, if terminal c is kept low, the circuit shown in Fig. 6b is a high impedance of nonconductivity between the terminals as long as the potential of terminals a, b remains only in the stated range. Will maintain state.

If the potential at terminal c rises to or approaches VDD, the gate of NMOS transistor TR1 accepts a high potential while the gate of transistor TR2 of PMOS due to inverter INV. Accepts low voltage. Therefore, the NMOS transistor TR1 is conducted while the terminals of the terminals a and b have a lower potential than the potential at the control terminal c by the low potential, the threshold voltage of the TR1. The PMOS transistor TR2 assumes a conducting state when the higher potential at the terminals a, b is at or near the threshold voltage of (TR2) higher than the gate voltage of the PMOS transistor TR2. . Thus, if a high potential is applied to terminal c, the circuit of Fig. 6b suitable for floating operation assumes a low impedance transfer state between terminals a and b regardless of the potential at terminals a and b.

Claims (11)

In the line receiving circuit, An integrated input amplifier circuit (1) having a non-inverting input terminal (11) and an inverting input terminal (12) connected to the transmission lines (31, 32); And A line termination impedance means (2) for terminating the characteristic impedance of the transmission lines (31, 32), The input amplifier circuit (1) and the line termination impedance means (2) are integrated on a common semiconductor substrate. 2. The line termination impedance means (2) according to claim 1, Multiple impedance circuits R; And At least one transfer gate circuit T having a pair of transfer terminals a, b and controllable to assume a low impedance or high impedance blocking state between the transfer terminals a, b, The plurality of impedance circuits (R) and the at least one transfer gate circuit (T) are interconnected such that an impedance value of the line termination impedance controls the at least one transfer gate circuit. 2. The line termination impedance means (2) according to claim 1, A series connection of the impedance circuits R11, R12 and the first transmission gate circuit T1, The serial connection is connected to both ends of the input terminals (11, 12) of the input circuit (1). The method of claim 3, wherein the serial connection A first having one of the terminals of the one connected to one of the input terminals of the input amplification circuit and having the other terminal of the one connected to one terminal of the first transfer gate circuit T1; T2; Impedances R11; R21; R31; And A second impedance having one of the terminals connected to the other input terminal of the input amplification circuit 1 and having its other terminal connected to the other terminal of the first transfer gate circuit T1; T2; T3; And a circuit receiving circuit comprising: (R12; R22; R32). 5. The line termination impedance means (2) according to claim 4, A second transmission gate circuit (T12; T14) connected between said one terminal of said first transmission gate circuit (T1) and one of the power terminals of the line receiving circuit (VDD; VSS); And A third transmission gate circuit (T13; T11) connected between said other terminal of said first transmission gate circuit (T1) and one of the power supply terminals of a circuit reception circuit (VDD; VSS); Receiving circuit. 5. The circuit of claim 4, wherein the line termination impedance means A fourth transfer gate circuit (T15) connected on said one terminal of said first transfer gate circuit (T1) and on a terminal (VT) for supplying an external termination voltage; And A fifth transmission gate circuit (T16) connected between said other terminal of said first transmission gate circuit (T1) and a terminal (VT) for supplying an external termination voltage. 3. The line termination impedance means (2) according to claim 2, Series connection of the third impedance R21, the sixth transmission gate T21, the seventh transmission gate T22 and the fourth impedance R22; And An eighth transmission gate (T23, T25), one of its transmission terminals being connected to the sixth transmission gate (T21) and the seventh transmission gate (T22), the other of its transmission terminals The circuit receiving circuit is characterized in that it is connected to one of the power supply terminals VSS and VDD of the circuit receiving circuit. 8. The line termination impedance means (2) according to claim 7, A ninth transfer gate T24, one of which is connected to the sixth and seventh transfer gates T22, the other of which is external A line receiving circuit characterized by being connected to a terminal (VT) for supplying a termination voltage. 3. The line impedance terminator (2) of claim 2, wherein Multiple impedances (R31, R32, R33) connected in series, At least one of said impedances (R31, R32, R33) comprises transmission gates (T31, T32, T33) connected in parallel. The method according to any one of claims 2 to 9, Each transfer gate circuit T1 comprises an N-channel MOSFET TR1 and a P-channel MOSFET TR2 in parallel connection, The gate of the N-channel MOSFET TR1 is connected to receive a transmission control signal C1 and the gate of the P-channel MOSFET TR2 is connected to receive the inverted transmission control signal. Circuit. The method according to any one of claims 2 to 10, -A line receiving circuit comprising a plurality of line termination impedance means (2) connected in parallel between said input terminals (11, 12) of said input amplifier circuit (1).