KR20000009275A - Fabrication method of semiconductor memory device - Google Patents

Abstract

PURPOSE: A fabrication method of semiconductor memory device is provided to prevent a short circuit among wiring lines using a patterning process so as to remove a residue due to a stage difference between a cell array region and a periphery circuit. CONSTITUTION: The fabrication method of semiconductor memory device having a dielectric layer(116) between an upper electrode layer and a lower electrode layer includes the step of gradient patterning a side of the lower electrode layer presented at the most outside angle of cells among lower electrodes to reduce the stage difference between a cell array region and a periphery circuit. Thereby, it is possible to prevent short circuits among wiring lines using the patterning process and to obtain a high integration in fabricating the semiconductor memory device.

Description

Manufacturing Method of Semiconductor Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for improving planarization of a semiconductor memory device.

Recently, as the degree of integration of semiconductor memory devices is gradually increased, not only various patterns constituting the memory cell but also rapid high integration have been shown in the width of the wiring and the space between the wiring and the wiring. Therefore, in this field, researches on MDL (Merged DRAM and Logic) devices that form DRAMs and logic on one device at the same time have been actively conducted according to the development trend that is becoming highly integrated. However, while the MDL device has a very good advantage of increasing the degree of integration of a semiconductor memory device, the complexity of the manufacturing process causes undesirable problems. In general, a metal contact is formed on a silicon substrate, a polysilicon film of a word line and a bit line, and a plate electrode, which is an upper electrode of a capacitor, to form a DRAM wiring. However, in the case of forming such a metal contact, a plurality of material layers are deposited in the previous process step so that the cell array region and the peripheral circuit region have different stack heights from the semiconductor substrate, thereby forming a step. In particular, by forming a thick storage electrode to increase the capacitance of the capacitor, a large step is formed between the cell array region and the peripheral circuit region to form a plate contact for applying an external voltage to the plate electrode in a subsequent process. In case of performing etch back after depositing a metal film such as tungsten, the step is not completely removed and residue remains due to the recessed boundary, resulting in particles or wiring and wiring defects that cause defects in the semiconductor device. It may also cause short circuits. In this field, in order to solve such a problem, after depositing a metal film for forming a contact, the residue of the stepped portion is removed by over etching until the insulating film on the lower side is etched. However, when using this method, the residue of the stepped portion is removed, but the metal film consumption in the plate contact is increased, which causes device defects. As another method, an CVD film or an SOG film is deposited and etched back before the deposition of the insulating film on which the contact is to be formed. However, due to the addition of deposition and etch back processes, the unit cost is increased and the uniformity of the insulating layer is decreased, and the thickness of the insulating layer in the portion where the storage electrode is formed is relatively thick. Occurred. In addition, despite the added process, the step was not alleviated significantly.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device that can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device that can alleviate the step between the cell array region and the peripheral circuit region.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device for preventing metal film residue from remaining between a cell array region and a peripheral circuit region in forming a plate contact.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device that does not cause short circuit between wirings.

In order to achieve the above objects, the present invention provides a semiconductor memory device having a high dielectric layer between an upper electrode layer and a lower electrode layer, wherein one side of the lower electrode layer existing at the outermost side of the cell among the lower electrode layers is obliquely patterned. Provided is a semiconductor memory device characterized by mitigating a step between an array region and a peripheral circuit region.

Preferably, one side of the lower electrode layer is characterized in that the side adjacent to the peripheral circuit region.

Also, in order to achieve the above objects, the present invention provides a method of manufacturing a semiconductor memory device for alleviating the step difference between a cell array region and a peripheral circuit region: after depositing a conductive film to be patterned as a storage electrode of a capacitor, Forming a periphery film; In the outermost part of the cell, the photolithography and etching process are performed using a mask pattern designed to prevent light from being completely transmitted. The storage electrode formed at the outermost part of the cell is formed so that one side is inclined, thus, between the cell array area and the peripheral circuit area. It provides a method for manufacturing a semiconductor memory device, comprising the step of mitigating the step.

Also, in order to achieve the above objects, the present invention provides a method of manufacturing a semiconductor memory device for alleviating the step difference between a cell array region and a peripheral circuit region: after depositing a conductive film to be patterned as a storage electrode of a capacitor, Forming a periphery film; Patterning the photoresist through photolithography and etching, and then forming a dummy pattern at a predetermined interval from the photoresist pattern positioned at the outermost portion to alleviate the step between the cell array region and the peripheral circuit region. A manufacturing method of a semiconductor memory device is provided.

1 is a cross-sectional view of a semiconductor memory device according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order not to obscure the subject matter of the present invention, the atmosphere and characteristics of a conventional manufacturing process are not described in detail.

1 is a cross-sectional view of a semiconductor memory device in which a step between a cell array region and a peripheral circuit region is relaxed according to a preferred embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device having a word line 104 and a bit line 110 formed thereon and a capacitor having a structure in which a high dielectric layer 116 is stacked between the storage electrode 114 and the plate electrode 118 is illustrated. An access transistor is formed in a conventional process on the semiconductor substrate 100 where the active region is defined by the field oxide film 102. The access transistor includes a word line 104 and a diffusion region, and the diffusion region includes a drain region 106 and a source region 107. In this case, the word line 104 is a gate region of an access transistor, and has a structure in which a gate insulating film, a polycrystalline silicon, and a silicide film are sequentially stacked. Subsequently, the first interlayer insulating film 108 is entirely deposited on the semiconductor substrate 100 on which the access transistor is formed, and then a bit line 110 is formed in contact with the drain region 106. Subsequently, the second interlayer insulating layer 112 is entirely deposited on the bit line 110, and the storage electrodes 114-1 and 114-2 are formed in contact with the source region of the access transistor and serve as a lower electrode of the capacitor.

In this case, referring to a manufacturing process for forming the storage electrodes 114-1 and 114-2, first, an opening for exposing the source region 107 of the access transistor is formed by etching the second interlayer insulating layer 112. Subsequently, a conductive film to be patterned as a storage electrode is deposited on the second interlayer insulating film having the opening, and then the conductive film is patterned into storage electrodes 114-1 and 114-2 by performing photolithography and etching processes. At this time, in the present invention, one side of the storage electrode to be present at the outermost part of the cell, more specifically, one side adjacent to the peripheral circuit region is patterned obliquely. As a result, as shown in the drawing, a storage electrode 114-1 having a general shape is formed inside the cell, and a storage electrode 114-2 having one side slanted patterned at the outermost part of the cell is formed. Subsequently, a high-k dielectric layer 116 and a plate electrode 118 are further formed on the resultant in which the storage electrodes 114-1 and 114-2 are formed to complete the capacitor. Subsequently, a third interlayer insulating layer 120 is formed on the plate electrode 118, and then plate contact 122 is formed. Preferably, the etchant for partially etching the third interlayer insulating film 120 to obtain the plate contact 122 uses CHF ₄ or CO.

As described above, in the present invention, one side of the storage electrode 114-2, which will be present at the outermost side of the cell, is inclined to alleviate the step between the cell array region and the peripheral circuit region. As a method for alleviating the step between the cell array region and the peripheral circuit region, first, one side of the storage electrode 114-2 is inclinedly patterned. That is, after forming a photoresist film on the conductive material to be patterned as a storage electrode, a mask pattern positioned at the outermost part of the cell is opaque so that only about 50% of light is transmitted. As such, the pattern of the photoresist film exposed through the opaque mask pattern is inclined, and the conductive material patterned through the inclined photoresist film is also inclined so that one side as in the present invention can pattern the inclined storage electrode 114-2. do.

As another method for alleviating the step between the cell array region and the peripheral circuit region, a dummy storage electrode is formed at an edge of the storage electrode existing at the outermost portion of the cell. In this case, the dummy storage electrode may be formed within a predetermined distance from the outermost storage electrode to mitigate the inclination between the cell array region and the peripheral circuit region.

In the present invention as described above, by inclining the one side of the storage electrode formed on the outermost of the cell, the inclination between the cell array region and the peripheral circuit region is relaxed. As a result, in forming a contact on the plate electrode extending long to the peripheral circuit region, there is no metal film residue present, there is an effect that the short circuit between the wiring is prevented.

Although described with reference to the preferred embodiment of the present invention as described above, it will be understood that various modifications and changes can be made without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims (5)

A semiconductor memory device having a high dielectric layer between an upper electrode layer and a lower electrode layer, And patterning one side of the lower electrode layer present at the outermost part of the cell among the lower electrode layers inclinedly, thereby alleviating the step between the cell array region and the peripheral circuit region. The semiconductor memory device of claim 1, wherein one side of the lower electrode layer is a side surface adjacent to a peripheral circuit area. In the method of manufacturing a semiconductor memory device for alleviating the step between the cell array region and the peripheral circuit region: Depositing a conductive film to be patterned as a storage electrode of the capacitor, and then forming a photosensitive film thereon; At the outermost part of the cell, the photolithography and etching process are performed using a mask pattern designed to prevent light from being completely transmitted. The storage electrode formed at the outermost part of the cell is formed to be inclined so that one side is inclined. Mitigating the step. In the method of manufacturing a semiconductor memory device for alleviating the step between the cell array region and the peripheral circuit region: Depositing a conductive film to be patterned as a storage electrode of the capacitor, and then forming a photosensitive film thereon; Patterning the photoresist through photolithography and etching, and then forming a dummy pattern at a predetermined interval from the photoresist pattern positioned at the outermost portion to alleviate the step between the cell array region and the peripheral circuit region. How to. The method of claim 4, wherein the dummy pattern is a dummy storage pattern.