KR20000009134A - Field emission display and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A field emission display and manufacturing method thereof is provided to lower operating voltage and enhance field emission efficiency, and to simplify the process due to self align process. CONSTITUTION: The present invention discloses a field emission display comprising: flat type emitter electrodes(4,32) formed on substrates(2,30); flat type emitters(34) formed on the emitter electrode and having an electron emission unit; flat type gate electrodes(8,44) focusing electrons emitted from the electron emission unit; insulation layers(6,36,38,40) separating the emitter and the gate electrode; and an anode electrode inducing the emitted electrons. The insulation layer has the first insulation layer formed on the emitter, the second insulation layer formed on the first insulation layer, and the third insulation layer formed on the second insulation layer.

Description

Field Emission Element and Fabrication Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display, and more particularly, to a field emission device and a method of manufacturing the same, which are configured to increase the field emission efficiency.

In general, a field emission display (hereinafter referred to as "FED") includes a row driver for supplying a driving voltage, a column driver for supplying image data, the row and column A pixel formed in a matrix structure is provided at the intersection of the driver. In the FED, electrons are emitted from pixels formed in a matrix structure according to a driving voltage or image data supplied from a raw driver or a column driver to display an image. At this time, each pixel Pixel has a sub-pixel of red (hereinafter referred to as "R"), green (hereinafter referred to as "G"), and blue (hereinafter referred to as "B"). And a high-density field between a cathode electrode formed on each of the R, G, and B subpixels, and an anode electrode formed on the subpixel, and a quantum mechanical tunnel effect. By means of emitting electrons. The emitted electrons are accelerated by the gate voltage and collide with the phosphor film formed under the anode electrode to excite the phosphor. The light is emitted to display an image. In this, FED is a variety of methods such as a micro tip method and a planar electron source method is currently being developed, and will be described below.

Referring to Figure 1, the manufacturing process procedure of the field emission device according to the prior art is shown.

The emitter electrode 4 is formed on the glass substrate 2. After depositing a metal film on the upper surface of the glass substrate 2, applying a photoresist (PR) to the upper portion of the metal film is patterned by photolithography (Photo Lithography), and then the emitter electrode (4) by etching (Etching) ). Subsequently, the resistive layer 6 and the insulating layer 8 are sequentially stacked on the glass substrate 2 on which the emitter electrode 4 is formed, and then a gate electrode is formed. The emitter electrode 4, the resistive layer 6, the insulating layer 8 and the metal film were sequentially formed on the glass substrate 2, and then photoresist PR was applied on the metal film to etch the photo. After the patterning method, the gate electrode 10 is formed by etching. Next, a space in which the field emission tip 12 is to be formed is prepared. The insulating layer 8 is etched through the gate electrode 10 to provide a space for forming a conical field emission tip 12 (ie, an emitter tip) as shown in FIG. Subsequently, the separation metal layer 16 is formed on the gate electrode 10 while rotating the glass substrate 2. By separating the metal material at a predetermined angle θ while rotating the glass substrate 2, a separation metal layer 16 is formed on the surface of the gate electrode 10 as shown in FIG. At this time, the separation metal layer 13 has an inlet groove in the center, and protects the gate electrode 10 when the tip material layer 14 to be described later is removed. Subsequently, the field emission tip material 14 is deposited while rotating the glass substrate 2 to form a conical field emission tip. By depositing the field emission tip material 14 at an angle while rotating the glass substrate 2, the inlet groove into which the tip material enters sequentially decreases, and in the field emission tip forming space, as shown in (c) of FIG. Field emission tips 12 are formed. Finally, the separation metal layer 13 and the field emission tip material layer 14 are removed to form a field emission device. By removing the field emission tip material layer 14 and the separation metal layer 16 in the process of forming the field emission tip, the field emission device is formed as shown in FIG. Such a manufacturing method is referred to as a rotary deposition method (ie, Spindt method). On the other hand, when the field emission device is manufactured by the spin method using the thin film and the etching process as described above, a problem that the process is complicated has been derived. In addition, as the upper part of the field emission tip becomes sharper, electron emission is performed at a lower voltage. However, this method makes it impossible to sharpen the tip below a certain limit, resulting in a high electron emission voltage. In order to solve this problem, US Patent No. 5,587, 628 proposes a method of manufacturing a field emission device described later in FIG.

2, there is shown another method of manufacturing a field emission device according to the prior art. The resistive layer 18, the emitter layer 4, the space layer 20, the insulating layer 6, and the conductive layer 22 are sequentially formed on the substrate at a predetermined thickness. (Eleventh Step) First, the resistive layer 18 is formed on the substrate (not shown) with a predetermined thickness (for example, 1 μm). Subsequently, the emitter layer 4 is formed on the resistive layer 18 to a predetermined thickness (for example, 0.1 μm). Next, a space layer 20 is formed on the emitter layer 4 with a predetermined thickness. In this case, the space layer 20 is provided to space the predetermined distance from the emitter 4 and the gate 8 and is formed of a semiconductor or a conductor. Next, the insulating layer 6 is formed in a predetermined thickness (for example, 1 micrometer) on the space layer 20. Next, the conductive layer 22 is formed in a predetermined thickness (for example, 0.5 micrometer) on the insulating layer 6. The conductive layer 22 is conductive to transfer the gate voltage to the gate electrode 8, and tungsten (W) is used. This process has a structure as shown in (a) of FIG. After the insulating layer 6 and the conductive layer 22 are etched to a desired shape, a gate material is applied to a predetermined thickness. (Step 12) The insulating layer 6 and the conductive layer 22 are etched to a desired shape. At this time, the etched form is shown in Figure 2 (b). A gate material is applied on the etched insulating layer 6 and the conductive layer 22 to a predetermined thickness (for example, 0.1 μm). In this case, chromium is used as the gate material and has a form shown in FIG. The gate material is etched into a desired shape by ion milling to form a gate electrode 8. (Step 13) The gate material is etched at a predetermined angle to form the gate electrode 8. The form of the gate electrode 8 is shown in Fig. 2D. The space layer 20 is etched to a predetermined depth. (Step 14) The space layer 20 is etched to a predetermined depth by a wet etching method so as to be spaced apart from the gate electrode 8 and the emitter 4 by a predetermined width. The emitter layer 4 and the resistive layer 18 are etched to a predetermined depth to form an emitter portion. (Step 15) The emitter layer 4 and the resistive layer 18 are etched to a predetermined depth to form an emitter portion. The emission of electrons occurs at the emitter part. However, in the above method, the ion milling method affects other electrode portions or materials with incident ions, and forms a gate material thereon by etching only a specific portion to a specific depth as shown in FIG. There are many difficulties in realizing this. In addition, in order to form the gate electrode in the structure as shown in FIG. Therefore, there is a need for a field emission device and a method of manufacturing the same that can increase the field emission efficiency while simplifying the manufacturing process.

Accordingly, it is an object of the present invention to provide a field emission device and a method of manufacturing the same configured to increase the field emission efficiency.

1 is a view showing a procedure for manufacturing a field emission device according to the prior art.

2 is a view showing a procedure for manufacturing another field emission device according to the prior art.

3 is a view showing a method of manufacturing a field emission device according to the present invention.

4 is a view showing a field emission device according to a first embodiment of the present invention.

FIG. 5 is an enlarged view of a portion of FIG. 4; FIG.

6 is a view showing a field emission device according to a second embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

2,30 substrate 4,32 emitter electrode

6,36,38,40 Insulation layer 8,44 Gate electrode

12: field emission tip 14: tip material

16: separation metal layer 18: resistance layer

20: space layer 42: seed layer

In order to achieve the above object, the field emission device according to the first embodiment of the present invention includes an emitter electrode formed in a planar shape on the top of the substrate, an emitter having an electron emission part formed in a planar shape on the emitter electrode, A planar gate electrode for focusing electrons emitted from the electron emission unit, an insulating layer for electrically isolating the emitter and the gate electrode, and an anode electrode for inducing emitted electrons.

In addition, the field emission device according to the second embodiment of the present invention, an emitter electrode formed in an annular shape on top of the substrate, an emitter having an electron emission portion formed in an annular shape on top of the emitter electrode, and in the electron emitting portion An annular gate electrode focusing the emitted electrons, an insulating layer electrically separating the emitter and the gate electrode, and an anode electrode inducing the emitted electrons.

In addition, the method for manufacturing a field emission device according to the present invention, the first step of forming an emitter electrode, an emitter layer and the first to third insulating layers to a predetermined thickness on the substrate, and the third insulating layer After etching to form a second step of forming a seed layer on top of the second and third insulating layers, and etching the second insulating layer to a predetermined depth, and then forming a gate electrode on the seed layer And a fourth step of etching the first insulating layer, the emitter layer, and the emitter electrode in a desired shape.

Other objects and features of the present invention other than the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

With reference to Figures 3 to 6 will be described a preferred embodiment of the present invention.

3, a method of manufacturing a field emission device according to the present invention is shown.

The emitter electrode 32, the emitter layer 34, and the first to third insulating layers 36, 38, and 40 are formed on the substrate 30 to have a predetermined thickness. (21st step) Referring to FIG. 3A, first, the emitter electrode 32 is formed on the substrate 30 to have a predetermined thickness. Subsequently, the emitter layer 34 is formed on the emitter electrode 32 with a predetermined thickness. Next, the first to third insulating layers 36, 38, and 40 are sequentially formed to have a predetermined thickness. In this case, the first to third insulating layers 36, 38, and 40 have selectivity during the etching process described later. That is, even if one insulating layer is etched, the other insulating layer is not etched. The third insulating layer 40 is etched to a desired shape. (Step 22) The third insulating layer 40 is etched until the second insulating layer 38 is exposed, as shown in FIG. At this time, the second insulating layer 38 has a selectivity and is not etched. The seed layer 42 is formed on the second and third insulating layers 38 and 40. (Step 23) The seed layer 42 is formed by the first and third insulating layers 38, by a catalytic deposition process using palladium (Pd) or a vacuum deposition method and a sputtering method using gold (Au), silver (Ag), or the like. The seed layer 42 is formed on top of the 40. A seed layer 42 formed as a discontinuous film by the above methods is shown in Fig. 3C. The second insulating layer 38 is etched to a predetermined depth. (Step 24) Referring to FIG. 3D, the second insulating layer 38 is etched to a predetermined depth until the first insulating layer 36 is exposed. In this case, the seed layer 42 formed on the second insulating layer 38 is removed by etching the second insulating layer 38. In this case, by etching the second insulating layer 36 to a predetermined depth, the second insulating layer 38 functions as a space that spaces the gap between the emitter layer 34 and the gate electrode 44 to a predetermined width. Will have The gate electrode 44 is formed on the seed layer 42. (Step 25) Referring to FIG. 3E, nickel (Ni), copper (Cu), and an alloying material thereof (for example, NiB) are formed on the seed layer 42 using the electroless plating method. , NiP, etc.) are formed to form the gate electrode 44. The first insulating layer 36, the emitter layer 34, and the emitter electrode 32 are etched to a desired shape. (Step 26) As shown in FIG. 3F, first, the first insulating layer 36 is etched to a desired shape until the emitter layer 34 is exposed. Subsequently, the emitter layer 34 is etched into a desired shape until the emitter electrode 32 is exposed, as shown in FIG. The emitter electrode 32 is etched to a desired shape. As shown in (h) of FIG. 3, the emitter electrode 32 is etched in a desired shape until the substrate 30 is exposed. In this process, the emitter layer 34 has an electron emission portion for emitting electrons, and can form an electron emission portion having a sharper edge than a field emission tip manufactured by a conventional spin method. By the same method as described above, it is possible to manufacture a linear field emission device or an annular field emission device. In addition, since the process itself is a process suitable for large area, it is possible to manufacture a large area field emission device. In addition, the self-align (Self Align) in the process can be used to simplify the process. In addition, the emitter having the above structure can form a sharper electron emitting portion than the field emission tip using the conventional spin method, thereby lowering the driving voltage.

Referring to FIG. 4, the field emission device according to the first exemplary embodiment of the present invention has an emitter electrode 32 formed in a planar shape on the substrate 30, and a planar shape formed on the emitter electrode 32. An emitter 34 having an electron emitting portion, a planar gate electrode 44 for focusing the emitted electrons, and insulating layers 36, 38, and 40 for electrically isolating the emitter 34 and the gate electrode 44; And a screen portion 46 on which a phosphor that collides with the emitted electrons to generate light and a planar anode electrode that induces emitted electrons are formed. When a driving voltage is applied between the gate electrode 44 and the emitter 34, electrons are emitted from the electron emission unit. Referring to FIG. 5, when a driving voltage is applied between the gate electrode 44 and the emitter 34, an electric field corresponding to the driving voltage is formed between the electron emission unit and the gate electrode 44. At this time, electrons are emitted from the electron emission unit, and the emitted electrons are emitted with a trajectory perpendicular to the equipotential lines. The trajectory and equipotential lines of the emitted electrons are shown in FIG. 5. The emitted electrons are guided to the anode electrode formed on the screen part 46 to collide with the phosphor formed on the screen part 46 to generate light. In this case, the first insulating layer 36 is formed on the emitter 34 to prevent the electrons emitted from the electron emission unit from being directly induced to the gate electrode 44. The second insulating layer 38 is formed on the first insulating layer 36 to serve as a space for separating the emitter 34 and the gate electrode 44 to a predetermined width, and the emitter 34 ) And the gate electrode 44 are electrically isolated. The third insulating layer 40 supports the gate electrode 44 to have a predetermined shape and serves to electrically isolate the emitter 34 from the gate electrode 44. The electron emission portion is formed more sharply than the field emission tip using the conventional spin method, thereby lowering the driving voltage. That is, the electron emission efficiency is increased. In addition, the emitter electrode is formed with a resistive layer in a predetermined manner to achieve stability of the emitter. The field emission device according to the first embodiment of the present invention has a linear structure.

Referring to FIG. 6, the field emission device according to the second embodiment of the present invention is formed in an annular shape on the substrate 30 and has an emitter 34 having an electron emission portion, and an annular gate electrode for focusing the emitted electrons. 44 and an insulating layer 36 which electrically isolates the emitter 34 and the gate electrode 44 from each other. When a driving voltage is applied between the gate electrode 44 and the emitter 34, electrons are emitted from the electron emission unit. The emitted electrons are induced by the anode electrode and collide with the phosphor to generate light. Since the field emission device according to the second embodiment of the present invention is formed in an annular structure to have the same function as the first embodiment, detailed description thereof will be omitted.

As described above, the field emission device according to the present invention has an advantage in that the electron emission unit is sharply formed to lower the driving voltage and improve the electron emission efficiency.

In addition, the manufacturing method of the field emission device according to the present invention has the advantage of simplifying the process because it uses a self alignment (Self Align) in the manufacturing process.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention.

For example, in the embodiments of the present invention, although the field emission device is formed in a linear or annular structure, it will be appreciated by those skilled in the art that the field emission device may have any structure according to the intention of the designer. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (14)

An emitter electrode formed in a planar shape on top of the substrate, An emitter having a planar shape on the emitter electrode and having an electron emission unit; A planar gate electrode for focusing electrons emitted from the electron emission unit; An insulating layer electrically insulating the emitter from the gate electrode; And an anode electrode for inducing the emitted electrons. The method of claim 1, The insulating layer, A first insulating layer formed on the emitter, A second insulating layer formed on the first insulating layer; And a third insulating layer formed on the second insulating layer. The method of claim 2, And the first insulating layer prevents electrons emitted from the electron emission unit from being guided to the gate electrode. The method of claim 2, And the second insulating layer separates the emitter and the gate electrode by a predetermined width. An emitter electrode formed in an annular shape on top of the substrate, An emitter formed in an annular shape on top of the emitter electrode and having an electron emission unit; An annular gate electrode focusing electrons emitted from the electron emission unit; An insulating layer electrically insulating the emitter from the gate electrode; And an anode electrode for inducing the emitted electrons. A first step of forming an emitter electrode, an emitter layer, and first to third insulating layers in a predetermined thickness on the substrate; Etching the third insulating layer to a desired shape, and then forming a seed layer on the second and third insulating layers; Etching the second insulating layer to a predetermined depth, and then forming a gate electrode on the seed layer; And a fourth step of etching the first insulating layer, the emitter layer, and the emitter electrode in a desired form. The method of claim 6, In the first step, The method of claim 1, wherein the first to third insulating layers have a selectivity during an etching process. The method of claim 6, And the seed layer is formed by a catalyst imparting process in the second step. The method of claim 8, The seed layer manufacturing method of the field emission device characterized in that the material of Pd. The method of claim 6, And forming the seed layer by vacuum deposition in the second step. The method of claim 10, And a material of the seed layer is at least one of Au, Ag, and Pt. The method of claim 6, And a gate electrode is formed by electroless plating in the third step. The method of claim 12, The gate electrode is a material of the field emission device, characterized in that at least one of Ni, Cu, NiB and NiP. The method of claim 6, And in the fourth step, by forming the electron-emitting part by etching the emitter layer in a predetermined shape.