KR20000008923U - Tester of memory semiconductor chip - Google Patents

Abstract

The present invention discloses a tester for testing read and write operations of a memory semiconductor chip and a memory semiconductor chip tester capable of achieving efficiency above the maximum frequency of the system regardless of signal delay caused by the wire of the test board. The tester is a tester board on which the memory semiconductor is mounted and a tester of a semiconductor chip which transmits read and write signals to the input / output terminals of the memory chip in order to test read and write operations of the memory semiconductor chip. A separate channel for transmitting read and write signals to the terminal and two separate wires formed on the tester board and connected to the input / output terminals of the semiconductor chip.

Description

Tester of memory semiconductor chip

The present invention relates to a tester for reading and writing tests of a memory semiconductor, and more particularly, to a package board for a test system capable of realizing a maximum frequency irrespective of signal delay caused by a wire of a system or test board.

In the process for semiconductor, there is a test process in the final process, and the equipment used in response to this is called a tester. Prior to moving from the wafer state to the assembly process, chip failure and repair can be performed on the wafer. The test equipment used for this is called a fab line tester, and the test equipment for classifying pre-shipment and grade of a product on a package is called an assembly tester. If the tester is reclassified by device, it is divided into a memory tester, a mixed signal tester, a linear tester, and a discrete tester.

Among these testers, the testing items of memory devices can be largely divided into DC-test and functional test. The functional test, which tests the function checking pattern under various voltage and timing conditions, doubles as an AC test.

The DC-test measures the direct current characteristics of the memory. It connects the DC-measuring device to the terminal under test and measures the specified voltage (current) with the DC-measuring device. Measurement items include open / short, input current, output voltage, power supply current, and the like.

In the AC test, a pulse signal is applied to an input terminal to measure operating characteristics such as input / output carrying delay time, start of output signal, and end time.

The functional test is a test of the read / write function and the mutual interference of each memory cell at the actual operating speed of the integrated circuit memory. A device for testing a pulse obtained by converting a test pattern generated from a pattern generator to a prescribed level (DUT: Device Under Test, hereinafter referred to as "DUT") to compare the output signal of the DUT with a specified level. The result of the comparison is compared with the expected output pattern generated by the pattern generator to test the success of the operation.

1 is a schematic diagram of a tester of a memory semiconductor chip according to a conventional embodiment, in which a device 18 under test is connected to a tester package board 16 by a short channel 20. The driver 12 of the tester transmits read and write data through this short channel, and tests read and write operations (“RMW”) to the device under test through the input / output terminal 18a of the device under test. .

In the RMW mode of a memory device with multiple inputs and outputs, a dead zone equals twice the sum of the wire delay of the tester and the wire delay of the tester board when performing a write operation after a read operation. Affects.

This fact will be described with reference to the signal timing diagram of FIG. 2.

After the read data from the device under test (Dut) is loaded on the channel 20, the tester's driver loads the write data on the channel to perform a write operation, the test wire delay + board wire delay time Data collisions occur during the process. In order to prevent the error due to the influence of the tester environment, as shown in the timing diagram of FIG. 3, after the data read operation, write after a timing corresponding to twice the tester wire delay + board wire delay time ("tpd"). The action must be performed.

As described above, the conventional tester tests the read and write operation modes through the short channel, and thus includes the error of the tester.

In addition, due to data collision, the efficiency of the system is degraded for two times the tester wire delay + board wire delay, making it difficult to realize the maximum frequency of the system when testing a high-speed device.

Accordingly, an object of the present invention is to provide a test package capable of achieving efficiency above a maximum frequency of a system regardless of signal delay caused by wires.

1 is a schematic configuration diagram of a tester of a memory semiconductor chip according to a conventional embodiment.

2 is a waveform diagram of each signal for explaining a data collision phenomenon in the tester of FIG.

3 is a timing diagram of the tester of FIG.

4 is a schematic configuration diagram of a tester of a memory semiconductor chip according to an embodiment of the present invention.

5 is a waveform diagram of each signal showing the input and output of the device under test and the tester in two channels in the tester of FIG.

6 is a timing diagram of the tester of FIG.

(Explanation of symbols for the main parts of the drawing)

42: Tester's Driver 44: Tester's Receiver

46: tester board 48: device for the tester

48a: I / O terminal 50, 51: wire

50a, 51a: resistor

In order to achieve the above object, the tester of the semiconductor chip of the present invention, the tester board on which the memory semiconductor is mounted and the read and write signals to the input and output terminals of the memory chip to test the read and write operation of the memory semiconductor chip A tester for transmitting semiconductor chips, comprising: a separate channel for transmitting read and write signals to input and output terminals of the memory semiconductor, and two separate wires formed on the tester board and connected to input and output terminals of the semiconductor chip. .

The package board for the tester system of the present invention eliminates dead zones caused by data collisions due to wire delays between read and write data when testing multiplexed devices.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a schematic configuration diagram of a tester for testing read and write operations of a memory semiconductor chip according to an embodiment of the present invention, and includes two input / output terminals (I / O Pin: 48a) of the semiconductor chip 48 under test. Wires are connected, and each wire is connected to the driver 42 and the receiver 44 of the tester through separate channels, that is, channel 1 54 and channel 2 46. Only an input signal is transmitted through channel 1 54, and only an output signal is transmitted through channel 2 56.

Referring to FIG. 5, through the channel 1 54, an output signal read from the semiconductor chip under test (DUT) is transmitted by driving the read mode, and the TPD is transmitted to the driver 42 of the tester. As much delay occurs. On the other hand, through the channel 2 56, a write signal is transmitted to the semiconductor chip 48 under test by driving in the write mode, and the signal 50 is connected to the wire 50, on the channel 2 56 and the tester board 52. A signal delay occurs while passing through 51, and a time delay occurs until input to the semiconductor chip 48 being tested. Therefore, a dead zone occurs as shown in FIG. 5. However, in the tester of the present invention, the channel 1 54 and the channel 2 56 are separated separately, and two separate wires 50 and 51 are connected to the input / output terminal 48a of the semiconductor chip 48 under test. ) Is on the board, thus preventing data collisions.

Referring to FIG. 6, since an input Din and an output Dout enter different channels, data collision due to Pd in channel 1 and Pd in channel 2 is prevented. Therefore, regardless of the wire delay of the system and the delay on the package board, performance over the system maximum frequency can be obtained, which is effective for testers of high-speed memory semiconductor devices such as SDRAM, SLDRAM, RDRAM, and DDR.

Meanwhile, referring back to FIG. 4, since two transmission lines 50 and 51 are connected to one input / output terminal 48a of the semiconductor chip 48 under test, impedance mismatching may occur. In order to prevent this, it is preferable to install a resistor R2 between the node where the two wires 50 and 51 are connected on the package board 52 and the input / output terminal of the device under test. The resistance of the resistor R2 is configured to have 25Ω, for example, when the resistance of each of the resistors 50a, 51a connected to the two wires 50, 51 is 50Ω.

As described above, the tester of the semiconductor chip according to the present invention eliminates data collision by providing channels for transmitting read and write data separately. In this way, the test error can be eliminated and the performance above the maximum frequency can be obtained, so that the test of the high speed semiconductor chip can be performed accurately and effectively.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Therefore, hereinafter, the scope of the utility model registration request can be understood to include all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (3)

A tester board on which the memory semiconductor is mounted and a tester of a semiconductor chip which transmits a read and write signal to an input / output terminal of the memory chip to test read and write operations of the memory semiconductor chip, wherein the readout is written to an input / output terminal of the memory semiconductor. And a separate channel for transmitting a write signal and two separate wires formed on the tester board and connected to input / output terminals of the semiconductor chip. 2. The resistor of claim 1, wherein the two wires of the package board are connected to each other at one node, and are connected to an input / output terminal of the semiconductor chip, and a resistor provided between the node connected to the wire and the input / output terminal of the semiconductor chip. The tester of the memory semiconductor chip comprising a. The tester of claim 2, wherein when the resistance of each of the two wires is 50 Ω, the resistance has a resistance of 25 Ω.