KR20000008473A - Frequency synthesizing device using low passing pll(phase locked loop) ic inside mobile communication terminal - Google Patents

Abstract

PURPOSE: A frequency synthesizing device using low passing PLL IC inside a mobile communication terminal is provided to decrease a locking time and improve quality such as phase noise and phase error and so on. CONSTITUTION: The frequency synthesizing device installs; a control unit(10) controlling an entire working; a fixed frequency generating unit(20) generating the fixed frequency for making a standard frequency of PLL IC down within 100MHz; a channel frequency generating unit(30) generating the channel frequency for transmitting; a local frequency generating unit(40) generating the local frequency for receiving; a first mixer(25) outputting the standard frequency within 100MHz to the channel frequency generating unit by mixing the channel frequency; and a second mixer(35) outputting the standard frequency within 100MHz to the local frequency generating unit by mixing the local frequency.

Description

Frequency Synthesizing Device Using Low Frequency PLEL IC in Mobile Communication Terminal

According to the present invention, in designing a frequency synthesizer for using a high frequency channel frequency resource in an RF transceiver in a mobile communication terminal, a locking time is realized by implementing a frequency synthesizer using a low-pass phase locked loop (PLL) IC. The present invention relates to a frequency synthesizer using a low-pass PLL IC in a mobile communication terminal to reduce time and improve characteristics such as phase noise and phase error.

In general, an RF transceiver in a mobile communication terminal uses a frequency synthesizer by a PLL IC to generate a desired channel frequency.

These PLL ICs generate a local frequency signal according to the internal reference frequency, and the time taken to move or jump from one channel to another depending on how much of the PLL IC's internal reference frequency is selected, that is, the locking time. Will be determined.

In the conventional Digital-Trunked Radio System (hereinafter, referred to as 'D-TRS') terminal, since the channel spacing is 25 kHz, the frequency synthesizer was designed using the reference frequency of the PLL IC as 25 kHz. It was not easy to create a TRS channel by adopting a direct modulation method, and the receiver also had to make and use a separate IF SAW filter in selecting an intermediate frequency to be 25 kHz.

In addition, the D-TRS terminal using the frequency hopping code division multiple access (FHMA) method could not satisfy the fast locking time characteristic when the channel jumps.

Using a single PLL IC as described above, the frequency problem, the locking time, the phase noise, and the phase error could not be satisfied.

As a result, since the conventionally permitted frequency interval is 25 kHz and the end position is 12.5 kHz, a frequency synthesizing apparatus having this 12.5 kHz as the reference frequency of the PLL IC was designed.

That is, when the reception frequency of channel 1 of the D-TRS vehicle terminal is 851.0125 MHz and the first intermediate frequency is 83.25 MHz, the local frequency can be divided by an integer for channel 1 and the above 12.5 kHz that can satisfy the 25 kHz channel spacing. The reference frequency was used to generate a local frequency of 934.2625 MHz.

However, the frequency synthesis as described above, while the hop time between the channels is 1.9 ms, the locking time is satisfactory, while the locking time is too low to satisfy the phase noise characteristic.

In other words, the larger the value of the N-counter in the PLL IC, the worse the phase noise. The higher the channel frequency is, the larger the value of the N-counter is.

On the other hand, based on the conventional results as described above to improve the phase noise characteristics by increasing the reference frequency inside the PLL IC to 100kHz.

As in the local frequency generator of the receiver in the D-TRS terminal shown in FIG. 1, when the first PLL unit 1 generates a frequency of 878.2 MHz using 100 kHz, which is four times the channel interval 25 kHz, as a reference frequency, The divider 2 divides 878.2 MHz by 4 to generate a frequency of 219.55 MHz for one channel, followed by 714.7125 MHz generated by the second PLL unit 3 and the divider 2. The 219.55 MHz generated through the first mixer 4 is mixed to generate a local frequency of 934.2625 MHz.

Then, the second mixer 5 outputs the first intermediate frequency of 83.25 MHz by mixing the reception frequency 851.0125 MHz of the channel 1 and 934.2625 MHz of the first mixer 4.

However, such a conventional frequency synthesizer also needs to use a separate divider (2) and a first mixer (4) to raise the reference frequency to 100 kHz, and also if the VCTCXO frequency must use 18.45 MHz for the FHMA algorithm, To use it as an internal reference frequency, the 18.45MHz / 100kHz value is not an integer. To compensate for this, a circuit implementing 16.4MHz, which can be an integer value, must be added again.

As described above, the conventional technology described above is not only impossible to simultaneously satisfy the locking time and phase noise characteristics by using one PLL IC, but also the method of raising the reference frequency to 100 kHz is complicated by many circuits. There was a problem that the size of the terminal is increased.

The present invention has been made to solve the above problems, the object of which is to generate using a mixer in the design of a frequency synthesizer for using the high frequency channel frequency resources in the RF transceiver in the mobile communication terminal Frequency synthesizer using low-pass PLL IC in mobile communication terminal to reduce locking time and improve characteristics such as phase noise and phase error by implementing low-cost PLL IC operating within 100MHz far below channel frequency band Is in providing.

1 is a block diagram of a local frequency generator using two PLL ICs in a receiver of a conventional mobile communication terminal.

2 is a block diagram of a frequency synthesizing apparatus using PEL IC of a low band in a mobile communication terminal according to the present invention;

<Description of the symbols for the main parts of the drawings>

10: control unit 20: fixed frequency generator

30: channel frequency generator 40: local frequency generator

21,31,41: first to third PLL sections 22,32,42: first to third loop filters

23, 33, 43: first to third VCO 25: first mixer

35: 2nd mixer 34, 44: 1st, 2nd LPF

In order to achieve the above object, a frequency synthesizer using a low frequency PLL IC in a mobile communication terminal according to the present invention may be obtained by mixing a channel frequency output from a transmitter and a fixed frequency for reducing the reference frequency of the PLL IC in the transmitter within 100 MHz. By lowering the frequency, the reference frequency of the PLL IC in the transmitter is operated within 100 MHz.The receiver also mixes the local frequency for channel formation and the fixed frequency to down the reference frequency of the PLL IC in the receiver within 100 MHz. It is characterized in that the reference frequency of the PLL IC in the receiver operates within 100MHz.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the frequency synthesizer using a low-frequency PLL IC in the mobile communication terminal according to the present invention.

2 is a block diagram of a frequency synthesizing apparatus using a low-pass PLL IC in a mobile communication terminal according to the present invention. The control unit 10 controls the overall operation of the frequency synthesizing apparatus according to the present invention, and the control unit 10. A fixed frequency generator 20 for generating a fixed frequency for lowering the reference frequency of each PLL IC used in the channel frequency generator on the transmitting side and the local frequency generator on the receiving side within 100 MHz according to the control operation of the transmitter; A channel frequency generator 30 generating a transmission channel frequency according to a control operation of the controller 10 and a control operation of the fixed frequency generator 20, and a control operation of the controller 10 and generation of the fixed frequency. Local frequency generator 40 for generating a local frequency for reception according to the control operation of the unit 20, the fixed frequency generated by the fixed frequency generator 20 and the channel frequency generator 30 The first mixer 25 for mixing the channel frequency generated in the) to output a reference frequency within 100MHz to the channel frequency generator 30, and the fixed frequency and the local frequency generated by the fixed frequency generator 20 The second mixer 35 is configured to mix the local frequencies generated by the generator 40 and output a reference frequency within 100 MHz to the local frequency generator 40.

The fixed frequency generator 20 is the channel frequency generator 30 and the local frequency generator based on data, clock, and a first enable signal output from the controller 10. A first PLL unit 21 for outputting a phase detection voltage control signal so as to generate a fixed frequency for lowering the reference frequency of the PLL IC within 100 MHz within 40; and a voltage output from the first PLL unit 21; The first PLL unit 21 according to a first loop filter 22 for controlling a control signal to satisfy a local specification characteristic and a voltage control signal passing through the first loop filter 22. Voltage control oscillator (VCO) for outputting a fixed frequency for lowering the reference frequency of the PLL IC in the channel frequency generator 30 and the local frequency generator 40 within 100 MHz. 23).

The channel frequency generator 30 outputs a phase detection voltage control signal to lock the channel frequency to be generated at the transmission side according to the data, the clock, and the second enable signal output from the controller 10. 2 PLL section 31, the second loop filter 32 and the second loop filter 32 so that the voltage control signal output from the second PLL section 31 satisfies the local specification characteristics, A second low pass filter for removing a high order frequency generated in the output signal of the first mixer 25 and a second VCO 33 for outputting a channel frequency to be generated at the transmitting side according to the voltage control signal; Hereinafter referred to as 'LPF' 34.

In addition, the local frequency generator 40 outputs a phase detection voltage control signal to lock to a local frequency to be generated at a receiving side according to data, a clock, and a third enable signal output from the controller 10. The third loop filter 42 and the third loop filter 42 so that the voltage control signal output from the third PLL unit 41 satisfies a local specification characteristic. A third VCO 43 for outputting a local frequency to be generated at the receiving side according to the voltage control signal that has passed, and a second LPF 44 for removing high-order frequencies generated at the output signal of the second mixer 35. It is composed.

Referring to the operation of the frequency synthesizer using a low-pass PLL IC in the mobile communication terminal configured as described above are as follows.

First, the first PLL unit 21 in the fixed frequency generator 20 is a second terminal used by the transmitter and the receiver for channel formation according to the data, the clock, and the first enable signal output from the controller 10. A fixed frequency is generated to lower the reference frequency supplied thereto so that the PLL section 31 and the third PLL section 41 can be used as a low-pass PLL IC.

That is, the first PLL unit 21 in the fixed frequency generator 20 generates a phase detection voltage control signal through the first loop filter 22 according to the data, the clock, and the first enable signal of the controller 10. Output to 1 VCO (23).

In this case, the first loop filter 22 may satisfy the local specification characteristics such as phase noise, locking time, phase error, and spurious characteristics of the phase detection voltage control signal output from the first PLL unit 21. do.

Subsequently, in response to the phase detection voltage control signal of the first PLL unit 21 that has passed through the first loop filter 22, the first VCO 23 may be configured to reference the PLL IC of the transmission / reception side PLL IC. A fixed frequency for reducing the frequency to within 100 MHz is fed back to the first PLL unit 21 and simultaneously output to the first mixer 25 and the second mixer 35.

Then, in the channel frequency generator 30 for forming 600 channels, the second PLL unit 31 generates 800 MHz according to the data, the clock, and the second enable signal output from the controller 10. The phase detection voltage control signal is output to the second VCO 33 through the second loop filter 32 so as to lock at the channel frequency of the band.

At this time, the second loop filter 32 also allows the phase detection voltage control signal output from the second PLL unit 31 to satisfy local specification characteristics.

Subsequently, the second VCO 33 outputs the channel frequency of the 800 MHz band to be generated at the transmitting side according to the phase detection voltage control signal passed through the second loop filter 32.

Accordingly, the first mixer 25 has a channel frequency output from the second VCO 33 in the channel frequency generator 30 and a fixed frequency output from the first VCO 23 in the fixed frequency generator 20. By mixing down the channel frequency of the 800MHz band of the second VCO 33 to a frequency within 100MHz to output a reference frequency within 100MHz to the second PLL unit 31.

At this time, the first LPF 34 removes the higher-order frequency generated in the output signal of the first mixer 25.

Accordingly, the second PLL unit 31 can use a low-pass PLL IC, and since the PLL IC is operated at a frequency within 100 MHz, it is possible to improve phase noise and locking time characteristics.

In addition, the third PLL unit 41 is also output according to the data, the clock, and the third enable signal of the controller 10 in the local frequency generator 40 generating a local frequency of 900 MHz band for forming 600 channels. The third VCO 43 outputs the local frequency of the 900 MHz band to be generated at the receiving side to the second mixer 35 by the phase detection voltage control signal of the signal.

Then, the second mixer 35 has a local frequency output from the third VCO 43 in the local frequency generator 40 and a fixed output from the first VCO 23 in the fixed frequency generator 20. The frequencies are mixed to lower the local frequency in the 900 MHz band to a reference frequency within 100 MHz, and then output to the third PLL unit 41 through the second LPF 44.

Accordingly, the third PLL unit 41 in the receiver can also use a low-pass PLL IC, and since the PLL IC is operated at a frequency within 100 MHz, it is possible to improve phase noise and locking time characteristics.

Meanwhile, in the case of the D-TRS terminal, 600 transmission channels are 806.0125 MHz to 820.9875 MHz, and reception channels are 851.0125 MHz to 865.9875 MHz, each 15 MHz band, and an intermediate frequency of the receiver is 83.25 MHz. In order to shorten the time it takes to hopping the signal, the fixed output output from the first VCO 23 in the fixed frequency generator 20 is divided into low, middle, and high bands by 5 MHz. Set the frequency differently.

In order to improve the phase noise characteristic, the reference frequency of the PLL IC in the first PLL unit 21 is set to 56.25 kHz, and the reference frequencies of the PLL ICs in the remaining second PLL unit 31 and the third PLL unit 41 are set to 56.25 kHz. Is 25 kHz for channel formation.

In the case of the D-TRS terminal having the above condition, the first PLL unit 21 is driven for the low band channel 1 to oscillate a fixed frequency of 899.6625 MHz from the first VCO 23, and the channel frequency generator ( The first mixer 25 inputs a channel frequency of 806.0125 MHz and a fixed frequency of 8.999.6625 MHZ generated by the second VCO 33 into the first mixer 25 to lower the fixed frequency of 899.6625 MHz to 93.65 MHz. It outputs to the part 31 again, and the drive of this 2nd PLL part 31 produces | generates the transmission channel 1 of 806.0125 MHz.

Using the frequency synthesizer of the present invention, configuring at 93.65MHz to 88.675MHz can make the locking time much shorter than constructing the PLL at 806.0125MHz to 810.9875MHz, and reduce the cost by using the low-frequency IC. You can do it.

As described above, the present invention implements a low-cost PLL IC operating within 100 MHz far below the channel frequency band to be generated by using a mixer to reduce locking time and improve characteristics such as phase noise and phase error. There is an effect that can be made, and the circuit can be simplified through a relatively simple structure has the advantage of reducing the size of the terminal.

Claims (4)

The reference frequency of each PLL IC used in the control unit 10 for controlling the overall operation of the frequency synthesizer and the channel frequency generator on the transmitting side and the local frequency generator on the receiving side in accordance with the control operation of the controller 10. A fixed frequency generator 20 for generating a fixed frequency for down to 100 MHz and a channel frequency for generating a channel frequency for transmission according to a control operation of the controller 10 and a control operation of the fixed frequency generator 20. A local frequency generator 40 for generating a reception local frequency according to the generator 30, a control operation of the controller 10, and a control operation of the fixed frequency generator 20, and the fixed frequency generator A first mixer 25 for mixing the fixed frequency generated at 20 and the channel frequency generated at the channel frequency generator 30 to output a reference frequency within 100 MHz to the channel frequency generator 30; A second mixer for mixing the fixed frequency generated by the fixed frequency generator 20 and the local frequency generated by the local frequency generator 40 to output a reference frequency within 100 MHz to the local frequency generator 40 ( 35) A frequency synthesizing apparatus using PEL IC of a low band in a mobile communication terminal, characterized in that consisting of. The channel frequency generator 30 and the local frequency generator 40 according to the data, the clock, and the first enable signal output from the controller 10. A first PLL unit 21 for outputting a phase detection voltage control signal to generate a fixed frequency for lowering the reference frequency of the PLL IC within 100 MHz, and a voltage control signal output from the first PLL unit 21 The first PLL unit 21 is connected to the channel frequency generator 30 according to the voltage control signal passing through the first loop filter 22 and the first loop filter 22 to satisfy the local specification characteristic. Frequency using the low frequency PLEL IC in the mobile communication terminal, characterized in that it comprises a first VCO (23) for outputting a fixed frequency for reducing the reference frequency of the PLL IC within the local frequency generator 40 within 100MHz Synthesis device. The phase detection voltage of claim 1, wherein the channel frequency generator 30 locks to a channel frequency to be generated at a transmitter according to data, a clock, and a second enable signal output from the controller 10. A second PLL unit 31 for outputting a control signal, a second loop filter 32 such that the voltage control signal output from the second PLL unit 31 satisfies a local specification characteristic, and the second loop filter A second VCO 33 for outputting a channel frequency to be generated at the transmitting side according to the voltage control signal passing through the 32, and a first LPF for removing the higher order frequency generated in the output signal of the first mixer 25; A frequency synthesizing apparatus using PLEL IC of a low range in a mobile communication terminal, characterized by comprising (34). The phase detection voltage of claim 1, wherein the local frequency generator 40 locks to a local frequency to be generated by a receiver according to data, a clock, and a third enable signal output from the controller 10. A third PLL unit 41 for outputting a control signal, a third loop filter 42 such that the voltage control signal output from the third PLL unit 41 satisfies a local specification characteristic, and the third loop filter A third VCO 43 for outputting a local frequency to be generated at the receiving side according to the voltage control signal passed through 42, and a second LPF for removing the higher order frequency generated in the output signal of the second mixer 35; A frequency synthesizing apparatus using PLEL IC of a low range in a mobile communication terminal, characterized by comprising (44).