KR20000007309A - Circuit for generating substrate bias voltage of semiconductor device - Google Patents

Abstract

PURPOSE: A circuit for generating a substrate bias voltage of a semiconductor device is provided to generate a substrate bias voltage to be able to regulate from outside. CONSTITUTION: The circuit for generating a substrate bias voltage offers; a launching circuit(100); a pumping circuit(200); a detecting circuit unit(300) containing a switch control signal generating circuit(310), a first load circuit unit(320), a second load circuit unit(330), and a detecting circuit(340). The first and the second load circuit units(320,330) control the detected power voltage to be a standard of the voltage detecting of the detecting circuit(340) by the control of the switch control signals(S1,S2,...,S7,S8) supplied from the switch control signal generating circuit(310). The detecting circuit(340) detects the voltage level of the substrate bias voltage(VBB) output from the pumping circuit(200) by having the detecting voltage level, the standard, controlled by the first and the second load circuits(320,330).

Description

A CIRCUIT FOR GENERATING SUBSTRATE BIAS VOLTAGE OF SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a circuit for generating substrate bias voltage for generating an externally adjustable substrate bias voltage.

The substrate bias voltage generator circuit is a circuit applied to a silicon substrate and generates a substrate bias voltage (VBB) having a negative voltage level. The first reason for supplying the substrate bias voltage VBB onto the semiconductor substrate is that the PN junctions of the respective elements in the semiconductor memory device are partially forward biased. This is to prevent data loss or latch-up of the memory cells by preventing the data from being lost. The second reason is to stabilize the semiconductor memory device by reducing the change in the threshold voltage of the MOS transistor due to the back gate effect. The third reason is that by increasing the threshold voltage of the parasitic MOS transistor, there is no need to increase the concentration of the channel stop implant under the field oxide charge and reverse bias. This is because (reverse bias) is applied, thereby reducing the PN junction capacitance of the MOS transistor, thereby improving the operation speed of the circuit.

Referring to FIG. 1, the substrate bias voltage generation circuit according to the related art includes an oscillation circuit 10, a pumping circuit 20, and a detection circuit 30. The oscillation circuit 10 outputs an oscillation signal CLK having a predetermined frequency under the control of a detection signal DS supplied from the detection circuit 30. The pumping circuit 20 is connected between the oscillation circuit 10 and a semiconductor substrate (not shown) and has a negative voltage level under control of the oscillation signal CLK. ) The detection circuit 30 is connected between the semiconductor substrate and the oscillation circuit 10, detects a voltage level of the semiconductor substrate, and outputs the detection signal DS as a detection result.

However, the substrate bias voltage generation circuit may not output the substrate bias voltage VBB desired by a designer. When the semiconductor memory device fails, the circuits must be analyzed while varying the substrate bias voltage VBB. In this case, the substrate bias voltage VBB is used forcing by using a driver or a power source of an automatic memory test system (ATE). That is, in the method of varying the substrate bias voltage VBB, a channel assign of the ATE system is used, and the application of the substrate bias voltage VBB is applied even when a test load board is configured. There is a drawback to be possible.

In addition, the pershing of the substrate bias voltage VBB is possible only in a wafer or ceramic state, where the wafer state is provided on a probe card to connect with the substrate bias voltage pad VBB pad. A pin must be assigned to the ceramic, and in the case of the ceramic, an additional work of bonding to the substrate bias voltage pad VBB pad is required. In particular, the substrate bias voltage generation circuit provided in a sealed package type semiconductor device such as a thin small outline package (TSOP) or a small outline j form (SOJ) is impossible to vary the substrate bias voltage itself. Problems arise.

It is therefore an object of the present invention to provide a substrate bias voltage generator circuit of a semiconductor device for generating an externally adjustable substrate bias voltage.

1 is a circuit diagram of a substrate bias voltage generation circuit according to the prior art; And

2 is a circuit diagram of a substrate bias voltage generation circuit according to the present invention.

* Explanation of symbols on the main parts of the drawings

10, 100: oscillation circuit 20, 200: pumping circuit

30, 300: detection circuit

(Configuration)

According to one aspect of the present invention for achieving the above object, a substrate bias voltage generation circuit is connected to the semiconductor substrate, pumping means for pumping charges to the semiconductor substrate in response to a predetermined oscillation signal; Detection means connected to the semiconductor substrate and detecting a voltage level of the semiconductor substrate on the basis of a predetermined detection voltage level varied by a control signal applied from the outside, and generating a detection signal as a detection result thereof; Oscillating means for generating the oscillating signal in response.

In this embodiment, the detecting means comprises: switch control signal generating means for generating first and second groups of switch control signals in response to the control signal, first load means connected to a power supply voltage, and the first means; A first load means and a switch connected between a predetermined node for outputting the detection voltage and on / off according to the substrate bias voltage, and second load means connected between the node and the ground voltage, Each resistance of the first and second load means is varied by corresponding first and second group of switch control signals such that the detected voltage level is varied.

In this embodiment, the first load means comprises: a first latch circuit portion for latching the first group of switch control signals; and the detected voltage of the node in response to the latched first group of switch control signals. And a first load circuit varying the level.

In this embodiment, the second load means comprises: an inverting circuit portion for inverting the second group of switch control signals, a second latch circuit portion for latching the inverted second group of switch control signals, and the latched said And a second load circuit that varies a voltage level of the detected voltage of the node in response to a second group of switch control signals.

In this embodiment, the first load circuit has a plurality of PMOSs having current paths respectively formed between a power supply voltage and the node and gates respectively controlled by corresponding first group of switch control signals. And a PMOS transistor having a gate controlled by a ground path and a current path formed between the power supply voltage and the node.

In this embodiment, the second load circuit comprises NMOS transistors each having current paths formed between the node and ground voltage and gates respectively controlled by corresponding second group of switch control signals; And an NMOS transistor having a gate controlled by a power supply voltage and a current path formed between the node and the ground voltage.

(Action)

By such an apparatus, the detection voltage level is adjusted by external input signals, whereby the substrate bias voltage supplied to the semiconductor substrate can be adjusted.

(Example)

Hereinafter, the present invention will be described in detail with reference to FIG. 2.

Referring to FIG. 2, the novel substrate bias voltage generator circuit of the present invention provides an oscillator circuit 100, a pumping circuit 200, and a detection circuit unit 300. The detection circuit unit 300 includes a switch control signal generation circuit 310, a first load circuit unit 320, a second load circuit unit 330, and a detection circuit 340. The first and second load circuit parts 320 and 330 are detected by the control of switch control signals S1, S2,..., S7 and S8 supplied from the switch control signal generation circuit 310. The detection voltage level, which is a reference for voltage detection of the circuit 340, is adjusted. The detection circuit 340 adjusts the voltage level of the substrate bias voltage VBB output from the pumping circuit 200 based on the detection voltage level adjusted by the first and second load circuit units 320 and 330. Detect.

Referring to FIG. 2, the substrate bias voltage generation circuit of the present invention includes an oscillation circuit 100, a pumping circuit 200, and a detection circuit unit 300. The oscillation circuit 100 is connected between the detection circuit unit 300 and the pumping circuit 200, and has an oscillation having a predetermined frequency under the control of the detection signal DS output from the detection circuit unit 300. Output the signal CLK. The pumping circuit 200 is connected between the oscillation circuit 100 and a semiconductor substrate (not shown), and the voltage level of the semiconductor substrate is controlled to a predetermined negative level by the control of the oscillation signal CLK. down to a negative voltage level.

The detection circuit unit 300 includes a switch control signal generation circuit 310, a first load circuit unit 320, a second load circuit unit 330, and a detection circuit 340. The switch control signal generation circuit 310 receives the input signals A0, A1, A2 applied from the outside, and controls the input signals A0, A1, A2 and the control by controlling the control signal CON. The load signals S1, S2, ... S7, S8 corresponding to the signal CON are output. The first load circuit unit 320 includes a first latch circuit unit 321 and a first load circuit 322, and the detection circuit (S1) by controlling the switch control signals S1, S2, S3, and S4. The detection voltage level of 340 is adjusted. The first latch circuit unit 321 is connected between the switch control signal generation circuit 310 and the PMOS transistors P1, P2, P3, and P4 of the first load circuit 322, respectively. The latch circuits L1, L2, L3, L4 are configured so that the terminals cross each other.

The first load circuit 322 includes PMOS transistors P1, P2, P3, and P4 P5. The PMOS transistors P1, P2, P3, and P4 are current paths respectively formed between a power supply voltage VCC and a source of the PMOS transistor P6 of the detection circuit 340 and the corresponding switch control signal. Have gates respectively controlled by S1, S2, S3, S4. The PMOS transistor P5 has a current path formed between the source voltage VCC and the source of the PMOS transistor P6 and a gate connected to the ground voltage VSS. The second load circuit unit 330 includes an inverting circuit 331, a second latch circuit unit 332, and a second load circuit 333, and controls the switch control signals S5, S6, S7, and S8. The detection voltage level of the detection circuit 340 is adjusted.

The inverting circuit 331 is inverters I1 connected between the switch control signal generating circuit 310 and the corresponding latch circuits L5, L6, L7, and L8 of the second latch circuit unit 332, respectively. , I2, I3, I4). The second latch circuit unit 332 may correspond to the corresponding inverters I1, I2, I3, and I4 of the inverting circuit 331 and the corresponding NMOS transistors N1, N2, and N3 of the second load circuit 333. And latch circuits L5, L6, L7, and L8, which are connected between N4 and are configured to cross each other. The second load circuit 333 includes NMOS transistors N1, N2, N3, N4, and N5. The NMOS transistors N1, N2, N3, and N4 are current paths respectively formed between the source of the NMOS transistor N6 of the detection circuit 340 and the ground voltage VSS and corresponding switch control. Have gates respectively controlled by signals S5, S6, S7, S8. The NMOS transistor N5 has a current path formed between the NMOS transistor N6 and the ground voltage VSS and a gate controlled by the power supply voltage VCC.

The detection circuit 340 includes MOS transistors P6 and N6 and an inverter In1, and the semiconductor is based on the detection voltage level adjusted by the first and second load circuit units 320 and 330. The voltage level of the substrate is detected. The PMOS transistor P6 has a current path formed between the first load circuit 320 and the node N1 and a gate connected to the semiconductor substrate. The NMOS transistor N6 has a current path formed between the node N1 and the second load circuit 330 and a gate connected to the power supply voltage VCC. An input terminal of the inverter In1 is connected to the node N1, and an output terminal is connected to the oscillation circuit 100.

2, the operation of the substrate bias voltage generation circuit of the present invention will be described.

Referring to FIG. 2, the substrate bias voltage generator circuit generates a substrate bias voltage VBB having a negative voltage level on a semiconductor substrate. The oscillation circuit 100 of the substrate bias voltage generation circuit outputs an oscillation signal CLK having a predetermined frequency under the control of the detection signal DS. The pumping circuit 200 lowers the voltage level of the semiconductor substrate to a predetermined negative voltage level by controlling the oscillation signal CLK. At this time, the detection circuit unit 300 detects whether the voltage level of the semiconductor substrate has a predetermined negative voltage level. That is, the detection circuit unit 300 detects whether the voltage level of the semiconductor substrate exceeds a predetermined negative voltage level and supplies the detection signal DS to the oscillation circuit 100 as a detection result. For example, when the voltage level of the semiconductor substrate exceeds the predetermined negative voltage level, the detection signal DS becomes logic high to stop the operation of the oscillation circuit 100. When the voltage level of the semiconductor substrate is lowered below the predetermined negative voltage level again, the detection signal DS becomes a logic low to operate the oscillation circuit 100.

However, when the substrate bias voltage VBB does not maintain the desired voltage level by the designer, the voltage level of the substrate bias voltage VBB is adjusted by adjusting the detection time point of the detection signal DS, that is, the detection voltage level. do. The switch control signal generation circuit 310 of the detection circuit unit 300 and the first and second load circuit units 320 and 330 function to adjust the detection voltage level. The switch control signal generation circuit 310 receives external input signals A0, A1, and A2, and controls the first and second load circuit parts 320 and 330 by controlling the control signal CON. It outputs the switch control signals (S1, S2, ..., S7, S8) for.

The first latch circuit part 321 of the first load circuit part 320 latches the corresponding switch control signals S1, S2, S3, and S4. The first load circuit 322 adjusts the detection voltage level by controlling the switch control signals S1, S2, S3, and S4 latched in the first latch circuit 321. The inversion circuit 331 of the second load circuit unit 330 inverts the corresponding switch control signals S5, S6, S7, and S8. The second latch circuit unit 332 latches the inverted switch control signals S5, S6, and S7 S8. The second load circuit 333 adjusts the detection voltage level by controlling the switch control signals S5, S6, S7, and S8 latched by the second latch circuit 332.

When the substrate bias voltage VBB does not have a desired voltage level, that is, when the substrate bias voltage VBB is lower than a desired negative voltage level, the predetermined switch input signal is input to the switch control signal generation circuit 310. Fields A0, A1, A2 and the control signal CON, the switch control signal generating circuit 310 corresponds to the input signals A0, A1, A2 and the control signal CON. The switch control signals S1, S2, ..., S7, S8 are output. The PMOS transistors P1, P2, P3, P4, and P5 have a function as a switch and a function as a resistor. In this case, the PMOS transistors P1, P2, P3, and P4 of the first load circuit 322 are turned on by controlling the switch control signals S1, S2, S3, and S4. )do. The PMOS transistors P1, P2, P3, and P4 are turned on, so that the PMOS transistors P1, P2, P3, P4, and P5 of the first load circuit 322 and the detection circuit 340 are turned on. The voltage-to-resistance ratio (V / R rate) of the PMOS transistor P6 is reduced to reduce the amount of charges charged to the node N1 of the detection circuit 340. As a result, the detection timing of the detection signal DS is delayed and the detection voltage level is increased, thereby increasing the substrate bias voltage VBB.

When the substrate bias voltage VBB is higher than a desired voltage level, when the predetermined input signals A0, A1, A2 and the control signal CON are applied to the switch control signal generation circuit 310, The switch control signal generation circuit 310 receives the switch control signals S1, S2,..., S7, S8 corresponding to the input signals A0, A1, A2 and the control signal CON. Output The NMOS transistors N1, N2, N3, N4, and N5 have a function as a switch and a function as a resistor. In this case, the NMOS transistors N1, N2, N3, and N4 of the second load circuit 333 are turned on by the control of the switch control signals S5, S6, S7, and S8. The NMOS transistors N1, N2, N3, and N4 are turned on so that the NMOS transistors N1, N2, N3, N4, and N5 of the second load circuit 333 and the detection circuit 340 are turned on. The voltage-to-resistance ratio of the NMOS transistor N6 is reduced to reduce the amount of charges discharged through the node N1 of the detection circuit 340. As a result, the detection timing of the detection signal DS is faster and the detection voltage level is lowered, thereby lowering the substrate bias voltage VBB.

The switch control signal generation circuit 310 of the substrate bias voltage generation circuit receives the predetermined input signals A0, A1, A2 and the control signal CON from the outside, and thus the switch control signals S1 and S2. S7 and S8 are supplied to the first and second load circuit parts 320 and 330. The first and second load circuit parts 320 and 330 adjust the detection voltage level of the detection circuit 340 by controlling the switch control signals S1, S2,..., S7 and S8. . The detection circuit 340 detects the voltage level of the semiconductor substrate based on the detection voltage level adjusted by the first and second load circuit units 320 and 330.

As described above, the detection voltage level is adjusted by external input signals, thereby adjusting the substrate bias voltage supplied to the semiconductor substrate.

Claims (6)

In a circuit for generating a substrate bias voltage of a semiconductor device formed on a semiconductor substrate: Pumping means connected to the semiconductor substrate and pumping charges to the semiconductor substrate in response to a predetermined oscillation signal; Detection means connected to the semiconductor substrate and detecting a voltage level of the semiconductor substrate on the basis of a predetermined detection voltage level varied by a control signal applied from the outside, and generating a detection signal as a detection result thereof; And oscillation means for generating the oscillation signal in response to the detection signal. The method of claim 1, The detection means, Switch control signal generating means for generating first and second group of switch control signals in response to the control signal; First load means connected to a power supply voltage, A switch connected between the first load means and a predetermined node for outputting the detection voltage and turned on / off according to the substrate bias voltage; A second load means connected between said node and a ground voltage, Wherein each resistance of the first and second load means is varied by corresponding first and second group of switch control signals such that the detected voltage level is varied. The method of claim 2, The first loading means, A first latch circuit portion for latching the first group of switch control signals; And a first load circuit varying the detected voltage level of the node in response to the latched first group of switch control signals. The method of claim 2, The second loading means, An inverting circuit unit for inverting the second group of switch control signals; A second latch circuit portion for latching the inverted second group of switch control signals; And a second load circuit that varies a voltage level of the detected voltage of the node in response to the latched second group of switch control signals. The method of claim 3, wherein The first load circuit, A plurality of PMOS transistors each having a current path formed between a power supply voltage and the node and gates respectively controlled by corresponding first control switch signals; And a PMOS transistor having a gate controlled by a current path and a ground voltage formed between the power supply voltage and the node. The method of claim 4, wherein The second load circuit, NMOS transistors having current paths respectively formed between the node and ground voltage and gates respectively controlled by corresponding second group of switch control signals, and And an NMOS transistor having a gate controlled by a power supply voltage and a current path formed between the node and the ground voltage.