KR20000006087U - Message bus sharing system - Google Patents

Abstract

The present invention relates to a message bus sharing system, and in particular, a message bus sharing that enables detachment of any subprocessor board from the message bus when an error is caused by any subprocessor board having a poor operation. It's about the system.

The message bus sharing system according to the present invention controls the message bus 30 and the message transmission operation signal controller 40 and the upper processor board 10 that transmits and receives data to and from the lower processor board 20 through the message bus 30. And a lower processor board 20 controlled by the upper processor board 10 to transmit and receive data to and from the upper processor board 10 through a message bus 30, and the upper processor board 10 and the lower processor board. The message bus 30, which is a transmission medium for transmitting and receiving data of 20, checks a normal state from the lower processor board 20, reports it to the upper processor board 10, and operates the lower processor board 20. And a message transmission operation signal control unit 40 for outputting a signal.

Description

Message bus sharing system

The present invention relates to a message bus sharing system. In particular, the message bus sharing system enables a separate bus bus board to be detached from the message bus when a message bus, which is a common bus, is abnormally caused by a bad bus processor board. It's about the system.

In general, a message bus sharing system composed of an upper processor board and one or more lower processor boards uses a message bus, which is a common bus, for data transmission and reception.

The prior art will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a message bus sharing system according to the related art.

The conventional message bus sharing system, as shown in FIG. 1, controls the lower processor board 2 and the message bus 3, and a higher processor that transmits and receives data to and from the lower processor board 2 by the message bus 3. A lower processor board (2) controlled by the upper processor board (1) and transmitting and receiving data to and from the upper processor board (1) by a message bus (3), and the upper processor board (1) And a message bus 3, which is a transmission medium through which data of the lower processor board 2 is transmitted and received.

The lower processor board 2 interfaces the message transfer bidirectional buffer unit 4 and the message transfer bidirectional buffer unit 4 and the message bus 3, where data of the upper processor board 1 is transmitted / received and stored. Interface bus (5), an internal message bus (6) for transmitting and receiving data within the board, and whether to transmit data of the message transfer bidirectional buffer unit (4) or receive data from the upper processor board (1). And a direction signal (7) for determining the transmission / reception direction of the data, and an operation signal (8) for operating the message transfer bidirectional buffer unit (4).

In the conventional message bus sharing system configured as described above, when the upper processor board 1 transmits / receives data with the lower processor board 2, the lower processor board 2 transmits / receives data with the upper processor board 1. The message transfer bidirectional buffer section 4 should be operated. At this time, the message transmission bidirectional buffer unit 4 is operated by the operation signal 8 and the direction of transmission and reception of data is determined by the direction signal 7 so that transmission and reception of data is performed on the message bus 3.

Here, the operation signal 8 is time-divided, assigned and applied by N, which is the number of lower processor boards 2. That is, when there are N lower processor boards 2, one lower processor board 2 applies the operation signal 8 to be a valid signal only for a time corresponding to one-Nth.

For example, in a message bus sharing system in which 16 lower processor boards 2 may be connected to one upper processor board 1, the upper processor board 1 allocates 2.048 ms of time for data transmission. If so, the 16 lower processor boards 2 are allotted time for data transfer by 2.048 ms ÷ 16 = 128 μs. Therefore, the lower processor board 2 transmits and receives data while the operation signal 8 becomes a valid signal for a time of 128 mu s, and also allocates 64 mu s to the data transmission and 64 mu s to the reception. In addition, each 64 μs, which is a time allocated for data transmission and reception, is transmitted and received by the direction signal 7, and it is determined whether or not data is to be transmitted or received by the message transmission bidirectional buffer unit 4. .

Meanwhile, in the conventional message sharing system, the bus transmission structure for transmitting and receiving data between the upper processor board 1 and the lower processor 2 is implemented by the message bus 3 which is a common bus, but only for transmitting and receiving data. As a configuration focused on, an error occurs in the message bus 3 when the message transfer bidirectional buffer unit 4 of the lower processor board 2 does not operate normally.

Therefore, if the message bus 3, which is a common bus, is abnormally generated by the lower processor board 2, the entire system cannot be operated normally. If any of the lower processor boards 2 is abnormal, the entire system operates properly. There was a problem that could not be done.

In addition, when the upper processor board 1 cannot grasp the operation state of the lower processor board 2 at all, and an error occurs in the message bus 3 by the lower processor board 2 having a poor function, the above function is performed. There was a problem that the system can be operated normally because the bad lower processor board (2) can not be separated.

The present invention has been made to solve the above-mentioned conventional problem, and the upper processor board can grasp the operation state of the lower processor board, and even if the error occurs due to the lower processor board in which the message bus, which is a common bus, is poor in operation, It is an object of the present invention to provide a message bus sharing system capable of separating a poorly operated lower processor board from a message bus.

1 is a configuration diagram of a message bus sharing system according to the prior art;

2 is a configuration diagram of a message bus sharing system according to the present invention;

3 is a detailed block diagram of a message transmission operation signal control unit according to the present invention.

Explanation of symbols on the main parts of the drawings

1, 10: upper processor board 2, 20: lower processor board

3, 30: message bus 4: message transfer bidirectional buffer unit

5, 22: interface bus 6: internal message bus

7: direction signal 8: operation signal

21: message transmission buffer 23: processor

24: watchdog circuit part 25: AND gate

26: internal operation signal 41: bidirectional buffer

42: first flip-flop 43: second flip-flop

44: control unit message bus 45: control unit operation signal

46: control unit direction signal 47: message transmission operation signal

48: steady state signal 49: inverter

In order to achieve the above object, the present invention controls a message bus and a message transmission operation signal control unit, and an upper processor board transmitting and receiving data to and from a lower processor board through a message bus, and controlled by the upper processor board through a message bus. A lower processor board that transmits and receives data to and from an upper processor board, a message bus that is a transmission medium for transmitting and receiving data between the upper processor board and the lower processor board, and checks a normal state from the lower processor board to report to a higher processor board. Provided is a message transfer sharing system including a message transfer operation signal controller for outputting a signal for operating a processor board.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram of a message bus sharing system according to the present invention, and FIG. 3 is a detailed configuration diagram of a message transmission operation signal controller of the present invention.

As shown in FIG. 2, the present invention controls the message bus 30 and the message transmission operation signal control unit 40, and the upper processor board for transmitting and receiving data to and from the lower processor board 20 through the message bus 30 ( 10) a lower processor board 20 controlled by the upper processor board 10 to transmit and receive data to and from the upper processor board 10 through a message bus 30, and the upper processor board 10 and lower nodes. The message bus 30 that transmits and receives data of the processor board 20 and the normal operation state of the lower processor board 20 are checked and reported to the upper processor board 10, and the lower processor board 20 is reported. And a message transmission operation signal control unit 40 for outputting a signal for operation.

The lower processor board 20 is an interface for interfacing the message transfer buffer unit 21, the message transfer buffer unit 21, and the message bus 30, where data of the upper processor board 10 is transmitted / received and stored. The processor unit 23 which controls the bus 22, the watchdog circuit unit 24, and the watchdog which outputs the result of periodically grasping the program execution of the processor unit 23 as the steady state signal 48. A circuit unit 24, an AND gate 25 for receiving the message transfer operation signal 47 and the internal operation signal 26 and logically multiply it and output the result to the message transfer buffer unit 20; The internal operation signal 26 which is an internal operation signal for operating the buffer part 21 is comprised.

The message transmission operation signal control unit 40 transmits and receives data to and from the upper processor board 10 through the control unit message bus 44 and transmits the control unit operation signal 45 and the control unit direction signal 46 from the upper processor board 10. A bidirectional buffer 41 that is applied as an input and receives an output signal 51 of the second flip-flop 43 and outputs a controller operation signal 45 to the first flip-flop 42; A first deflip-flop 42 and a steady state signal 48 for latching the output of the bidirectional buffer 41 to the input terminal D1 and outputting the latch to the lower processor board 20. A second deflip-flop 43 applied to the terminal D2 to be latched and output to the bidirectional buffer 41; a control unit message bus 44, which is a transmission medium for transmitting and receiving data to and from the upper processor board 10; Output from the processor board 10 and control the operation of the bidirectional buffer 41 The key functions as a control operation signal 45 which is a read / write signal of the upper processor board 10 and the direction of whether the bidirectional buffer 41 transmits or receives data from the upper processor board 10. And a control direction signal 46 applied to the first deflip-flop 42 as a clock function and inverted to the second deflip-flop 43 to a clock function. An inverter 49 for inverting the control direction signal 46 to be inputted as a clock of the flip-flop 43, and the control operation signal 45 is configured to generate the bidirectional buffer 41 and the first deflip-flop 42. And a steady state signal 48 that is output from the watchdog circuit section 24 and applied to the input of the first deflip-flop 43.

The message bus sharing system according to the present invention configured as described above operates as follows.

First, the upper processor board 10 reads the steady state signal 48 input to the message transmission operation signal control unit 40 through the control unit message bus 44 to confirm the normal state of the lower processor board 20. . The steady state signal 48 is an output signal of the watchdog circuit 24 of the lower processor board 20 and indicates whether the lower processor board 20 operates normally.

Next, when the lower processor board 20 operates normally, the upper processor board 10 effectively outputs the controller operation signal 45, and indicates whether the upper processor board 10 transmits or receives data. The control unit direction signal 46, which is a determination signal, is output. The bidirectional buffer 41 of the message transmission operation signal controller 40 receives the controller direction signal 46 to determine whether to transmit or receive data. The control direction signal 46 is also input to the clocks of the first and second deflip-flops 42, 43, and the control operation signal 45 is supplied to the bidirectional buffer 41 and the first deflip-flop 42. It is latched and outputted to become a message transfer operation signal 47. The message transmission operation signal 47 is logically multiplied with the internal operation signal 26 of the lower processor board 20 and input to the message transmission buffer unit 21. Here, the message transmission operation signal 47 is an operation signal output by the upper processor board 10, and the internal operation signal 26 is an operation signal generated and output by the lower processor board 20. When both signals are satisfied at the same time, the message transfer buffer unit 21 becomes operable. The internal operation signal 26 is time-divided and assigned by N, which is the number of lower processor boards 20, and is output. That is, when there are N lower processor boards 20, one lower processor board 20 outputs an internal operation signal 26 that is valid only for a time corresponding to one-Nth.

Here, the lower processor board 20 in which the output of the steady state signal 48 is not generated among the N lower processor boards 20 is a board not normally operating, and receives the steady state signal 48 of the board. Since the upper processor board 10 that detects the abnormal state of the lower processor board 20 outputs the control unit operation signal 45 as an invalid signal, the message transmission operation signal 47 also becomes invalid and eventually the message transmission buffer unit (21) does not work. Therefore, the lower processor board 20 having poor operation cannot transmit / receive data through the message bus 30 because the message transfer buffer unit 21 does not operate.

Therefore, the message bus 30 can always be normally operated, and since the lower processor board 20 which is poor in operation cannot transmit / receive data with the message bus 30, no abnormality occurs in the message bus 30. To be separated from the message bus 30.

As described above, the present invention enables the upper processor board to always know whether the lower processor board is normally operated and the message bus, which is a common bus, can always be normally operated, and the message bus is abnormal due to any lower processor board in which the operation is poor. When this happens, it is possible to separate any lower processor board from the message bus, so that the system can always operate stably.

Claims (3)

In a message bus sharing system having upper and lower processors, An upper processor board capable of sending and receiving data to and from the lower processor board via a message bus, A lower processor board controlled by the upper processor board and having a function of transmitting and receiving data to and from the upper processor board through a message bus; And a message transmission operation signal control unit configured to check a normal state of the lower processor board, report the signal to the upper processor board, and output a signal for operating the lower processor board. According to claim 1, The lower processor board may include a message transmission buffer unit having a function of transmitting and receiving and storing data of the upper processor board; A process unit having a function of controlling a watch dog circuit unit; A watch dog circuit unit having a function of periodically grasping the program execution of the processor unit as a steady state signal; And an AND gate having a function of receiving a message transmission operation signal and an internal operation signal as an input, and performing logical multiplication on the message transmission buffer unit and outputting the result to the message transmission buffer unit. According to claim 1, The message transmission operation signal control unit transmits and receives data to and from the upper processor board through the control unit message bus, receives the control unit operation signal and the control unit direction signal from the upper processor board as an input, receives the output signal of the second flip-flop, A bidirectional buffer having a function of applying a controller operation signal to a flip-flop; A first deflip-flop having a function of receiving an output of the bidirectional buffer through an input terminal and latching the output of the bidirectional buffer; A second deflip-flop having a function of applying a steady state signal to an input terminal and latching it to output the bidirectional buffer; And an inverter having a function of inverting a control direction signal to be input to the clock of the second flip-flop.