KR20000004725A - Electrostatic protection circuit of semiconductor devices - Google Patents

Abstract

PURPOSE: A circuit for protecting an electrostatic is provided to improve an electrostatic protecting capability by forming a low resistive metal film to the electrostatic protection circuit. CONSTITUTION: The circuit for protecting an internal circuit from external electrostatic connected to an input/output pad(10) comprises a first MOS transistor(22) connected between the input/output pad(10) and a power voltage(Vcc); and a second MOS transistor(24) having common drain connected to the first MOS transistor(22) and connected between the input/output pad(10) and a ground(GND); a pare of pick-up wells(228,248) formed in an N-well(220) and a P-well(240) of the first and second MOS transistors, respectively and for preventing currents from the input/output pad(10); and metal films(227,229,247,249) having a low resistivity formed on a source adjacent to the pick-up wells(228,248), respectively.

Description

Static electricity protection circuit of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection circuit of a semiconductor device. In particular, in the salicide process of a semiconductor device, a low-resistance metal thin film is formed in an electrostatic protection circuit of logic to effectively distribute transient currents from the outside, thereby improving electrostatic protection. And a static electricity protection circuit of a semiconductor device.

As the degree of integration of semiconductor memory devices increases and the size of devices becomes smaller, the reliability of integrated circuits against ESD (Electrostatic Discharge) is emerging as an important issue. This is because the submicron process technology makes the electrostatic discharge even worse by employing techniques such as thin oxide film, shallow junction, small contact area and short channel.

In the semiconductor device, in various cases, such as a manufacturing process or a distribution process, the device is often damaged by high voltage static electricity. The process of damaging a device by static electricity is divided into a human body model and a mechanical model. Recently, a charged device model (CDM), which is damaged by electric charges accumulated in a chip, is also considered.

To this end, the semiconductor device forms an electrostatic protection circuit in the current path of the input pad and the internal circuit to protect the internal circuit of the semiconductor device from pulses in which high voltage static electricity is discharged from the human body or an external object through the input pad. Internal circuits are protected by allowing pulses to be bypassed to ground or drive power.

In general, the static protection circuit of a logic circuit is composed of the active MOS transistors because of the small pad pitch. When a large amount of current is pumped, damage to a gate occurs frequently, so that a large amount of current is distributed. There was a limit. For this reason, some logic circuits use a silicon control rectifier (SCR) structure having a diode in the pad portion or an electrostatic protection circuit composed of field transistors. However, inserting this additional structure also suffered from limitations of pad pitch in logic circuits.

FIG. 1 is a diagram showing a static logic protection circuit of conventional logic, which is configured between the input pad 10 and the internal circuit 30, and the static electricity applied from the input pad 10 is applied to the power supply voltage Vcc. Drain in series with the drain of the PMOS transistor 22 to bypass the static electricity applied from the input pad 10 to the ground voltage GND. The NMOS transistor 24 is connected and the gate and the source are connected in common.

2 is a vertical cross-sectional view of the static electricity protection circuit of FIG. Referring to this, the PMOS transistor 22 of the electrostatic protection circuit has an n-type well in which a low concentration of n-type impurities is deeply implanted into a silicon substrate 2 on which a field oxide film 4 for defining an isolation region and an active region is formed. A drain 224 having a high concentration of p-type impurities in the gate 222 formed on the n-type well 220 and the n-type well 220 near the edge of the gate 222. And a pickup well 228 in which a high concentration of n-type impurities are injected into the n-type well 220 between the source 226 and the field oxide layer adjacent to the source 226.

In addition, the NMOS transistor of the static electricity protection circuit has a p-type well 240 in which p-type impurities are deeply injected at a low concentration adjacent to the n-type well 220, and a gate formed on the p-type well 240. 242, a drain 242 / source 246 in which a high concentration of n-type impurities are injected into the p-type well 240 near the edge of the gate 242, and a field oxide film adjacent to the source 246. It is composed of a pickup well 248 in which a high concentration of p-type impurities are injected into the p-type well 240.

Here, the input pad 10 is connected to the drain regions 224 and 244 of the PMOS and NMOS transistors 22 and 24, and the source regions 226 and 246 distribute current to each power line when a high voltage of static electricity is applied. The power supply voltage (Vcc) terminal and the ground voltage (GND) terminal are connected to each other.

The static electricity protection circuit of the logic circuit configured as described above is divided into a human body model and a mechanical model for testing. In this case, the test is applied to a power supply voltage mode for applying a positive voltage and a ground voltage mode for applying a negative voltage. That is, in the case of the PMOS transistor 22, current flowing from the input pad 10 flows through the drain 224 to the pickup well 228, and current flows from the source 226 to the drain 224. In the case of the NMOS transistor 24, a current flows from the drain 244 to the source 246, and a current flows from the pickup well 248 to the drain 244. Here, reference numerals Ia and Ib denote current paths of the PMOS transistor, and reference numerals Ia 'and Ib' denote current paths of the NMOS transistor.

3 is a diagram illustrating a parasitic resistance applied to a transistor constituting an electrostatic protection circuit, and reference numerals R1, R2, R3, R4, and R5 represent parasitic resistances applied to internal elements when current flows through a PMOS transistor. .

Referring to this, in order to distribute the current flowing in the pip to the input pad or the supply line of the supply voltage or the ground voltage, the total resistance value that contributes to the path of the entire current must be reduced.

To this end, the static electricity protection circuit of the logic circuit performs a silicide process of forming a low resistance metal thin film having a lower resistance value at the source / drain portion. However, the parasitic capacitance caused by the low-resistance metal thin film is generated in the drain directly connected to the input pad, thereby degrading the characteristics of the logic circuit requiring high-speed operation. In addition, when a high current is applied to the pad and a current flows from the drain to the source of the transistor, the temperature of the drain portion increases. At this time, if the low-resistance metal thin film is formed on the drain and the upper surface of the source, the thermal conductivity of the drain region is improved, causing thermal damage to the low-resistance metal thin film of the source.

Therefore, the static electricity protection circuit of the logic circuit can improve the current driving capability of the device by providing a low resistive metal thin film in the drain and source regions by the silicide process, but the thermal characteristics of the device can be improved by the low resistive metal thin film in the drain region. There was a problem of deterioration.

An object of the present invention is to solve the problems of the prior art as described above, while effectively distributing the transient current flowing from the outside of the semiconductor device can significantly improve the electrostatic discharge characteristics of the circuit without compromising the thermal characteristics of the device To provide a protection circuit.

Another object of the present invention is to provide an electrostatic protection circuit of a semiconductor device that can implement the current driving capability of the logic circuit in the same manner as the prior art without hindering the thermal characteristics of the device in order to solve the problems of the prior art as described above. have.

1 is a diagram showing an electrostatic protection circuit of conventional logic;

2 is a vertical cross-sectional view of the static electricity protection circuit by the line A-A 'shown in FIG.

3 is a diagram showing a parasitic resistance applied to a transistor constituting an electrostatic protection circuit;

4 is a vertical cross-sectional view showing an electrostatic protection circuit of a semiconductor device according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: input / output pad 22: PMOS transistor

24: NMOS transistor 30: internal circuit

2: silicon substrate 4: field oxide film

220: n well 240: p well

222, 242: gate 224, 244: drain

226,246 source 228, 248 pickup well

227, 229, 247, and 249: low resistance metal thin film

In order to achieve the above object, the present invention provides an electrostatic protection circuit connected to an input / output pad to protect an internal circuit from external static electricity, comprising: a first MOS transistor connected between the input / output pad and a power supply voltage, an input / output pad, and a ground; A second MOS transistor coupled between the first MOS transistor and a drain, the second MOS transistor being connected in common with the transistor source and the drain to block a current flowing from the pad in each of the low concentration impurity wells of the first and second MOS transistors. The pick-up well implanted with other conductive impurities and the source upper surface of the transistor adjacent to the well are each formed with a low-resistance metal thin film.

In the static electricity protection circuit of the present invention, the first MOS transistor is a p-channel MOS transistor, and the second MOS transistor is preferably an n-channel MOS transistor.

According to an aspect of the present invention, there is provided an electrostatic protection circuit connected to an input / output pad to protect an internal circuit from external static electricity, the first MOS transistor connected between the input / output pad and a power supply voltage, an input / output pad, A second MOS transistor connected between the ground voltage and the first MOS transistor and the drain in common, and having a transistor source and a drain to block current flowing from the pad in each of the low concentration impurity wells of the first and second MOS transistors. Is characterized in that a low resistance metal thin film is formed in each of the pickup wells into which the other conductivity type impurities are injected and the source upper surface of the transistor adjacent to the wells.

According to the present invention, there is a feature of improving the ESD protection characteristics by using the salicide process without inserting an additional structure into a protection circuit composed of an active transistor which is a basic ESD circuit in a logic circuit. In addition, by configuring ESD protection circuits without providing additional circuit structure, an effective ESD protection circuit can be configured without any limitation on pad pitch even on a chip requiring a large number of pads.

Since the low-resistance metal thin film is not selectively formed in the transistor drain region of the static electricity protection circuit, parasitic resistance applied to the drain when the transistor is driven can be reduced, thereby enabling high-speed operation of the circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a vertical cross-sectional view showing a static electricity protection circuit of the semiconductor device according to the present invention, and the same reference numerals are used because they are the same as the circuit configuration of FIG.

The electrostatic protection circuit of the present invention has a high concentration of p-type impurities in the gate 222 having the PMOS transistor 22 formed on the n-type well 220 and the n-type well 220 near the edge of the gate 222. The pick-up well 228 and the source 226 in which a high concentration of n-type impurities are injected into the n-type well 220 between the implanted drain 224 / source 226 and the source 226 and the adjacent field oxide layer. And low resistance metal thin films 227 and 229 formed on the top surface of the pickup well 228, respectively.

The NMOS transistor of the electrostatic protection circuit also has low resistance metal thin films 247 and 249 formed on the top surface of the source 246 and the pickup well 248, respectively.

Therefore, the present invention forms a low-resistance metal thin film only in the source and pickup well regions except the drain region in the silicide process, thereby reducing the parasitic capacitance of the drain region directly connected to the input pad while maintaining the operation characteristics of the logic circuit at high speed.

Meanwhile, in the above embodiment, the silicide process is selectively performed only on the high concentration impurity regions (source and pickup well) except the drain region. In the other embodiment, the low resistance is selectively selected only in the pickup EL region excluding the source and drain regions of the transistor. It is also possible to form a metal thin film.

As described above, in the present invention, since the low-resistance metal thin film by the silicide process is selectively provided only in the high concentration impurity region excluding the drain region, the thermal current characteristic of the drain region is reduced while improving the current driving capability of the device. To prevent.

Therefore, the present invention has the effect of greatly improving the electrostatic discharge characteristics of the circuit while effectively distributing the transient current introduced from the outside.

Claims (3)

In the static protection circuit connected to the input / output pad to protect the internal circuit from external static electricity, A first MOS transistor coupled between the input / output pad and a power supply voltage; And A second MOS transistor connected between the input / output pad and a ground voltage and commonly connected with the first MOS transistor and a drain; The pick-up well and the source top surface of the transistor adjacent to the well are implanted with a conductivity type impurity different from the transistor source and the drain to block the current flowing from the pad in each of the low concentration impurity wells of the first and second MOS transistors. A low-resistance metal thin film is formed, respectively. The static electricity protection circuit according to claim 1, wherein the first MOS transistor is a p-channel MOS transistor, and the second MOS transistor is an n-channel MOS transistor. In the static protection circuit connected to the input / output pad to protect the internal circuit from external static electricity, A first MOS transistor coupled between the input / output pad and a power supply voltage; And A second MOS transistor connected between the input / output pad and a ground voltage and commonly connected with the first MOS transistor and a drain; The pick-up well and the source top surface of the transistor adjacent to the well are implanted with a conductivity type impurity different from the transistor source and the drain to block the current flowing from the pad in each of the low concentration impurity wells of the first and second MOS transistors. A low-resistance metal thin film is formed, respectively.